Author: claimsbot

1. An apparatus for a power conversion system, the apparatus comprising:
a process-and-drive component configured to receive an input signal, process information associated with the input signal, and output a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system;
wherein:
the input signal includes a first pulse associated with a first input period and a second pulse associated with a second input period; and
the drive signal is associated with a first modulation period for the first input period and a second modulation period for the second input period;

wherein the process-and-drive component is further configured to:
determine the first modulation period for the first input period;
change the drive signal between a first logic level and a second logic level at a modulation frequency during the first modulation period;
determine the second modulation period for the second input period; and
change the drive signal between the first logic level and the second logic level at the modulation frequency during the second modulation period;

wherein:
the first pulse corresponds to a first pulse width;
the second pulse corresponds to a second pulse width;
the first modulation period corresponds to a first duration; and
the second modulation period corresponds to a second duration;

wherein:
the first pulse width and the second pulse width are different in magnitude; and
the first duration and the second duration are equal in magnitude.
2. The apparatus of claim 1 wherein:
the drive signal is associated with a first off-time period for the first input period and a second off-time period for the second input period;
wherein the process-and-drive component is further configured to:
keep the drive signal at the second logic level during the first off-time period; and
keep the drive signal at the second logic level during the second off-time period.
3. The apparatus of claim 1 wherein the switch is configured to be closed in response to the drive signal being at the first logic level and be opened in response to the drive signal being at the second logic level.
4. The apparatus of claim 1, further comprising:
a reference signal generator configured to receive the input signal and generate a reference signal based on at least information associated with the input signal;
an error amplifier configured to receive the reference signal and a current sensing signal and generate an amplified signal based on at least information associated with the reference signal and the current sensing signal;
a modulation component configured to generate a modulation signal based on at least information associated with the amplified signal; and
a drive component configured to generate the drive signal based on at least information associated with the modulation signal.
5. The apparatus of claim 4 wherein the reference signal generator includes:
a first logic control component configured to receive the input signal and generate a first signal based on at least information associated with the input signal; and
a reference signal modulator configured to receive the first signal and change the reference signal based on at least information associated with the first signal.
6. The apparatus of claim 5 wherein the drive component includes:
a second logic control component configured to receive the modulation signal and a dimming signal generated by the first logic control component and generate a second signal based on at least information associated with the modulation signal and the dimming signal; and
a gate driver configured to generate the drive signal based on at least information associated with the second signal.
7. The apparatus of claim 4 wherein the modulation component includes:
a multiplier configured to receive the amplified signal and the input signal and generate a multiplied signal based on at least information associated with the amplified signal and the input signal; and
a modulator configured to receive the multiplied signal and the current sensing signal and generate the modulation signal based on at least information associated with the multiplied signal and the current sensing signal.
8. The apparatus of claim 4 wherein the error amplifier is further configured to generate the amplified signal with a capacitor.
9. The apparatus of claim 1 wherein:
the first pulse width is smaller than the second pulse width;
the first pulse width corresponds to the first duration; and
the second pulse width is larger than the second duration.
10. The apparatus of claim 1 wherein:
the input signal includes a third pulse associated with a third input period;
the drive signal is associated with a third modulation period for the third input period;
the process-and-drive component is further configured to:
determine the third modulation period for the third input period;
change the drive signal between the first logic level and the second logic level at the modulation frequency during the third modulation period;
the third pulse corresponds to a third pulse width;
the third modulation period corresponds to a third duration;
the second pulse width and the third pulse width are different in magnitude; and
the second duration and the third duration are equal in magnitude.
11. An apparatus for a power conversion system, the apparatus comprising:
a process-and-drive component configured to receive an input signal, process information associated with the input signal, and output a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system;
wherein:
the input signal includes one or more input pulses and a first input pulse, the one or more input pulses corresponding to one or more input periods respectively, the first input pulse corresponding to a first input period, the first input period being after the one or more input periods;
the drive signal is associated with one or more modulation periods and a first modulation period, the one or more modulation periods corresponding to the one or more input periods respectively, the first modulation period corresponding to the first input period;

wherein:
the one or more input pulses are associated with one or more pulse widths respectively;
the process-and-drive component is further configured to:
process information associated with the one or more pulse widths;
select a first smallest pulse width from the one or more pulse widths;
determine a first duration of the first modulation period based on at least information associated with the first smallest pulse width; and
change the drive signal between a first logic level and a second logic level at a modulation frequency during the first modulation period.
12. The apparatus of claim 11 wherein:
the drive signal is associated with a first off-time period for the first input period; and
the process-and-drive component is further configured to keep the drive signal at the second logic level during the first off-time period.
13. The apparatus of claim 11 wherein the process-and-drive component is further configured to:
detect one or more phase angles associated with the one or more input pulses;
store the one or more phase angles into a queue;
select a smallest phase angle from the one or more phase angles, the smallest phase angle corresponding to the first smallest pulse width; and
determine the first duration based on at least information associated with the smallest phase angle.
14. The apparatus of claim 13 wherein the process-and-drive component is further configured to detect a first phase angle corresponding to the first input pulse and store the first phase angle into the queue.
15. The apparatus of claim 11 wherein the switch is configured to be closed in response to the drive signal being at the first logic level and be opened in response to the drive signal being at the second logic level.
16. The apparatus of claim 11, further comprising:
a reference signal generator configured to receive the input signal and generate a reference signal based on at least information associated with the input signal;
an error amplifier configured to receive the reference signal and a current sensing signal and generate an amplified signal based on at least information associated with the reference signal and the current sensing signal;
a modulation component configured to generate a modulation signal based on at least information associated with the amplified signal; and
a drive component configured to generate the drive signal based on at least information associated with the modulation signal.
17. The apparatus of claim 16 wherein the reference signal generator includes:
a first logic control component configured to receive the input signal and generate a first signal based on at least information associated with the input signal; and
a reference signal modulator configured to receive the first signal and change the reference signal based on at least information associated with the first signal.
18. The apparatus of claim 17 wherein the drive component includes:
a second logic control component configured to receive the modulation signal and a dimming signal generated by the first logic control component and generate a second signal based on at least information associated with the modulation signal and the dimming signal; and
a gate driver configured to generate the drive signal based on at least information associated with the second signal.
19. The apparatus of claim 16 wherein the modulation component includes:
a multiplier configured to receive the amplified signal and the input signal and generate a multiplied signal based on at least information associated with the amplified signal and the input signal; and
a modulator configured to receive the multiplied signal and the current sensing signal and generate the modulation signal based on at least information associated with the multiplied signal and the current sensing signal.
20. The apparatus of claim 16 wherein the error amplifier is further configured to generate the amplified signal with a capacitor.
21. The apparatus of claim 11 wherein:
the input signal includes a second input pulse, the second input pulse corresponding to a second input period, the second input period being after the first input period;
the drive signal is associated with a second modulation period, the second modulation period corresponding to the second input period;
the process-and-drive component is further configured to:
process information associated with the one or more pulse widths and the first pulse width;
select a second smallest pulse width from the one or more pulse widths and the first pulse width;
determine a second duration of the second modulation period based on at least information associated with the second smallest pulse width; and
change the drive signal between the first logic level and the second logic level at a modulation frequency during the second modulation period.
22.-40. (canceled)
41. A method for a power conversion system, the method comprising:
receiving an input signal including a first pulse associated with a first input period and a second pulse associated with a second input period;
processing information associated with the input signal; and
outputting a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system, the drive signal being associated with a first modulation period for the first input period and a second modulation period for the second input period;
wherein the processing information associated with the input signal includes:
determining the first modulation period for the first input period; and
determining the second modulation period for the second input period;

wherein the outputting a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system includes:
changing the drive signal between a first logic level and a second logic level at a modulation frequency during the first modulation period; and
changing the drive signal between the first logic level and the second logic level at the modulation frequency during the second modulation period;

wherein:
the first pulse corresponds to a first pulse width;
the second pulse corresponds to a second pulse width;
the first modulation period corresponds to a first duration; and
the second modulation period corresponds to a second duration;

wherein:
the first pulse width and the second pulse width are different in magnitude; and
the first duration and the second duration are equal in magnitude.
42. A method for a power conversion system, the method comprising:
receiving an input signal, the input signal including one or more input pulses and a first input pulse, the one or more input pulses corresponding to one or more input periods respectively, the first input pulse corresponding to a first input period, the first input period being after the one or more input periods;
processing information associated with the input signal; and
outputting a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system, the drive signal being associated with one or more modulation periods and a first modulation period;
wherein:
the one or more modulation periods correspond to the one or more input periods respectively;
the first modulation period corresponds to the first input period;
the one or more input pulses are associated with one or more pulse widths respectively;

wherein the processing information associated with the input signal includes:
processing information associated with the one or more pulse widths;
selecting a first smallest pulse width from the one or more pulse widths; and
determining a first duration of the first modulation period based on at least information associated with the first smallest pulse width; and

wherein the outputting a drive signal to a switch to affect a current that flows through a primary winding of a power conversion system includes changing the drive signal between a first logic level and a second logic level at a modulation frequency during the first modulation period.
43.-44. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A timing extraction device in an information reproduction device for extracting data and recording timing of the data from a received signal, comprising:
an asynchronous clock generator for generating an asynchronous clock which is asynchronous with data recording timing of the received signal;
an AD converter for converting the received signal which is an analog signal into a digital signal based on the asynchronous clock of the asynchronous clock generator;
an asynchronous timing detector for measuring an appearance interval of a specific pattern included in the digital signal from the AD converter based on the asynchronous clock of the asynchronous clock generator, and outputting the measured value which is the number of clock pulses of the asynchronous clock;
a phase controller for receiving the digital signal from the AD converter and calculating a phase error between the digital signal and the asynchronous clock generated by the asynchronous clock generator; and
a pseudo-synchronous clock generator for thinning the asynchronous clock of the asynchronous clock generator based on the specific pattern appearance interval measured by the asynchronous timing detector and the phase error calculated by the phase controller to generate a pseudo-synchronous clock which is pseudo-synchronous with the data recording timing.
2. The timing extraction device of claim 1, wherein
the asynchronous timing detector calculates a cycle ratio of the asynchronous clock to the synchronous clock based on the number of clock pulses of the asynchronous clock corresponding to the measured specific pattern appearance interval and a set number of clock pulses of a synchronous clock synchronous with data recording timing within the specific pattern appearance time interval, and
the pseudo-synchronous clock generator thins the asynchronous clock of the asynchronous clock generator based on the cycle ratio from the asynchronous timing detector and the phase error calculated by the phase controller.
3. The timing extraction device of claim 1, wherein
the asynchronous timing detector receives the digital signal and determines that a specific pattern has been detected if a ratio of the number of successive data \u201c1\u201ds to the number of successive data \u201c0\u201ds included in the digital signal is within a predetermined range.
4. The timing extraction device of claim 3, wherein
the asynchronous timing detector determines that a specific pattern has been detected only if a ratio of the number of successive data \u201c1\u201ds to the number of successive data \u201c0\u201ds is within a predetermined range and a total of the number of the successive \u201c1\u201ds and the number of the successive \u201c0\u201ds is within a predetermined range.
5. The timing extraction device of claim 1, comprising:
a synchronous timing detector for receiving the pseudo-synchronous clock generated by the pseudo-synchronous clock generator, and based on the pseudo-synchronous clock, measuring an appearance interval of a specific pattern included in the digital signal from the AD converter, and confirming whether or not the number of clock pulses of the pseudo-synchronous clock corresponding to the measured specific pattern appearance interval is equal to a set number of clock pulses of a synchronous clock synchronous with data recording timing within the specific pattern appearance time interval.
6. The timing extraction device of claim 1, wherein
the asynchronous clock generator generates an asynchronous clock having a fixed frequency.
7. The timing extraction device of claim 3, wherein
a ratio of the number of successive data \u201c1\u201ds and the number of successive data \u201c0\u201ds included in the digital signal is 14:4 in DVD-ROMs, 11:11 in CDs, and 2:9:9 in Blu-rays.
8. The timing extraction device of claim 3, wherein
the predetermined range is a range of a ratio in which there is a margin of \xb11 with respect to each of the number of successive data \u201c1\u201ds and the number of successive data \u201c0\u201ds.
9. The timing extraction device of claim 1, wherein
the set number of clock pulses of the synchronous clock within the specific pattern appearance time interval is 1488 in DVDs, 588 in CDs, and 1932 in Blu-rays.
10. The timing extraction device of claim 1, wherein
the phase controller includes a loop filter for smoothing a calculated phase error value.
11. The timing extraction device of claim 10, wherein
the loop filter includes an IIR digital filter.
12. The timing extraction device of claim 10, wherein
the loop filter includes an FIR digital filter.
13. The timing extraction device of claim 10, wherein
the loop filter calculates an average value of calculated phase errors in predetermined time intervals.
14. The timing extraction device of claim 10, wherein
the loop filter subjects a calculated phase error to gain multiplication with a specific value.
15. The timing extraction device of claim 1, wherein
a baseline controller for removing a DC offset included in the digital signal from the AD converter is provided between the AD converter and the asynchronous timing detector.
16. The timing extraction device of claim 1, wherein
a digital equalizer for amplifying a signal having a specific band of the digital signal from the AD converter is provided between the AD converter and the asynchronous timing detector.
17. The timing extraction device of claim 1, wherein
the asynchronous timing detector has a zero crossing detector operated based on the asynchronous clock of the asynchronous clock generator and for determining the polarities of two adjacent pieces of data in the digital signal from the AD converter.
18. The timing extraction device of claim 1, wherein
the asynchronous timing detector has an adder for receiving the asynchronous clock of the asynchronous clock generator, and based on the asynchronous clock, adding the number of clock pulses of the asynchronous clock.
19. The timing extraction device of claim 1, wherein
the phase controller has an adder and a multiplier for receiving the digital signal from the AD converter, and based on the asynchronous clock of the asynchronous clock generator, calculating a phase error in the digital signal from the AD converter.
20. A video display device comprising:
an LSI having the timing extraction device of claim 1 and a signal processing circuit for receiving the pseudo-synchronous clock obtained by the timing extraction device, and based on the pseudo-synchronous clock, decoding a received signal including audio data and video data; and
a display terminal for receiving a decoded signal from the LSI and displaying decoded video data while emitting decoded audio data.
21. The timing extraction device of claim 1, wherein
the received signal is supplied via a wireless communication channel or a communication channel including an optical fiber, a coaxial cable, or a power line.
22. The timing extraction device of claim 1, wherein
the received signal is supplied from an optical disc including a DVD disc, a CD disc, or a Blu-ray disc.

1. A piezoelectric crystal element for use in a sensor device for identifying at least one foreign material from environment, the crystal element comprising at least one crystal resonator in the form of an inverted mesa structure having a membrane-like region, which is substantially thinner as compared to end portion of the crystal resonator surrounding said membrane-like region and has a certain resonance frequency value, a surface region of said at least one crystal resonator being modified by reactive molecules of a kind capable of interacting with said at least one foreign material to yield a reaction product that effects a change in the resonance frequency of said membrane-like region from said certain resonance frequency value, said change being indicative of the identity and quantity of said at least one foreign material.
2. The element according to claim 1, wherein said at least one crystal resonator is a quartz crystal.
3. The element according to claim 1, wherein said at least one membrane-like region has a thickness of about several micrometers.
4. The element according to claim 1, wherein the membrane-like region of the at least one crystal resonator is coated with metal electrodes on opposite sides thereof, said electrodes being made of metal selected from Au, Pt and Al.
5. The element according to claim 4, wherein said electrodes are made of Au.
6. The element according to claim 4, wherein an Au-based glue is used for attaching the crystal element to a holder.
7. The element according claim 1, further comprising at least one additional crystal resonator in the form of an inverted mesa structure having a membrane-like region substantially thinner as compared to end portion of the additional crystal resonator surrounding said membrane-like region, and having a surface region modified by reactive molecules of a kind capable of interacting with a foreign material of the environment to yield a reaction product that effects a change in the resonance frequency of the additional membrane-like region.
8. The element according to claim 7, comprising an array of spaced-apart crystal resonators, each resonator being in the form of an inverted mesa structure formed with a pair of electrodes at opposite sides of the membrane-like region thereof and having the modified surface region, thereby defining an array of sensing regions excitable by the environment to produce the changes in the frequencies of crystal resonators.
9. The device according to claims 8, wherein a distance between each of the crystal resonators and its associated oscillator of the actuator utility is the same for all the crystal resonators.
10. The device according to claim 9, wherein the crystal resonators are arranged in spaced-apart relationship along a circular path, and are associated with the common oscillator located on a central axis of the circle.
11. The device according to claim 9, wherein the piezoelectric crystal element comprises a disc formed with a circular array of the piezoelectric quartz crystal resonators, and the actuator utility comprises the oscillator located in the center of the disc and associated with all the crystal resonators.
12. The device according to claim 9, wherein the piezoelectric crystal element comprises a disc formed with a circular array of the piezoelectric quartz crystal resonators, and the actuator utility comprises a plurality of oscillators located on said disc, each of the oscillators being associated with a corresponding one of the oscillators.
13. The element according to claim 7, wherein the surface regions of different crystal resonators are modified with different reactive molecules, thereby enabling detection of various foreign materials contained in the environment.
14. A piezoelectric sensor for use in a device for identifying at least one foreign material from environment, the piezoelectric sensor comprising the piezoelectric crystal element of any one of preceding claims with electrodes formed on opposite sides of said at least one membrane-like sensing region.
15. A piezoelectric sensor device for identifying at least one foreign material from environment, the device comprising the sensor of claim 14, and a control means operable for actuating said at least one crystal resonator, measuring the change in the resonance frequency of said at least one membrane-like region, and generating measured data indicative of the identity and quantity of said at least one foreign material.
16. The device according to claim 15, wherein the control means comprises an actuator utility for operating said at least one crystal resonator, and a detector utility for detecting the frequency of said at least one membrane-like region to enable the measurement of said change.
17. The piezoelectric crystal element according claim 1, wherein said reactive molecules form an organized, self-assembled monolayer (SAM), said monolayer consisting of receptor compounds comprising a linker that connects said compound to the surface of said substrate, an optional spacer, a structural element and an active head group.
18. The piezoelectric crystal element according claim 1, wherein said surface region of said at least one crystal resonator is modified by a polymeric layer.
19. The piezoelectric crystal element according to claim 18, wherein said polymeric layer comprises at least one polymeric material selected from the group consisting of: polypyrrole, polythiophene, polytriphenylene, poly(dimethylamino)pyrrole, polyaniline, poly(N-phenyl)aniline, poly(N-methyl)aniline, polyfluoroaniline, polypyrene, polyfluorene and polyfluoranthene.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of early starting the operation of a descrambler, comprising the steps of:
receiving a synchronous byte of a transport packet in a group of m packets, where m is an integer;
generating an alignment index to indicate a location of said synchronous byte;
delivering said alignment index to said descrambler; and
loading an initialization sequence to said descrambler in accordance with said alignment index and starting an operation of said descrambler.
2. The method, as recited in claim 1, wherein said loading said initialization sequence step is to load said initialization sequence to a pseudo-random binary sequence (PRBS) register in said descrambler.
3. The method, as recited in claim 1, wherein said initialization sequences in accordance with said alignment indexes are from a look-up table.
4. The method, as recited in claim 2, wherein said initialization sequences in accordance with said alignment indexes are from a look-up table.
5. A method of communicating data from a transmitter to a receiver comprising coding an input signal with n-bit codewords, where n is an integer, converting the n-bit codewords to a serial bit-stream, generating a fixed length bit pseudo-random binary sequence with a pseudo-random binary sequence generator in the transmitter, generating a synchronization byte in response to a predetermined location in each repetition of the pseudo-random binary sequence in said pseudo-random binary sequence generator of said transmitter, synchronizing the coding of said input signal in accordance with said synchronization byte, scrambling said serial bit-stream with said pseudo-random binary sequence, transmitting said scrambled data to the receiver, generating a corresponding binary sequence with a pseudo-random binary sequence generator of said receiver, generating a corresponding alignment index in response to the predetermined location in each repetition of said corresponding binary sequence, descrambling the data at the receiver with said corresponding binary sequence and different initialization sequences in accordance with said alignment indexes.