Author: claimsbot

1. A semiconductor device comprising:
a modulation circuit, a demodulation circuit, a logic circuit, a nonvolatile memory circuit, a level shift circuit, a control circuit, and an antenna circuit, which are formed over an insulating substrate,
wherein the modulation circuit and the demodulation circuit are electrically connected to the antenna circuit,
wherein the demodulation circuit is connected to the logic circuit,
wherein the logic circuit is connected to the control circuit and the level shift circuit,
wherein a signal inputted from the antenna circuit is operated by the logic circuit and inputted to the level shift circuit,
wherein the nonvolatile memory circuit includes means for storing an output signal of the level shift circuit,
wherein the nonvolatile memory circuit is for storing data by charge injection,
wherein the control circuit writes data to the nonvolatile memory circuit only once, and
wherein the nonvolatile memory circuit writes data in accordance with the instruction of the control circuit and the level shift circuit.
2. The semiconductor device according to claim 1, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a floating gate.
3. The semiconductor device according to claim 1, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a gate insulating film.
4. The semiconductor device according to claim 1, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained by rectifying and boosting the signal outputted from the antenna circuit.
5. The semiconductor device according to claim 1, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained from an external high voltage power supply.
6. The semiconductor device according to claim 1, wherein at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit is constituted by a thin film transistor.
7. The semiconductor device according to claim 1, wherein the insulating substrate is selected from the group consisting of a glass substrate, a plastic substrate and a film insulator.
8. The semiconductor device according to claim 1, wherein the antenna circuit is formed over at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit.
9. The semiconductor device according to claim 1, wherein a signal inputted to the antenna circuit is a wireless signal.
10. A product having the semiconductor device according to claim 1, wherein the product is selected from the group consisting of an IC card, an IC tag, an RFID, a transponder, a bill, a security, a passport, an electronic apparatus, a bag, and clothes.
11. The semiconductor device according to claim 1, wherein a thin film transistor in the logic circuit and a thin film transistor in the nonvolatile memory circuit are formed simultaneously.
12. The semiconductor device according to claim 1, wherein the logic circuit includes at least a switch and a volatile memory circuit.
13. The semiconductor device according to claim 12, wherein in the case of the switch is on, the signal is outputted to the level shift circuit.
14. The semiconductor device according to claim 1, wherein the control circuit writes only first data to the nonvolatile memory circuit.
15. A semiconductor device comprising:
a modulation circuit, a demodulation circuit, a logic circuit, a nonvolatile memory circuit, a level shift circuit, a control circuit, and an antenna circuit, which are formed over an insulating substrate,
wherein the modulation circuit and the demodulation circuit are electrically connected to the antenna circuit,
wherein the demodulation circuit is connected to the logic circuit,
wherein the logic circuit is connected to the control circuit and the level shift circuit,
wherein a signal inputted from the antenna circuit is operated by the logic circuit and inputted to the level shift circuit,
wherein the nonvolatile memory circuit includes means for storing an output signal of the level shift circuit,
wherein the nonvolatile memory circuit is for storing data by charge injection,
wherein the control circuit controls whether data can be written to the nonvolatile memory circuit or not depending on the data stored in the nonvolatile memory circuit, and
wherein the nonvolatile memory circuit writes data in accordance with the instruction of the control circuit and the level shift circuit.
16. The semiconductor device according to claim 15, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a floating gate.
17. The semiconductor device according to claim 15, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a gate insulating film.
18. The semiconductor device according to claim 15, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained by rectifying and boosting the signal outputted from the antenna circuit.
19. The semiconductor device according to claim 15, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained from an external high voltage power supply.
20. The semiconductor device according to claim 15, wherein at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit is constituted by a thin film transistor.
21. The semiconductor device according to claim 15, wherein the insulating substrate is selected from the group consisting of a glass substrate, a plastic substrate and a film insulator.
22. The semiconductor device according to claim 15, wherein the antenna circuit is formed over at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit.
23. The semiconductor device according to claim 15, wherein a signal inputted to the antenna circuit is a wireless signal.
24. A product having the semiconductor device according to claim 15, wherein the product is selected from the group consisting of an IC card, an IC tag, an RFID, a transponder, a bill, a security, a passport, an electronic apparatus, a bag, and clothes.
25. The semiconductor device according to claim 15, wherein a thin film transistor in the logic circuit and a thin film transistor in the nonvolatile memory circuit are formed simultaneously.
26. The semiconductor device according to claim 15, wherein the logic circuit includes at least a switch and a volatile memory circuit.
27. The semiconductor device according to claim 26, wherein in the case of the switch is on, the signal is outputted to the level shift circuit.
28. The semiconductor device according to claim 15, wherein the control circuit writes only first data to the nonvolatile memory circuit.
29. A semiconductor device comprising:
an antenna circuit;
a modulation circuit electrically connected to the antenna circuit;
a demodulation circuit electrically connected to the antenna circuit;
a logic circuit electrically connected to the demodulation circuit;
a nonvolatile memory circuit having means for storing an output signal of the logic circuit and for storing data by charge injection;
a control circuit capable of writing data to the nonvolatile memory circuit only once, and
a level shift circuit electrically connected to the nonvolatile memory circuit,
wherein the logic circuit is connected to the control circuit and the level shift circuit,
wherein a signal inputted from the antenna circuit is operated by the logic circuit and inputted to the level shift circuit, and
wherein the nonvolatile memory circuit writes data in accordance with the instruction of the control circuit and the level shift circuit.
30. The semiconductor device according to claim 29, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a floating gate.
31. The semiconductor device according to claim 29, wherein an element constituting the nonvolatile memory circuit stores data by charge injection into a gate insulating film.
32. The semiconductor device according to claim 29, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained by rectifying and boosting the signal outputted from the antenna circuit.
33. The semiconductor device according to claim 29, wherein a power supply used by the nonvolatile memory circuit for storing data is obtained from an external high voltage power supply.
34. The semiconductor device according to claim 29, wherein at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit is constituted by a thin film transistor.
35. The semiconductor device according to claim 29, wherein the insulating substrate is selected from the group consisting of a glass substrate, a plastic substrate and a film insulator.
36. The semiconductor device according to claim 29, wherein the antenna circuit is formed over at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the nonvolatile memory circuit.
37. The semiconductor device according to claim 29, wherein a signal inputted to the antenna circuit is a wireless signal.
38. A product having the semiconductor device according to claim 29, wherein the product is selected from the group consisting of an IC card, an IC tag, an REID, a transponder, a bill, a security, a passport, an electronic apparatus, a bag, and clothes.
39. The semiconductor device according to claim 29, wherein a thin film transistor in the logic circuit and a thin film transistor in the nonvolatile memory circuit are formed simultaneously.
40. The semiconductor device according to claim 29, wherein the logic circuit includes at least a switch and a volatile memory circuit.
41. The semiconductor device according to claim 40, wherein in the case of the switch is on, the signal is outputted to the level shift circuit.
42. The semiconductor device according to claim 29, wherein the control circuit writes only first data to the nonvolatile memory circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor structure comprising:
a conductive substrate;
a first semiconductor die and a second semiconductor die, wherein said first semiconductor die and said second semiconductor die are coupled to said conductive substrate, and wherein said first semiconductor die and said semiconductor die are separated by a trench;
a passivation layer on a front side of said first and said second semiconductor die, wherein said passivation layer covers a portion of said first semiconductor die and a portion of said second semiconductor die; and
a metal layer lining the bottom and walls of said trench and extending onto said passivation layer, wherein said metal layer lining leaves at least a portion of said passivation layer on said front side of said first and said second semiconductor die exposed.
2. The semiconductor structure as described in claim 1 wherein said front side of said first and said second semiconductor die comprise at least one connection pad.
3. The semiconductor structure as described in claim 2, wherein said metal layer is electrically insulated from said connection pad.
4. The semiconductor structure of claim 2 further comprising a second metal layer is in electrical contact with said connection pad.
5. The semiconductor structure as described in claim 1, wherein portions of said walls are in contact with at least a portion of said conductive substrate.
6. The semiconductor structure as described in claim 1, wherein a portion of said bottom of said trench is in contact with at least a portion of said conductive substrate.
7. The semiconductor structure as described in claim 1, wherein said first and said second exposed portions form a gate and a source for said first and said second semiconductor die.
8. The semiconductor structure as described in claim 7, wherein said source and said gate are formed on one side of said first and said second semiconductor die, and wherein a drain is formed on a side opposite to said side comprising said gate and said source.
9. The semiconductor structure as described in claim 1, wherein said metal layer further comprises a plurality of sub-layers.
10. The semiconductor structure as described in claim 1, wherein said first semiconductor die is a MOSFET.
11. The semiconductor structure as described in claim 1, wherein said first semiconductor die is a junction field effect transistor.
12. A semiconductor structure comprising:
a conductive substrate;
a plurality of semiconductor dice attached to the conductive substrate and attached to a passivation layer on a front side of each die, wherein rows of the dice are separated from each other by a plurality of parallel trenches; and
a metal layer lining the bottoms and walls of the trenches and extending onto the passivation layer.
13. The semiconductor structure of claim 12 wherein the front side of each die comprises at least one connection pad, the metal layer being electrically insulated from the connection pad.
14. The semiconductor structure of claim 12 comprising a second metal layer in electrical contact with the connection pad.

1. A roll of image-customized postage labels, said roll comprising:
a label roll core:
a length of label liner wound around the label roll core, said length of label liner comprising an upper liner surface, an underneath liner surface, a first end disposed on the label roll core, and a second dispensing end; and
a user-specified plurality of adhesive-backed, image-customized postage labels disposed on the upper liner surface of the length of label liner that is wound around the label roll core, each of said adhesive-backed, image-customized postage labels comprising an indication of postal-system-approved provider of Internet postage labels that produced the roll of image-customized postage labels, an upper label surface and an underneath label surface, wherein an adhesive is disposed on the underneath label surface of each adhesive-backed, image-customized postage label, said upper label surface of each adhesive-backed, image-customized postage label comprising a user-supplied customized image, a respective machine-readable, postal-system-approved, information-based postage indicia corresponding to a user-specified paid postage amount, and a human-readable postage indicia corresponding to the user-specified paid postage amount, said roll of image-customized postage labels configured for application of each of said adhesive-backed, image-customized postage labels to respective mail pieces, said user comprising an individual or entity other than the postal-system-approved provider.
2. The roll of claim 1, wherein an invisible fluorescent ink is disposed on a portion of the upper label surface of each adhesive-backed, image-customized postage label.
3. The roll of claim 1, wherein each adhesive-backed, image-customized postage label further comprises a user-specified height, a user-specified width, a top edge, a bottom edge, a left edge and a right edge, and wherein the customized image comprises a top, a bottom, a left side and a right side.
4. The roll of claim 3, wherein at least one edge is serrated, wherein the at least one edge is selected from the group consisting of: the top edge, the bottom edge, the left edge and the right edge.
5. The roll of claim 3, wherein the left edge of each adhesive-backed, image-customized postage label is adjacent to the left side of the customized image.
6. The roll of claim 5, wherein each respective adhesive-backed, image-customized postage label is disposed on the length of the label liner so that the left edge of the respective adhesive-backed, image-customized postage label is oriented toward the second dispensing end of the length of label liner, said respective machine-readable information-based postage indicia adjacent to the right edge of said adhesive-backed, image-customized postage label.
7. The roll of claim 1, said length of label liner further comprising single-label-width columns of postage labels spliced together, end-to-end.
8. The roll of claim 7, wherein each respective adhesive-backed, image-customized postage label is disposed on the length of the label liner so that a respective left edge of the respective adhesive-backed, image-customized postage label is oriented toward the second dispensing end of the length of label liner.
9. The roll of claim 1, said user-supplied customized image comprising a polychromatic user-supplied customized image.
10. A roll of image-customized postage labels, said roll comprising:
a label roil core;
a length of label liner wound around the label roll core, said length of label liner comprising an upper liner surface, an underneath liner surface, a first end disposed on the label roll core, and a second dispensing end; and
a user-specified plurality of adhesive-backed, image-customized postage labels disposed on the upper liner surface of the length of label liner that is wound around the label roll core, each of said adhesive-backed, image-customized postage labels comprising an indication of a postal-system-approved provider of Internet postage labels that produced the roll of image-customized postage labels, an upper label surface and an underneath label surface, wherein an adhesive is disposed on the underneath label surface of each adhesive-backed, image-customized postage label, said upper label surface of each adhesive-backed, image-customized postage label comprising a user-supplied customized image, a respective machine-readable, postal-system-approved, information-based postage indicia corresponding to a user-specified paid postage amount, and a human-readable postage indicia corresponding to the user-specified paid postage amount, said roll of image-customized postage labels configured for application of each of said adhesive-backed, image-customized postage labels to respective mail pieces by a high-speed postage application machine, said user comprising an individual or entity other than the postal-system-approved provider.
11. The roll of claim 10, said user-supplied customized image comprising a polychromatic user-supplied customized image.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A fluoropolymer fiber comprising an improved hydrophilicity and a surface deformation configured for providing the improved hydrophilicity.
2. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a tear in the fluoropolymer fiber.
3. The fluoropolymer fiber according to claim 2 wherein the tear is a split.
4. The fluoropolymer fiber according to claim 2 wherein the tear is a plurality of splits.
5. The fluoropolymer according to claim 4 wherein the tear forms a plurality of strands.
6. The fluoropolymer fiber according to claim 5 wherein the plurality of strands provides an end of the fluoropolymer fiber with a frayed appearance.
7. The fluoropolymer fiber according to claim 2 wherein the tear is a slit.
8. The fluoropolymer fiber according to claim 1 wherein the surface deformation extends along a grain of the fluoropolymer fiber.
9. The fluoropolymer fiber according to claim 1 wherein surface deformation extends substantially longitudinally along an exterior surface of the fluoropolymer fiber.
10. The fluoropolymer fiber according to claim 1 wherein the surface deformation includes an exposed interior surface of the fluoropolymer fiber.
11. The fluoropolymer fiber according to claim 10 wherein the exposed interior surface includes a fibril-like member extending outwardly therefrom.
12. The fluoropolymer fiber according to claim 11 wherein the fibril-like member is bent.
13. The fluoropolymer fiber according to claim 1 wherein the improved hydrophilicity is UV light resistant.
14. The fluoropolymer fiber according to claim 1 wherein the improved hydrophilicity is resistant to humidity.
15. The fluoropolymer fiber according to claim 1 wherein the improved hydrophilicity is resistant to temperature.
16. The fluoropolymer fiber according to claim 1 wherein the fluoropolymer fiber is a polytetrafluoroethylene fiber between about 127 microns and about 1115,000 microns in length.
17. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a split having a length that is equal to between 1% and 100% of a length of the fluoropolymer fiber.
18. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a tear having a length that is equal to between 5% and 90% of a length of the fluoropolymer fiber.
19. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a tear having a length that is equal to between 10% and 80% of a length of the fluoropolymer fiber.
20. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a tear having a depth that is greater than 0.5 micron.
21. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a tear having a depth that is greater than 2.5 microns.
22. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a slit having a depth that is greater than 10% of an average width of the fluoropolymer fiber.
23. The fluoropolymer fiber according to claim 1 wherein the surface deformation is a slit having a depth that is greater than 25% of an average width of the fluoropolymer fiber.
24. A fluoropolymer fiber comprising,
an elongate body having a first end and a second end,
a split extending through the first end of the elongate body,
a slit in the elongate body, and
an improved hydrophilicity.
25. The fluoropolymer fiber according to claim 24 wherein the fluoropolymer fiber is a polytetrafluoroethylene fiber.
26. The fluoropolymer fiber according to claim 24 wherein the fluoropolymer fiber is a floc fiber.
27. The fluoropolymer fiber according to claim 24 wherein the fluoropolymer fiber is a staple fiber.
28. The fluoropolymer fiber according to claim 24 wherein the split includes a first elongate portion partially removed from a surface of the elongate body, the first elongate portion having a first end coupled to the elongate body and a second free end.
29. The fluoropolymer fiber according to claim 28 wherein the split includes a second portion including an exposed interior surface of the elongate body.
30. The fluoropolymer fiber according to claim 29 wherein the exposed interior surface is rougher than an exterior surface of the fluoropolymer fiber and includes a plurality of outwardly extending, fibril-like, curved members.
31. The fluoropolymer fiber according to claim 24 wherein the split extends through the second end.
32. The fluoropolymer fiber according to claim 24 wherein the split has a length that is equal to between 2% and 75% of a length of the fluoropolymer fiber.
33. The fluoropolymer fiber according to claim 24 wherein the split has a length that is equal to between 15% and 60% of a length of the fluoropolymer fiber.
34. The fluoropolymer fiber according to claim 24 wherein the slit has a depth that is greater than 0.75 micron.
35. The fluoropolymer fiber according to claim 24 wherein the slit has a depth that is greater than 2.0 microns.
36. A hydrophilic fluoropolymer fiber comprising a slit, a split end, an exposed interior fluoropolymer fiber surface and a plurality of fibril-like members extending outwardly from the exposed interior surface.
37. The fluoropolymer fiber according to claim 36 wherein the slit has a depth of at least 0.8 micron.
38. The fluoropolymer fiber according to claim 36 wherein the slit has a depth that is greater than 10% of an average width of the fluoropolymer fiber.
39. The fluoropolymer according to claim 36 wherein the split has a length that is equal to between 10% and 100% of a length of the fluoropolymer fiber.
40. The fluoropolymer according to claim 36 wherein the split end appears frayed.
41. The fluoropolymer fiber according to claim 36 wherein the fluoropolymer floc is an expanded fluoropolymer fiber.
42. The fluoropolymer fiber according to claim 36 wherein the fluoropolymer fiber is a polytetrafluoroethylene floc fiber or a polytetrafluoroethylene staple fiber.