Author: claimsbot

1. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor,
a second layer composed of a group III nitride semiconductor, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein a channel is formed in at least one of: (1) the first layer, (2) the second layer, (3) the region between the first layer and the second layer; and
wherein the conductivity type of the second layer is inversed with respect to the conductivity type of carriers flowing in the channel.
2. The semiconductor device as described in claim 1, wherein the second layer is in contact with an electrode for leading out carriers with the conductivity type inversed with respect to that of the carriers flowing in the channel from the device.
3. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer, and the first layer and the second layer are in contact with each other; and
wherein the band gap of the first layer is larger than the band gap of the second layer.
4. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type,
a third layer composed of a group III nitride semiconductor of the first conductivity type, and a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein the third layer has a region formed between the first layer and the second layer; and
wherein the band gap of the third layer is less than the band gap of the first layer.
5. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type,
a third layer composed of a group III nitride semiconductor, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer;
wherein the third layer has a region formed between the first layer and the second layer; and
wherein the band gap of the third layer is less than the band gap of the first layer and the second layer.
6. The semiconductor device as described in claim 5, wherein the third layer is composed of a substantially true group III nitride semiconductor.
7. A semiconductor device comprising:
a first layer composed of a group III nitride semiconductor of a first conductivity type,
a second layer composed of a group III nitride semiconductor of a second conductivity type, and
a gate electrode,
wherein the first layer has a region formed between the gate electrode and the second layer; and
wherein the thickness of the first layer is not more than the thickness of a depleted layer extending from a boundary between the first layer and the second layer to the first layer side when no electric voltage is applied to the gate electrode.
8. A field-effect transistor comprising:
a gate electrode,
a first layer composed of a group III nitride semiconductor of a first conductivity type, and
a second layer composed of a group III nitride semiconductor of a second conductivity type located on a side of the first layer opposite to the gate electrode.
9. The field-effect transistor as described in claim 8, wherein the first layer and second layer are in direct contact with each other, and the band gap of the first layer is larger than the band gap of the second layer.
10. The field-effect transistor as described in claim 8, wherein a third layer having a band gap smaller than the band gaps of the first layer and the second layer is located between the first layer and second layer.
11. The field-effect transistor as described in claim 10, wherein the third layer is composed of a true group III nitride semiconductor.
12. The field-effect transistor as described in claim 8, wherein a third layer composed of a group III nitride semiconductor of the first conductivity type and having a band gap smaller than the band gap of the first layer is located between the first layer and second layer.
13. The field-effect transistor as described in claim 8 that operates in a normally off condition, wherein a depleted layer expanding from the second layer to the first layer depletes the entire first layer when no electric voltage is applied to the gate electrode.
14. The field-effect transistor as described in claim 13, further comprising a gate insulating film disposed between the gate electrode and the first layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A parasitic element extracting apparatus comprising:
wire congestion calculating means for calculating a degree of wire congestion in a wiring area, which is placed in a layout of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area;
dummy wiring area judging means for pre-setting a reference degree of the wire congestion relating to the arrangement of dummy wire, and comparing the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means with the reference degree of the wire congestion to judge whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated by the wire congestion calculating means;
dummy wiring assuming means for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means in cases where it is judged by the dummy wiring area judging means that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area; and
parasitic element extracting means for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.
2. A parasitic element extracting apparatus according to claim 1, wherein information of wire capacitance andor inductance is extracted as the information of the parasitic element of the semiconductor circuit by the parasitic element extracting means, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged.
3. A parasitic element extracting apparatus according to claim 1, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates.
4. A parasitic element extracting apparatus according to claim 1, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability.
5. A parasitic element extracting method comprising:
a wire congestion calculating step for calculating a degree of wire congestion in a wiring area of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area;
a dummy wiring area judging step for comparing the degree of the wire congestion calculated in the wire congestion calculating step with a reference degree of the wire congestion relating to the arrangement of dummy wire, and judging whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated in the wire congestion calculating step;
a dummy wiring assuming step for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area calculated in the wire congestion calculating step in cases where it is judged in the dummy wiring area judging step that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area; and
a parasitic element extracting step for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.
6. A parasitic element extracting method according to claim 5, wherein information of wire capacitance andor inductance is extracted as the information of the parasitic element of the semiconductor circuit in the parasitic element extracting step, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged.
7. A parasitic element extracting method according to claim 5, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates.
8. A parasitic element extracting method according to claim 5, wherein a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability.

1. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for providing accelerated data storage and retrieval, said method steps comprising:
receiving a data stream at an input data transmission rate which is greater than a data storage rate of a target storage device;
compressing the data stream at a compression rate that increases the effective data storage rate of the data storage device; and
storing the compressed data stream in the target storage devices,
wherein the input data stream comprises one or more data blocks, and
wherein the instructions for performing compression comprise instructions for:
(a) compressing an input data block with a plurality of encoders to provide a set of encoded data blocks;
(b) determining a compression ratio for each of the encoded data blocks;
(c) comparing each compression ratio with an a priori specified compression threshold;
(d) selecting for output an encoded data block in the set having the highest compression ratio and appending a corresponding descriptor, if at least one of the compression ratios exceeds the a priori specified compression threshold; and
(e) repeating steps (a) through (d) for each successive input data block.
2. The program storage device of claim 1, wherein the compression rate is at least equal to the ratio of the input data transmission rate to the data storage rate so as to provide continuous storage of the input data stream at the input data transmission rate.
3. The program storage device of claim 1, further including instructions for performing the steps of:
determining the input data transmission rate and the data compression rate;
comparing the input data transmission rate, the data compression rate and the data storage rate to determine if they are compatible; and
adjusting one or more parameters to obtain compatibility between the input data transmission rate, the data compression rate and the data storage rate, if they are determined to be incompatible.
4. The program storage device of claim 3, wherein the instructions for performing the adjusting step include instructions for performing one of adjusting the input data transmission rate, adjusting the compression rate and a combination thereof.
5. The program storage device of claim 4, wherein the instructions for performing the adjusting step further include instructions for temporarily buffering one of the input data stream, the compressed data stream, and a combination thereof.
6. The program storage device of claim 1, further including instructions for performing the steps of:
retrieving the compressed data stream from the target storage device at a rate equal to a data access rate of the target storage device; and
decompressing the compressed data at a decompression rate that increases the effective data access rate of the target storage device.
7. The program storage device of claim 6, wherein the decompression rate is equal to the ratio of the data access rate to the input data transmission rate so as to obtain an output data transmission rate which is equal to the input data transmission rate.
8. The program storage device of claim 6, wherein the decompression rate is equal to or greater than the ratio of the data access rate to a maximum accepted output data transmission rate so as to provide a continuous and optimal data output transmission rate.
9. The program storage device of claim 6, further including instructions for performing the steps of:
determining the data retrieval rate and the data decompression rate;
comparing the data retrieval rate, the data decompression rate and the output data transmission rate to determine if they are compatible; and
adjusting one or more parameters to obtain compatibility between the data retrieval rate, the data decompression rate and the output data transmission rate if they are determined to be incompatible.
10. The program storage device of claim 9, wherein the instructions for performing the adjusting step include instructions for performing one of adjusting the data retrieval rate, adjusting the decompression rate, and a combination thereof.
11. The program storage device of claim 9, wherein the instructions for performing the adjusting step include instructions for temporarily buffering one of the retrieved data stream, the decompressed data stream, and a combination thereof.
12. The program storage device of claim 1, further including instructions for selecting for output the input data block and appending a null descriptor to the input data block if all of the compression ratios of the corresponding encoded data blocks fall below the a priori compression limit.
13. The program storage device of claim 1, wherein the instructions for the compressing step include instructions for simultaneously compressing the data block with a plurality of encoders in parallel.
14. The program storage device of claim 1 wherein the instructions for performing the compressing step include instructions for sequentially compressing the data block with the plurality of encoders.
15. The program storage device of claim 6, wherein the instructions for performing the decompressing step include instructions for performing the steps of:
(a) extracting an encoding type descriptor from an input data block;
(b) decompressing the data block in accordance with a decoder corresponding to the extracted descriptor; and
(c) repeating steps (a) and (b) for each successive input data block.
16. The program storage device of claim 15, further including instructions for outputting the input data block if the extracted descriptor is a null descriptor.
17. A method for providing accelerated data storage and retrieval, comprising:
receiving a data stream at an input data transmission rate which is greater than a data storage rate of a target storage device;
compressing the data stream at a compression rate that increases the effective data storage rate of the data storage device; and
storing the compressed data stream in the target storage device,
wherein the input data stream comprises one or more data blocks, and
wherein the instructions for performing compression comprise instructions for:
(a) compressing an input data block with a plurality of encoders to provide a set of encoded data blocks;
(b) determining a compression ratio for each of the encoded data blocks;
(c) comparing each compression ratio with an a priori specified compression threshold;
(d) selecting for output an encoded data block in the set having the highest compression ratio and appending a corresponding descriptor, if at least one of the compression ratios exceeds the a priori specified compression threshold; and
(e) repeating steps (a) through (d) for each successive input data block.
18. The method of claim 17, wherein the compression rate is at least equal to the ratio of the input data transmission rate to the data storage rate so as to provide continuous storage of the input data stream at the input data transmission rate.
19. The method of claim 17, further comprising the steps of:
determining the input data transmission rate and the data compression rate;
comparing the input data transmission rate, the data compression rate and the data storage rate to determine if they are compatible; and
adjusting one or more parameters to obtain compatibility between the input data transmission rate, the data compression rate and the data storage rate, if they are determined to be incompatible.
20. The method of claim 19, wherein adjusting comprises one of adjusting the input data transmission rate, adjusting the compression rate and a combination thereof.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A game board device for directing body movement in games or exercise comprising,
at least one support frame, all such frames employed together defining a suitable game board of limited area;
a plurality of contact surfaces of relatively the same size and shape and providing part of modular units of generally rectangular shape and of generally the same size supported side by side relative to one another by one another within and filing each support frame employed, in a coordinated matrix pattern so that all the contact surfaces in each frame lie generally in a common plane and provide a continuous matrix of contact surfaces sufficiently close to one another that a player may move a selected body extremity from any contact surface in the matrix to any other without stepping up or down out of the general common plane, and
illumination means which is normally-off for each module to separately and selectively illuminate each of the respective contact surfaces individually to cue movement to contact a newly illuminated contact surface by a selected body extremity, and
switching means to selectively connect the illumination means for various contact surfaces to a power source to control the sequence of illumination of a selected contact surface whereby a player is cued to move his selected body extremities to each newly illuminated contact surface as different selected contact surfaces in turn become illuminated and to turn off the illuminated surface at a predetermined time after contact has been made to keep dark the contact surfaces when they are not immediate in play.
2. The device of claim 1 in which there are a plurality of support frames which fit together and can be secured relative to one another so that positions of contact surfaces remain fixed but may be separated and stacked together relative to one another for compactness and portability when not in use.
3. The device of claim 1 in which the rigid frame members are hinged together to permit folding and unfolding to provide the continuous matrix of contact surfaces.
4. The device of claim 1 in which separately energized illumination means is incorporated within each modular unit, the contact surfaces of which are each arranged to be illuminated by its illumination means principally and distinctly that contact surface.
5. The device of claim 1 in which the contact surface of each modular unit displays one color with at least two different colors being used and distributed around the contact surfaces.
6. The device of claim 5 in which the various contact surfaces, when illuminated, display many different colors distributed around the contact surfaces with contact surfaces of the same color being separated from each other.
7. The device of claims 6 in which separate illumination means are beneath the contact surfaces which are translucent to display the color of the illumination selected for that contact surface.
8. The device according to claim 1 wherein the means to control the sequence of illumination is provided with switching means enabling the sequence and timing of illumination of contact surfaces to be remotely controlled.
9. The device of claim 8 in which the switching means comprises at least as many individual manually actuated switches as there are illuminating means arranged together for the convenience of human operation.
10. The device of claim 9 in which switching means include individually manually controlled switch actuators arranged in a pattern corresponding to the configuration of the contact surfaces, with each actuator arranged in a relative position corresponding to the position of the contact surface in the pattern which it will illuminate.
11. The device of claim 10 in which the configuration of contact surfaces and of actuator for switching means, respectively, is a rectangular matrix having positioned switch actuator means in the same relative positions in regular rows and columns as the contact surfaces they are used to illuminate.
12. The device of claim 8 in which the switching means involves switches arranged to be sequentially activated by a moving actuator.
13. The device of claim 12 in which the moving actuator is capable of various patterns of movement.
14. The device of claim l2 in which the moving actuator is confined to a specific path but can be moved in either direction along the path.
15. The device of claim 14 in which the moving actuator is a slide confined to linear movement along a linear array of switches.
16. The device of claim 12 in which the moving actuator provides a common switch contact completing a circuit through switch contacts to complete a power circuit to illumination means which successively light various contact surfaces.
17. The device of claim 16 in which the actuator includes a sliding conductor bridging a continuous conductor serving as a common electrode for multiple switches and a commutator providing separate contacts for each means of illumination.
18. The device of claim 1 in which the game board is divided into parts which may be folded relative to one another for portability and storage.
19. The device of claim 1 in which at least one illumination means is incorporated as part of the structure associated with each contact surface.
20. The device of claim 19 in which the illumination means is provided beneath each contact surface and the surfaces are translucent.
21. The device according to claim 1 wherein the illuminating means is controlled by computer in such a way that the illumination switching will be changed as directed by a computer program.
22. The device according to claim 21 wherein the switching means is controlled by a computer wherein the program will randomly change the sequence of illumination.
23. The device according to claim 21 wherein the switches for the illuminating means may be set to activate in a repeatable sequence and that sequence may be changed to produce other desired sequences by the program.
24. The device according to claim 23 wherein said control means is adjustable to vary the frequency of change.
25. A method of game playing involving stepping from one illuminated contact surface to another where the contact surfaces are arranged in a repetitive pattern fully covering a predetermined game surface area in a common plane compactly so that the player can step from any contact surface to any other in the game area with ease, and the contact surfaces being illuminated one contact surface at a time to provide the player with the only clue as to where he should next step comprising;
lighting a first contact surface as the cue to where the player should step;
lighting a next contact surface as the cue to where the player should next step, while discontinuing the lighting of the previous surface,
repeating the second step of the process for as many steps as desired by lighting sequentially different contact surfaces at random and discontinuing the lighting of each lighted contact surface when the player leaves it for a total number of successive steps onto lighted contact surfaces as desired.
26. The method of claim 25 in which the rate of lighting changes is varied during play and the pattern of changes is varied for each player.
27. The method of claim 25, in which the player is graded on the number of hits or the number of misses in a total number of sequential contact surface illuminations during the period of the game.
28. A method of providing therapy involving moving alternative body extremities from one illuminated contact surface to another where the contact surfaces are arranged in a repetitive pattern fully covering a predetermined surface area in a common plane sufficiently compactly that the patient can move alternate body extremities from one contact surface to another over a selected area with ease, comprising,
placing the patient receiving therapy in a position to contact the contact surfaces alternating with a selected pair of extremities,
illuminating a first contact surface to cue placing a selected extremity on that illuminated surface;
lighting a next contact surface to cue the patient to place his other selected extremity there while extinguishing the light on the first contact surface,
providing a sequence of lighting of contact surfaces, and extinguishing the lighting of the last previously contacted surface to cue movement of the patient for the therapy alternating movement of the selected extremities, and continuing the process for a period prescribed for the therapy while timing successive lighting cues at rates prescribed by the therapy to achieve the desired exercise results.
29. A device for directing body movement in games or exercise comprising,
a game board providing generally planar contact surfaces arranged in a coordinated pattern for hand or foot contact which contact surfaces are sufficiently large to accommodate the playing extremities of an anticipated largest player so that it is possible for players to contact each contact surface with a hand or foot without also contacting an adjacent contact surface,
illumination means to separately and selectively illuminate each of the respective contact surfaces, and
means to provide and control the sequence of illumination of the contact surfaces, so that newly illuminated surfaces are lighted no more than two at a time and extinguished after the player contacts the lighted area in order to avoid confusion,
whereby a player is directed to move his selected body extremity to a newly illuminated contact surface as the surface, in turn, become illuminated.
30. The device of claim 29 in which the contact surfaces are part of a game board and have fixed positions specific relative to one another on the game board.