1. A microbolometer or thermopile comprising a substrate and a light detector, wherein the light detector comprises ordered arrays of nanomaterial embedded in a matrix that enhances light absorption and releases heat for enhanced sensitivity.
2. The device according to claim 1, wherein the nanomaterial comprises nanorods, nanospheres or nanocrystals.
3. The device of claim 2 wherein the nanomaterial comprises aligned nanorods.
4. The device of claim 3 wherein the aligned nanorods are gold nanorods.
5. The device of claim 4 wherein the gold nanorods have an aspect ratio greater than two.
6. The device of anyone of claims 1-5 wherein the substrate is a monocrystalline silicon wafer or an organic thin film.
7. The device of claim 4 or 5 wherein spacing between adjacent nanorods is between 10 and 50 nm.
8. The microbolometer of claim 1 having a size of 3-50 microns square.
9. In a thermal photodetector comprising a mircrobolometer or thermopile, the improvement wherein the mircrobolomeer or thermopile is in accordance with claim 1.
10. In a thermal imaging camera or an infra-red camera comprising a thermal photodetector, the improvement wherein the thermal photodetector is in accordance with claim 9.
11. A method of integrating a nanomaterial in an electro-optical device for enhanced sensitivity, the method comprising:
providing a substrate;
forming on the substrate a conductive matrix which sandwiches an ordered array of nanomaterials, and
connecting the matrix and the ordered array of nanomaterials to two separate conductive layers to form an electro-optical device,
wherein the plurality of ordered arrays of nanomaterials operably change the conductivity of the matrix.
12. The method according, to claim 11, wherein the nanomaterial is homogenously integrated in planar form as a monolayer.
13. The method of claim 11, wherein the nanomaterial is hormogenously integrated in a planar form as a multilayer.
14. The method of any one of claim 12 or 13, wherein the nanomaterial comprises nanorods, nanospheres, nanoshells or nanocrystals.
15. The method of claim 14 wherein the nanomateriai comprises aligned nanords.
16. The method of claim 15 wherein the aligned nanorods are gold nanorods.
17. The method of claim 16 wherein the gold nanorods have an aspect ratio greater than two.
18. The method of claims 11 wherein the substrate is a monocrystalline silicon wafer or an organic thin film.
19. The method of claim 16 wherein spacing between adjacent nanorods is between 10 and 50 nm.
20. The microbolometer of claim 8 having a size of 3-50 microns square.
21. In a thermal photodetector comprising a mircrobolometer or thermopile, the improvement wherein the mircrobolometer or thermopile is in accordance with claim 11.
22. In a thermal imaging camera or an infra-red camera comprising a thermal photodetector, the improvement wherein the thermal photodetector is in accordance with claim 21.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a semiconductor region comprising an embedded strain-inducing semiconductor alloy formed at least partially in drain and source regions;
a gate electrode structure formed on a portion of said semiconductor region, said gate electrode structure comprising a metal-containing electrode material and a high-k dielectric material; and
contact areas formed above said strain-inducing semiconductor alloy and comprising a metal silicide having a top surface at a height that substantially corresponds to a height of a top surface of said metal-containing electrode material.
2. The semiconductor device of claim 1, further comprising:
a second semiconductor region comprising an embedded second strain-inducing semiconductor alloy formed at least partially in second drain and source regions; and
a second gate electrode structure formed on a portion of said second semiconductor region and comprising a second metal-containing electrode material and a second high-k dielectric material, wherein said embedded second strain-inducing semiconductor alloy differs from said embedded strain-inducing semiconductor alloy.
3. A semiconductor device comprising:
a semiconductor region of a first transistor comprising a strain-inducing semiconductor alloy and a strained semiconductor material laterally enclosed by said strain-inducing semiconductor alloy, said strained semiconductor material and said strain-inducing semiconductor alloy differing in material composition; and
a gate electrode structure formed on a portion of said semiconductor region, said gate electrode structure comprising a metal-containing electrode material, a high-k dielectric material and a spacer structure that is aligned to said strained semiconductor material.
4. The semiconductor device of claim 3, further comprising:
a second semiconductor region of a second transistor comprising a second strain-inducing semiconductor alloy and a second strained semiconductor material laterally enclosed by said second strain-inducing semiconductor alloy, wherein said second semiconductor material and said second strain-inducing semiconductor material differ in material composition; and
a second gate electrode structure formed on a portion of said second semiconductor region, wherein said second gate electrode structure comprises a second metal-containing electrode material, a second high-k dielectric material and a second spacer structure that is aligned to said second strained semiconductor material.
5. The semiconductor device of claim 3, wherein said strain-inducing semiconductor alloy is positioned at least partially in drain and source regions of said first transistor and said strained semiconductor material is positioned at least partially in a channel region of said first transistor.
6. The semiconductor device of claim 3, wherein a bottom of said strained semiconductor material extends to a depth level in said semiconductor region that is below a depth level of a bottom of said strain-inducing semiconductor alloy.
7. The semiconductor device of claim 3, wherein said semiconductor region comprises a semiconductor material layer that is positioned below said strain-inducing semiconductor alloy.
8. The semiconductor device of claim 7, wherein said semiconductor material layer is positioned above a buried insulating material.
9. The semiconductor device of claim 4, wherein said second strain-inducing semiconductor alloy is positioned at least partially in drain and source regions of said second transistor and said second strained semiconductor material is positioned at least partially in a channel region of said second transistor.
10. The semiconductor device of claim 4, wherein a bottom of said second strained semiconductor material extends to a depth level in said second semiconductor region that is below a depth level of a bottom of said second strain-inducing semiconductor alloy.
11. The semiconductor device of claim 4, wherein said strain-inducing semiconductor alloy comprises silicon and carbon and said second strain-inducing semiconductor alloy comprises silicon and germanium.
12. The semiconductor device of claim 4, wherein said first transistor is an N-channel transistor and said second transistor is a P-channel transistor.
13. A semiconductor device comprising:
an isolation structure laterally isolating an active region of said semiconductor device;
a plurality of transistor elements positioned in and above said active region, each of said plurality of transistor elements comprising a gate electrode structure that comprises a high-k gate dielectric material and a metal-containing electrode material; and
a plurality of material regions, each comprising:
a lower strain-inducing portion that is embedded in one of a source region and a drain region of a respective one of said plurality of transistor elements, said lower strain-inducing portion comprising a first semiconductor material; and
an upper contact portion that extends above said active region, said upper contact portion comprising a second semiconductor material and a metal silicide, wherein a height level of a top surface of said upper contact portion substantially corresponds to a height level of a top surface of said metal-containing electrode material.
14. The semiconductor device of claim 13, wherein each of said plurality of transistor elements has a same conductivity type.
15. The semiconductor device of claim 13, wherein a composition of said first semiconductor material is substantially the same as a composition of said second semiconductor material.
16. The semiconductor device of claim 13, wherein said first and semiconductor materials comprise silicon and germanium.
17. The semiconductor device of claim 16, wherein a germanium content of said first semiconductor material is greater than a germanium content of said second semiconductor material in at least part of said upper contact portion.
18. The semiconductor device of claim 13, wherein said metal silicide is positioned at said top surface of said upper contact portion.
19. The semiconductor device of claim 13, wherein said upper contact portion further comprises said high-k dielectric material and said metal containing electrode material.
20. The semiconductor device of claim 19, wherein said metal-containing electrode material of said upper contact portion is positioned at said top surface of said upper contact portion.