Author: claimsbot

1. A device for separating paint overspray from the exhaust air, laden with overspray, of a booth of painting plant, having
a) at least one separating surface along which a booth exhaust air can be guided and which is connected to a first pole of a high-voltage source;
b) an electrode means which is arranged in the booth exhaust air and is associated with the at least one separating surface and is connected to a second pole of the high-voltage source; and,
c) means which can be used to transport paint overspray that is separated off away from the separating surface,
wherein
d) the means for transporting away the paint overspray from the separating surface include a separating liquid which flows downwards over the separating surface; and, wherein
e) a discharge means is provided which has an upwardly open channel out of which separating liquid supplied thereto flows along a longitudinal extent thereof when the level of separating liquid in the channel exceeds an outflow level and reaches the separating surface in such a manner that the separating liquid on the separating surface in flows down as a largely cohesive film.
2. The device of claim 1, wherein the discharge means includes a drainage surface which is associated with the channel and runs parallel thereto and over which the separating liquid flowing out of the channel flows away laterally in the direction of the separating surface.
3. The device of according to claim 2, wherein the drainage surface merges along the channel into the edge thereof.
4. The device of claim 2, wherein the drainage surface has a first section which is inclined outwards and upwards and merges into a second section which runs in a horizontal plane.
5. The device of claim 2, wherein the separating surface carries a brush element.
6. The device of claim 1, wherein substantially vertical walls are arranged above edges of the channel such that a slot running in a longitudinal direction of the is in each case left between them.
7. The device of claim 1, wherein the channel tapers upwards into an outflow slot, with a bottleneck being provided in a path of flow of the separating liquid towards the outflow slot, with the result that the separating liquid is accelerated and undergoes turbulence there.
8. The device of claim 2, wherein the channel andor the associated drainage surface is provided with a groove structure, preferably made of synthetic or rubber material, the grooves whereof extend in a longitudinal direction of the channel.
9. The device of claim 2, wherein the discharge means includes at least one roller projecting into the channel and rotatable about an axis of rotation which runs parallel to a longitudinal direction of the channel, with the result that the separating liquid in the channel is carried upwards by the rotating roller, the drainage surface being the surface of a stripping element, in particular a resilient plate, which bears in a longitudinal direction of the roller against the outer surface thereof such that the separating liquid carried along by the roller is stripped off and flows away, over the surface of the stripping element, in the direction of the separating surface.
10. The device of claim 1, wherein the separating liquid is supplied to the channel at below the outflow level.
11. The device of according to claim 10, wherein there is arranged in the channel, in a longitudinal direction thereof, at least one pipe on which the separating liquid may act and along the longitudinal extent whereof a plurality of outlet openings is provided.
12. The device of claim 1, wherein a horizontal position of the channel in relation to a component carrying it is variable.
13. The device of claim 2, wherein a horizontal position of the drainage surface associated with the channel in relation to a component carrying it is variable.
14. The device of according to claim 12, wherein or 13, the channel andor a component defining the drainage surface isare mounted to be floating as a result of a carrier fluid.
15. The device of claim 2, wherein a compressed air means is provided in the channel and may be used to blow compressed air, below the outflow level, from below onto the separating liquid level, with the result that waves are produced in the separating liquid in a region of the drainage surface.
16. The device of claim 1, wherein a distributing medium, in particular a porous material, through which the separating liquid may flow is arranged in the channel in the longitudinal direction thereof.
17. The device of claim 1, wherein, the channel takes the form of a first pipe having an upwardly pointing overflow slot which runs along a longitudinal extent of the first pipe, with at least one further pipe being arranged below the first pipe such that the separating liquid flowing out of the first pipe passes over the outer surface thereof and reaches the outer surface of the at least one further pipe and from there flows on to the separating surface.
18. The device of according to claim 17, wherein the at least one further pipe is chargeable with the separating liquid and has an outlet slot which runs along a longitudinal extent thereof and by way of which the separating liquid may be discharged in the direction of the separating surface.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A low power, low noise amplifier system comprising:
a first amplifier having first and second differential input terminals, and first and second differential output terminals for providing a differential output of said first amplifier;
first and second input capacitors interconnected with said first and second differential input terminals of said first amplifier;
first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with said differential input and output terminals of said first amplifier;
an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping said low frequency differential input through said first and second input capacitors to the first and second differential input terminals of said first amplifier;
an output chopper switch circuit for receiving and selectively, alternately swapping said differential output of said first amplifier synchronously with said input chopper switch circuit;
a low pass filter responsive to said swapped differential output for providing a low noise, low power amplification of said low frequency differential input;
a second amplifier having third and fourth differential input terminals, and third and fourth differential output terminals for providing a differential output of said second amplifier;
third and fourth input capacitors interconnected with said third and fourth differential input terminals; and
third and fourth feedback circuits containing third and fourth feedback capacitors, respectively, interconnected with said differential input and output terminals of said second amplifier.
2. The amplifier system of claim 1 in which said first and second feedback circuits include a resistor in parallel with each said first and second feedback capacitors.
3. The amplifier system of claim 1 in which said first and second feedback circuits include a pseudo resistance element in parallel with each said first and second feedback capacitors.
4. The amplifier system of claim 1 in which said input and output chopper switch circuits are switched at a frequency that is substantially higher than a highest frequency component of the low frequency differential input.
5. A low power, low noise amplifier system comprising:
at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output;
first and second input capacitors interconnected with said first and second differential amplifier input terminals;
first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with said differential input and output terminals;
an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping said low frequency differential input through said first and second input capacitors to the first and second differential input terminals of said at least one amplifier;
an output chopper switch circuit for receiving and selectively, alternately swapping said differential output synchronously with said input chopper switch circuit;
a low pass filter responsive to said swapped differential outputs for providing a low noise, low power amplification of said low frequency differential inputs; and
an analog to digital converter coupled to said low pass filter output, said analog to digital converter having a sampling bandwidth that is greater than the bandwidth of said low pass filter.
6. A low power, low noise amplifier system comprising:
at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output;
first and second input capacitors interconnected with said first and second differential amplifier input terminals;
first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with said differential input and output terminals;
an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping said low frequency differential input through said first and second input capacitors to the differential input terminals of said at least one amplifier;
an output chopper switch circuit for receiving and selectively, alternately swapping said differential output synchronously with said input chopper switch circuit;
a low pass filter responsive to said swapped differential outputs for providing a low noise, low power amplification of said low frequency differential inputs; and
a common mode feedback and offset cancellation circuit for setting an input common mode level independently of output common mode levels of said at least one amplifier and compensating for amplifier offset of said at least one amplifier.
7. The amplifier system of claim 6 in which said common mode feedback and offset cancellation circuit includes a differential output low pass filter responsive to said amplifier offset, a common mode voltage reference for defining the input common mode level, a summing circuit for combining low pass filter output with the common mode voltage reference, first and second voltage buffers responsive to said summing circuit, and first and second level setting resistors responsive to said first and second buffers, respectively, to apply the combined input common mode level and offset compensation to said first and second differential input terminals.
8. The amplifier system of claim 7 in which said low pass filter includes a pair of capacitors, an input filter chopper circuit for selectively, alternately interconnecting said differential output of said at least one amplifier to said pair of capacitors and an output filter chopper circuit for selectively, alternately interconnecting said pair of capacitors to said summing circuit in synchronism with said input filter chopper circuit and said input and output chopper switch circuits.
9. The amplifier system of claim 6 in which said common mode feedback and offset cancellation circuit includes a common mode voltage reference interconnected with one input terminal of said at least one amplifier to control the input common mode level and an error amplifier responsive to a differential output of said low pass filter interconnected with the other input terminal of said at least one amplifier to compensate for amplifier offset.
10. The amplifier system of claim 5 in which said first and second feedback circuits include a resistor in parallel with each said first and second feedback capacitors.
11. The amplifier system of claim 5 in which said first and second feedback circuits include a pseudo resistance element in parallel with each said first and second feedback capacitors.
12. The amplifier system of claim 5 in which said input and output chopper switch circuits are switched at a frequency that is substantially higher than a highest frequency component of the low frequency differential input.
13. The amplifier system of claim 6 in which said first and second feedback circuits include a resistor in parallel with each said first and second feedback capacitors.
14. The amplifier system of claim 6 in which said first and second feedback circuits include a pseudo resistance element in parallel with each said first and second feedback capacitors.
15. The amplifier system of claim 6 in which said input and output chopper switch circuits are switched at a frequency that is substantially higher than a highest frequency component of the low frequency differential input.

1. A computer-implemented method in a graphical modeling environment, the method comprising:
providing a first control initiator, where the first control initiator is connected to a first subgraph by a first control signal, where:
the control initiator is a block that uses a control signal output to explicitly control execution of one or more subgraphs;

executing the first subgraph in a first thread whose execution is explicitly controlled;
providing a second control initiator, where the second control initiator is connected to a second subgraph by a second control signal;
executing the second subgraph in a second thread whose execution is explicitly controlled; and
interacting with a data synchronization block, where:
the interacting allows a result from the first subgraph to be used by the second subgraph when the second subgraph is executing, and

the data synchronization block waits for the first thread to finish executing before allowing the first result to be used by the second subgraph when the second subgraph is executing.
2. The method of claim 1, where the graphical modeling environment includes a graphical representation that represents the first control initiator and the second control initiator.
3. The method of claim 2, where the graphical representation is a block.
4. The method of claim 1, where graphical modeling environment further includes a splitter block, where the splitter block connects the first control initiator to the first subgraph and the second control initiator to the second subgraph.
5. The method of claim 1, where the synchronization block includes a timeout threshold.
6. The method of claim 5, further comprising:
producing an error when the timeout threshold is exceeded.
7. The method of claim 1, where the control initiator is a state chart.
8. The method of claim 1, where the model is a time-based model, a data flow model, or an event-based model.
9. The method of claim 1, where the control signal is a function-call or an action signal.
10. The method of claim 1, where the model includes one or more data signals.
11. A computer-implemented method in a graphical modeling environment, the method comprising:
providing a spawn control initiator, the spawn control initiator executing on a main thread in the modeling environment where:
the spawn control initiator is a block that uses a control signal output to explicitly control execution of one or more subgraphs;

providing a subgraph in the modeling environment, where:
the subgraph includes one or more blocks, and the subgraph is connected to the spawn control initiator via a control signal;

directly providing inputs to the subgraph; and
executing the subgraph in a separate thread, the separate thread differing from the main thread, the executing producing a result.
12. The method of claim 11, where the modeling environment further includes:
a synchronization block, connected to the output of the subgraph the synchronization block waiting for the separate thread to finish executing before allowing the result to be used by the main thread.
13. The method of claim 11, where the modeling environment produces an error when the result is used in the main thread without first passing through a synchronization block.
14. The method of claim 13, where the synchronization block is the last block executed on the main thread.
15. The method of claim 13, where the synchronization block includes additional inputs, the additional inputs depicting when the result is needed by the main thread.
16. The method of claim 13, where the synchronization block includes a timeout threshold.
17. The method of claim 16, further comprising:
producing an error when the timeout threshold is exceeded.
18. The method of claim 11, where the control initiator is a state chart.
19. The method of claim 11, where the model is a time-based model, a data flow model, or an event-based model.
20. The method of claim 11, where the control signal is a function-call or an action signal.
21. The method of claim 11, where the model includes one or more data signals.
22. A non-transitory computer-readable medium holding executable instructions that when executed on a processor control subgraph execution in a model, the medium holding one or more instructions for:
providing a first control initiator, where the first control initiator is connected to a first subgraph by a first control signal where:
the control initiator is a block that uses a control signal output to explicitly control execution of one or more subgraphs;

executing the first subgraph in a first thread whose execution is explicitly controlled;
providing a second control initiator, where the second control initiator is connected to a second subgraph by a second control signal where:
the control initiator is a block that uses a control signal output to explicitly control execution of one or more subgraphs;

executing the second subgraph in a second thread whose execution is explicitly controlled; and
interacting with a data synchronization block, where: the interacting allows a result from the first subgraph to be used by the second subgraph when the second subgraph is executing, and

the data synchronization block waits for the first thread to finish executing before allowing the first result to be used by the second subgraph when the second subgraph is executing.
23. A non-transitory computer-readable medium holding executable instructions that when executed on a processor control execution of a subgraph in a model, the medium holding one or more instructions for:
providing a spawn control initiator, the spawn control initiator executing on a main thread in the modeling environment where:
the spawn control initiator is a block that uses a control signal output to explicitly control execution of one or more subgraphs;
providing a subgraph in the modeling environment, where:
the subgraph includes one or more blocks, and
the subgraph is connected to the spawn control initiator via a control signal;
directly providing inputs to the subgraph; and
executing the subgraph in a separate thread, the separate thread differing from the main thread, the executing producing a result.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for processing data, the method comprising:
coding a data item to obtain a coded data item that includes a predefinable number of bits;
influencing bits of the coded data item to obtain a changed data item;
decoding the changed data item by using a fault-correcting code to obtain a decoded data item; and
processing the decoded data item.
2. The method of claim 1, wherein for the step of coding, a fault-correcting code is used, in particular a Hamming code.
3. The method of claim 1, wherein the step of influencing includes at least one of inverting and deleting bits of the coded data item.
4. The method of claim 1, wherein the step of processing includes carrying out at least a part of a cryptographic method or comparing data with predefinable reference data.
5. The method of claim 1, wherein at least one of the coded data item, the changed data item, and the decoded data item is stored at least temporarily.
6. The method of claim 1, wherein the influencing is carried out as a function of at least one of a deterministic process and a stochastic process.
7. The method of claim 1, wherein the decoding is carried out in such a way that a time for the decoding of the changed data item is not constant between different performances of the decoding.
8. A device for processing data, the device comprising:
processing circuitry, wherein the processing circuitry is configured to:
code a data item to obtain a coded data item that includes a predefinable number of bits;
influence bits of the coded data item to obtain a changed data item;
decode the changed data item by using a fault-correcting code to obtain a decoded data item; and
process the decoded data item.
9. The device of claim 8, wherein the coding includes use of a fault-correcting code.
10. The device of claim 9, wherein the fault-correcting code is a Hamming code.
11. The device of claim 8, wherein the influencing includes at least one of inverting and deleting bits of the coded data item.
12. The device of claim 8, further comprising a memory, wherein the processing circuitry is configured to store at least one of the coded data item, the changed data item, and the decoded data item at least temporarily in the memory.