Author: claimsbot

1. A sauna comprising:
an enclosure assembly for accommodating a user;
at least one heat source disposed within the enclosure;
at least one monitoring device that collects biological data associated with a user, while the user is within the enclosure assembly;
a first computing device coupled to the at least one monitoring device, wherein the first computing device comprises an analysis module for analyzing collected biological data associated with a user; and
a display device attached to the enclosure assembly, wherein the display device is coupled to the first computing device.
2. The sauna of claim 1, wherein the at least one monitoring device comprises a sensor that can be worn by a user.
3. The sauna of claim 1, wherein biological data associated with a user comprises one or more of a blood pressure, a heart rate, a core body temperature, a body weight and a measure of perspiration.
4. The sauna of claim 1, wherein analyzing collected biological data associated with a user comprises computing a caloric measurement.
5. The sauna of claim 1, further comprising a remote control module for adjusting sauna features from a location remote from the sauna.
6. The sauna of claim 1, wherein the display device comprises a touch-screen inputoutput device.
7. The sauna of claim 1, further comprising an adjustable lighting system.
8. The sauna of claim 1, further comprising a multimedia entertainment system, the multimedia entertainment system comprising at least one audio media device.
9. The sauna of claim 8, wherein the multimedia entertainment system comprises at least one interface for receiving multimedia content from a storage device.
10. The sauna of claim 1, wherein the at least one heat source comprises an infrared heat source.
11. The sauna of claim 1, further comprising a heat control module for controlling the at least one heat source.
12. The sauna of claim 10, wherein the heat control module is further operable to cause the sauna to rapidly achieve a desired temperature before a user enters the sauna.
13. The sauna of claim 10, wherein the heat control module is operable to allow the user to select a desired wavelength output associated with the at least one heat source, the wavelength output comprising a wavelength corresponding to infrared radiation.
14. The sauna of claim 12, wherein the infrared radiation comprises one or more of near infrared radiation, mid infrared radiation, and far infrared radiation.
15. The sauna of claim 1, wherein the at least one heat source is adapted for providing adjustable infrared radiation within a zone corresponding to a region of a user’s body.
16. The sauna of claim 1, further comprising a timing device coupled to the at least one heat source, wherein said timing device is adapted to allow operation of the at least one heat source for a selected time period.
17. The sauna of claim 1, wherein the computing device is configured for storing at least one profile, the at least one profile comprising at least one sauna feature setting.
18. The sauna of claim 17, wherein the at least one profile is associated with at least one treatment type.
19. The sauna of claim 18, wherein the at least one treatment type comprises at least one of detoxification, weight loss, and pain management.
20. The sauna of claim 17, wherein the at least one profile is associated with at least one user of the sauna.
21. The sauna of claim 1, wherein the computing device comprises a connection port for interfacing with peripheral devices.
22. The sauna of claim 1, wherein the computing device comprises a client, the client comprising:
an inputoutput component for communicating with a server, wherein communications from the server comprise at least one sauna feature setting;
a storage component for storing data; and
a settings component for implementing the at least one sauna feature setting.
23. The sauna of claim 22, wherein the server comprises a dynamic experience updating module for generating sauna feature settings to be communicated to the client.
24. The sauna of claim 22, wherein the server is adapted to maintain a website.
25. The sauna of claim 22, wherein the sauna feature settings comprise at least one computer-readable instruction embodied on a computer readable medium, wherein the at least one instruction corresponds to an output associated with at least one heat source.
26. The sauna of claim 1 further comprising an electrical system that facilitates the operation of the sauna, wherein the electrical system comprises a plurality of diagnostic devices for detecting electrical failure.
27. The sauna of claim 26, wherein the computing device further comprises a diagnostic module for analyzing data received from at least one of the plurality of diagnostic devices.
28. A method for using a sauna, the method comprising:
identifying a plurality of progress levels associated with a training program, wherein each of the plurality of progress levels corresponds to at least one sauna feature setting;
receiving notification that a user has initiated a training session associated with a first one of the plurality of progress levels;
receiving biological data corresponding to the user, wherein the biological data is communicated to a server from a client associated with the sauna;
storing the biological data, wherein the biological data is stored as part of a session entry in a training log associated with the user;
determining whether the user has successfully completed the first one of the plurality of progress levels, wherein said determination is based on an analysis of the biological data;
if the user has successfully completed the first one of the plurality of progress levels, generating at least one updated sauna feature setting that corresponds to a second one of the plurality of progress levels; and
communicating the at least one updated sauna feature setting to the client.
29. A method for using a sauna, the method comprising:
providing at least one diagnostic device for detecting electrical failure within an electrical system, wherein the electrical system comprises a plurality of electrical connections that facilitate control of the sauna;
receiving diagnostic data communicated from the at least one diagnostic device, wherein diagnostic data comprises data associated with an electrical failure;
analyzing the diagnostic data, wherein analyzing the diagnostic data comprises determining at least one characteristic of the electrical failure; and
generating a repair plan based on the at least one characteristic, wherein the repair plan comprises a set of instructions for repairing the electrical failure.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An interactive head-mounted device, comprising:
an optical assembly through which a surrounding environment is viewable;
an integrated processor for handling virtual content for display;
an integrated image source for introducing the virtual content to the optical assembly; and
an environmental sensor;
wherein the integrated processor is adapted to initially display, via the integrated image source and the optical assembly, the virtual content with a display parameter having a first setting, and
wherein the integrated processor is adapted to display, via the integrated image source and the optical assembly, the virtual content with the display parameter having a second setting, different from the first setting, responsive to a change in the surrounding environment as recognized by the environmental sensor.
2. The device of claim 1, wherein the virtual content is a video image.
3. The device of claim 2, wherein the display parameter is at least one of brightness, color saturation, color balance, color hue, video resolution, transparency, compression rate, frames per second rate, and playback speed.
4. The device of claim 1, wherein the environmental sensor includes at least one of a charge-coupled device, a black silicon sensor, an IR sensor, an acoustic sensor, an induction sensor, a motion sensor, an optical sensor, an opacity sensor, a proximity sensor, an inductive sensor, an Eddy-current sensor, a passive infrared proximity sensor, a radar, a capacitive displacement sensor, a hall-effect sensor, a magnetic sensor, a GPS sensor, a thermal imaging sensor, a thermocouple, a thermistor, a photoelectric sensor, an ultrasonic sensor, an infrared laser sensor, an inertial motion sensor, a MEMS internal motion sensor, an ultrasonic 3D motion sensor, an accelerometer, an inclinometer, a force sensor, a piezoelectric sensor, a rotary encoder, a linear encoder, a chemical sensor, an ozone sensor, a smoke sensor, a heat sensor, a magnetometer, a carbon dioxide detector, a carbon monoxide detector, an oxygen sensor, a glucose sensor, a smoke detector, a metal detector, a rain sensor, an altimeter, an activity sensor, an object detector, a marker detector, a laser rangefinder, a sonar, a capacitive sensor, a heart rate sensor, and an RFmicropower impulse radio (MIR) sensor.
5. The device of claim 2, wherein the video image is stopped from playing in response to an indication from an accelerometer input of the environmental sensor that a user’s head is moving.
6. The device of claim 4, wherein an audio sensor input of the environmental sensor is generated by the speaking of at least one participant of a video conference.
7. The device of claim 2, wherein the video image is made more or less transparent in response to an indication from the environmental sensor that a user is moving.
8. An interactive head-mounted device, comprising:
an optical assembly through which a surrounding environment is viewable;
an integrated processor for handling virtual content for display;
an integrated image source for introducing the virtual content to the optical assembly; and
an integrated virtual image capture facility that images an aspect of the surrounding environment and provides the virtual content for display;
wherein the integrated processor is adapted to initially display, via the integrated image source and the optical assembly, the virtual content with a display parameter having a first setting, and
wherein the integrated processor is adapted to display, via the integrated image source and the optical assembly, the virtual content with the display parameter having a second setting, different from the first setting, responsive to a change in the surrounding environment as recognized by the integrated virtual image capture facility.

1.-38. (canceled)
39. A single-step, single-vial method for preparing micron-sized or submicron-sized particles comprising:
reducing the temperature of a vial wherein the vial has a temperature differential of at least 30\xb0 C. between the solvent and the vial; and
spraying or dripping solvent droplets of a water soluble effective ingredient dissolved in one or more solvents directly into the vial such that the effective ingredient is exposed to a vapor-liquid interface of less than 500 cm\u22121 areavolume, wherein the surface freezes the droplet into a thin film with a thickness of less than 500 micrometers and a surface area to volume between 25 to 500 cm\u22121.
40. The method of claim 39, wherein the droplets freeze upon contact with the surface in about 50, 75, 100, 125, 150, 175, 200, 250, 500, 1,000 and 2,000 milliseconds.
41. The method of claim 39, wherein the droplets freeze upon contact with the surface in about 50 to 500 milliseconds.
42. The method of claim 39, wherein the droplets freeze upon contact with the surface in about 50 to 150 milliseconds.
43. The method of claim 39, wherein the droplet has a diameter between 0.1 and 5 mm at room temperature.
44. The method of claim 39, wherein the droplet has a diameter between 2 and 4 mm at room temperature.
45. The method of claim 39, wherein the droplet forms a thin film on the surface of between 50 and 500 micrometers in thickness.
46. The method of claim 39, wherein the droplets have a cooling rate of between 50-250 Ks.
47. The method of claim 39, wherein the vial is cooled by a cryogenic solid, a cryogenic gas, a cryogenic liquid, a freezing fluid, a freezing gas, a freezing solid, a heat exchanger, or a heat transfer fluid capable of reaching cryogenic temperatures or temperatures below the freezing point of the solvent.
48. The method of claim 39, wherein the vial, the water soluble effective ingredient and the one or more solvents are pre-sterilized prior to spraying or dripping.
49. The method of claim 39, wherein the step of spraying or dripping is repeated to overlay one or more thin films on top of each other to fill the vial to any desired level up to totally full.
50. The method of claim 39, further comprising the step of resuspending the composition in a solvent in an individually dosed vial to create a suspension or solution for delivery of the effective ingredient.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An improved security processing circuit for performing 3DES IPsec security processing services for a host system using a DES engine, the security processing circuit comprising:
the DES engine having a message input, a cipher key input, and a pre-data output, the engine adapted to receive and selectively process a block of data from the message input of the security processing circuit during a first DES processing operation, and subsequently to process data from an intermediate result during second and third DES processing operations and store an intermediate result of the third DES processing operation to the pre-data output;
a security keys circuit having a set of cipher keys input and a key output, the security keys circuit operable to select and transfer a different cipher key to the key output coupled to the cipher key input of the DES engine selected from the set of cipher keys associated with each DES processing operation during the first, second and third DES processing operations; and
a data output circuit having a pre-data input and a data output, the pre-data input of the data output circuit coupled to the pre-data output of the DES engine, and the data output selectively coupleable to the host system, the data output circuit operable to further security process data from the pre-data input and to selectively exclusive OR an initialization vector with the processed data and latch a final third DES result to the data output of the security processing circuit for use by the host system,
wherein the DES engine comprises:
a permutation block having the message input and a permutation output, the permutation block operable to receive a block of data at the message input and to perform an initial permutation of the message input data and provide a permutation result at the permutation output;
a data input multiplexer having a first and second input and a data selection output, the data input multiplexer operable to select and couple one of the first and second inputs to the data selection output;
an intermediate result register having a data input coupled to the data selection output, a clock input, and a latched data output, the register operable to store right and left half results of the initial permutation or of an eight round cipher process based on data present at the data input upon receipt of a clock signal at the clock input;
eight cipher blocks having a data input, a key input, and a cipher output, operable to receive data at the data input and a key at the key input, to perform the cipher process comprising right and left halves of a sequential eight step cipher process on the data at the data input employing the key, and to provide a first and second cipher result during a first and second eight step cycle of each of the three DES processing operations;
a pre-data output multiplexer having a first and second input and a data selection output, the pre-data output multiplexer operable to select and couple one of the first and second inputs to the data selection output; and
a pre-data output register having a data input, a clock input, and a latched data output,
wherein the permutation output of the permutation block is coupled to the first input of the data input multiplexer, the data selection output of the data input multiplexer coupled to the data input of the intermediate result register, the latched data output of the intermediate result register coupled to the data input of the eight cipher blocks having the cipher output of the eight cipher blocks feedback coupled to the second input of the data input multiplexer and to the first input of the pre-data output multiplexer, the data selection output of the pre-data output multiplexer coupled to the pre-data output register, the latched data output of the pre-data output register feedback coupled to the second input of the pre-data output multiplexer and the pre-data output.
2. The security processing circuit of claim 1,
wherein the DES engine is further operable to perform the initial permutation of the message input data using the permutation block, initially select the permutation result with the data input multiplexer and couple and store the result to the intermediate result register during a data input latch cycle, to transfer the initial result and the cipher key from the security keys circuit to the eight cipher blocks for cipher processing and intermediate storage of the right and left halves of the first eight step cipher results subsequent to selection of the second input of the data input multiplexer into the intermediate result register during the first cipher process cycle, to transfer the stored intermediate result and the cipher key from the security keys circuit to the eight cipher blocks for cipher processing and intermediate storage of the right and left halves of the second eight step cipher results subsequent to selection of the second input of the data input multiplexer into the intermediate result register and the pre-data output register subsequent to selection of the first input of the pre-data output multiplexer during the second cipher process cycle of the first DES processing operation, and
wherein the DES engine is operable to repeat the first and second cipher process cycles for the subsequent second and third DES security processing operations of the security processing circuit, and latch the intermediate result of the third DES operation to the pre-data output of the pre-data output register of the DES engine, using the selection of the second input of the pre-data output multiplexer during the third DES processing operation of the 3DES security processing.
3. The security processing circuit of claim 2, wherein the 3DES processing is completed in three single DES processing operations.
4. The security processing circuit of claim 2, wherein the 3DES processing is completed in eight clock cycles.
5. The security processing circuit of claim 2, wherein the first, second and third DES processing operations each have a duration of two clock cycles.
6. The security processing circuit of claim 4, wherein the clock cycle has a period of about 8 ns.
7. The security processing circuit of claim 4, wherein the eight clock cycles of the 3DES security processing comprise:
a data input latch cycle;
a first DES processing operation comprising two cycles;
a second DES processing operation comprising two cycles;
a third DES processing operation comprising two cycles; and
a data output latch cycle.
8. The security processing circuit of claim 1, further comprising a clock input coupled to one or more of the DES engine, the security keys circuit, and the data output circuit for timing clock cycles of the first, second and third DES processing operations of the 3DES processing for the security processing circuit.
9. The security processing circuit of claim 1, wherein the security keys circuit comprises:
a set of cipher keys input, wherein the set of cipher keys comprise three different cipher keys, each cipher key associated with one of the three DES processing operations of the 3DES security processing;
a keys input multiplexer having a set of cipher keys input, and a cipher key selection output, the keys input multiplexer operable to select and couple a cipher key to the cipher key selection output; and
a security keys register having a data input, a clock input, and a latched data output, the register operable to store the cipher key selection associated with one of the three DES processing operation of the 3DES security processing based on cipher key data at the data input upon receipt of a clock signal at the clock input, the latched data output of the security keys register coupled to the key input of the eight cipher blocks.
10. The security processing circuit of claim 9, wherein the keys input multiplexer is operable to receive the three cipher keys and to selectively couple one of the three cipher keys associated with a DES processing operation to the Des engine during the three DES processing operations of the 3DES security process.
11. The security processing circuit of claim 1, wherein the data output circuit comprises:
an inverse permutation block having a pre-data input and an inverse permutation output, the inverse permutation block operable to receive and further security process the pre-data output from the DES engine, performing an inverse permutation of the pre-data and transfer the processed data to the inverse permutation output;
an XOR gate having a processed data input, an initialization vector input, and an XOR gate output, the XOR gate operable to selectively exclusive OR the initialization vector at the initialization vector input together with the processed data from the inverse permutation output of the inverse permutation block coupled to the processed data input, and transfer the XOR data to the XOR gate output;
a data output multiplexer having a first and second input, a selection control signal, and a data selection output, the data output multiplexer operable to select and couple one of the first and second inputs to the data selection output, based on the state of the selection control signal, the first input coupled to the XOR gate output, and the second input coupled to a data output register; and
the data output register having a data input, a clock input, and a latched data output, the register operable to store the output data results of the third DES process based on data present at the data input upon receipt of a clock signal at the clock input, the latched data output of the data output register feedback coupled to the second input of the data output multiplexer to insure latching of the data at the output,
wherein the data output circuit is operable to further security process data from the pre-data input and to selectively exclusive OR an initialization vector with the processed data and latch a final third DES result to the data output of the security processing circuit for use by the host system.
12. The security processing circuit of claim 11, wherein the data output circuit is operable to further security process data from the pre-data input and to selectively exclusive OR an initialization vector with the processed data and latch a final third DES result to the data output of the security processing circuit for use by the host system.
13. The security processing circuit of claim 1, wherein the security processing circuit resides within a network interface device of a host system for performing 3DES encryption and decryption services for the host system using a Des engine.
14. The security processing circuit of claim 1, further comprising a network interface device coupled with the security processing circuit, the network interface device being adapted to selectively encrypt outgoing data from the host system to cryptographically process data for transmission to the network.
15. The security processing circuit of claim 14, wherein the network interface device comprises a bus interface, a media access control system, and the security processing circuit.
16. The security processing circuit of claim 15, wherein the network interface device is a single integrated circuit.
17. The security processing circuit of claim 1, wherein the circuit comprises an IPsec circuit adapted to selectively provide authentication, encryption, and decryption functions for incoming and outgoing data.
18. An improved DES engine used in a security processing circuit for performing 3DES IPsec security processing, the DES engine comprising:
a permutation block having the message input and a permutation output, the permutation block operable to receive a block of data at the message input and to perform an initial permutation of the message input data and provide a permutation result at the permutation output;
a data input multiplexer having a first and second input and a data selection output, the data input multiplexer operable to select and couple one of the first and second inputs to the data selection output;
an intermediate result register having a data input coupled to the data selection output, a clock input, and a latched data output, the register operable to store right and left half results of the initial permutation or of an eight round cipher process based on data present at the data input upon receipt of a clock signal at the clock input;
eight cipher blocks having a data input, a key input, and a cipher output, operable to receive data at the data input and a key at the key input, to perform the cipher process comprising right and left halves of a sequential eight step cipher process on the data at the data input employing the key, and to provide a first and second cipher result during a first and second eight step cycle of each of the three DES processing operations;
a pre-data output multiplexer having a first and second input and a data selection output, the pre-data multiplexer operable to select and couple one of the first and second inputs to the data selection output; and
a pre-data output register having a data input, a clock input, and a latched data output,
wherein the engine is adapted to receive and selectively process a block of data from the message input of the security processing circuit during a first DES processing operation, and subsequently to process data from an intermediate result during second and third DES processing operations of a 3DES security processing and store an intermediate result of the third DES processing operation to a pre-data output of the pre-data output register, and
wherein the permutation output of the permutation block is coupled to the first input of the data input multiplexer, the data selection output of the data input multiplexer coupled to the data input of the intermediate result register, the latched data output of the intermediate result register coupled to the data input of the eight cipher blocks having the cipher output of the eight cipher blocks feedback coupled to the second input of the data input multiplexer and to the first input of the pre-data output multiplexer, the data selection output of the pre-data output multiplexer coupled to the pre-data output register, the latched data output of the pre-data output register feedback coupled to the second input of the pre-data output multiplexer and the pre-data output.
19. The DES engine of claim 18,
wherein the engine is further operable to perform the initial permutation of the message input data using the permutation block, initially select the permutation result with the data input multiplexer and coupled and store the result to the intermediate result register during a data input latch cycle, to transfer the initial result and the cipher key from the security keys circuit to the eight cipher blocks for cipher processing and intermediate storage of the right and left halves of the first eight step cipher results subsequent to selection of the second input of the data input multiplexer into the intermediate result register during the first cipher process cycle, to transfer the stored intermediate result and the cipher key from the security keys circuit to the eight cipher blocks for cipher processing and intermediate result register and the pre-data output register subsequent to selection of the first input of the pre-data output multiplexer during the second cipher process cycle of the first DES processing operation, and
wherein the DES engine is operable to repeat the first and second cipher process cycles for the subsequent second and third DES security processing operations of the security processing circuit, and latch the intermediate result of the third DES operation to the pre-data output of the pre-data output register of the DES engine, using the selection of the second input of the pre-data output multiplexer during the third DES processing operation of the 3DES security processing.
20. The DES engine of claim 18, wherein the timing of the 3DES processing is completed in three single DES processing operations.
21. The DES engine of claim 18, wherein the timing of the 3DES processing is completed in eight clock cycles.
22. The DES engine of claim 18, wherein the first, second and third DES processing operations each have a duration of two clock cycles.
23. The DES engine of claim 21, wherein the clock cycle has a period of about 8 ns.
24. The DES engine of claim 21, wherein the eight clock cycles of the 3DES security processing comprise:
a data input latch cycle;
a first DES processing operation comprising two cycles;
a second DES processing operation comprising two cycles;
a third DES processing operation comprising two cycles; and
a data output latch cycle.
25. The DES engine of claim 18, further comprising a clock input coupled to one or more of the DES engine, the security keys circuit, and the data output circuit for timing clock cycles of the first, second and third DES processing operations of the 3DES processing for the security processing circuit.