Author: claimsbot

1. An apparatus for controlling NAND flash memory, the apparatus comprising:
a register unit storing a start address of a macro-command to be executed, wherein macro-commands are described in a command script, and wherein each macro-command comprises a plurality of micro-commands in an array for controlling a unit operation of NAND flash memory;
a command fetch unit, if a start address of the macro-command to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command to be executed and sequentially reading the plurality of micro-commands from the start address of the macro-command to be executed;
a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and
a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation.
2. The apparatus of claim 1, wherein the register unit comprises:
a first register storing a start address of a macro-command to be executed, wherein macro-commands are described in a command script; and
a second register storing a start address of a macro-command array to be executed,
wherein macro-command arrays are described in a command script comprising at least one macro-command array, and
wherein each macro-command array comprises a plurality of micro-command arrays for controlling a unit operation of NAND flash memory and if the start address of the macro-command array to be executed is recorded in the second register, the command fetch unit accesses first memory connected based on the start address of the macro-command array to be executed, sequentially reads start addresses of the macro-command from the start address of the macro-command array to be executed, and sequentially reads the plurality of micro-commands that constitute each macro-command from the first memory based on the start address of each macro-command.
3. The apparatus of claim 2, wherein final data of the macro-command array is a macro-command array end command that indicates an end of the macro-command array, and if the macro-command array end command is read, the command fetch unit stops an additional operation of reading the start address of each macro-command.
4. The apparatus of one of claims 1 to 3, wherein final data of the macro-command array is a macro-command end command that indicates an end of the macro-command, and if the macro-command end command is read, the command fetch unit stops an additional operation of reading the micro-commands.
5. The apparatus of one of claims 1 to 3, wherein each of the interface signals is a NAND flash memory control signal selected from the group consisting of a single read signal RDS for reading data once from NAND flash memory, a single write signal WRS for writing data once in NAND flash memory, a multiple read signal RDM for reading data a plurality of times from NAND flash memory, a multiple write signal WRM for writing data a plurality of times in NAND flash memory, a chip enable (CE) signal for selecting a NAND flash memory chip for operation control from a plurality of NAND flash memory chips, a state check signal RB for checking a state of a NAND flash memory chip selected from the plurality of NAND flash memory chips, a wait signal WAIT for delaying for a predetermined number of times of an internal clock period, and an end signal END for ending an operation of controlling NAND flash memory.
6. The apparatus of one of claims 1 to 3, further comprising a register bank unit in which a plurality of registers in which a value of a command parameter that constitutes the micro-commands is recorded, are arranged in an array shape, wherein the command interpretation unit reads the value recorded in a register corresponding to a number of a register defined due to the command parameter of the micro-commands and provides the read value to the command execution unit.
7. The apparatus of one of claims 1 to 3, further comprising a data management unit which reads data stored in the connected second memory and provides the read data to the command execution unit or which receives the data read from NAND flash memory through an inputoutput (IO) bus from the command execution unit and stores the data in the second memory, wherein the register unit comprises a third register in which a data start address that indicates a start point of data write in the second memory and a start point of data write from the second memory by using the data management unit, is recorded.
8. An apparatus for controlling NAND flash memory, the apparatus comprising:
a register unit storing a start address of a macro-command array to be executed, wherein selected from macro-command arrays are described in a command script, and wherein each macro-command array comprises a plurality of micro-command arrays for controlling a unit operation of NAND flash memory;
a command fetch unit, if the start address of the macro-command array to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command array to be executed, sequentially reading start addresses of the macro-command from the start address of the macro-command array to be executed, and sequentially reading the plurality of micro-commands that constitute each macro-command from the first memory based on the start address of each macro-command;
a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and
a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation.
9. The apparatus of claim 8, wherein final data of the macro-command array is a macro-command array end command that indicates an end of the macro-command array, and if the macro-command array end command is read, the command fetch unit stops an additional operation of reading the start address of each macro-command.
10. The apparatus of claim 8 or 9, wherein final data of the macro-command array is a macro-command end command that indicates an end of the macro-command, and if the macro-command end command is read, the command fetch unit stops an additional operation of reading the micro-commands.
11. The apparatus of one of claims 8 to 9, wherein each of the interface signals is a NAND flash memory control signal selected from the group consisting of a single read signal RDS for reading data once from NAND flash memory, a single write signal WRS for writing data once in NAND flash memory, a multiple read signal RDM for reading data a plurality of times from NAND flash memory, a multiple write signal WRM for writing data a plurality of times in NAND flash memory, a chip enable (CE) signal for selecting a NAND flash memory chip for operation control from a plurality of NAND flash memory chips, a state check signal RB for checking a state of a NAND flash memory chip selected from the plurality of NAND flash memory chips, a wait signal WAIT for is delaying for a predetermined number of times of an internal clock period, and an end signal END for ending an operation of controlling NAND flash memory.
12. The apparatus of one of claims 8 to 9, further comprising a register bank unit in which a plurality of registers in which a value of a command parameter that constitutes the micro-commands is recorded, are arranged in an array shape, wherein the command interpretation unit reads the value recorded in a register corresponding to a number of a register defined due to the command parameter of the micro-commands and provides the read value to the command execution unit.
13. The apparatus of one of claims 8 to 9, further comprising a data management unit which reads data stored in the connected second memory and provides the read data to the command execution unit or which receives the data read from NAND flash memory through an inputoutput (IO) bus from the command execution unit and stores the data in the second memory, wherein the register unit comprises a third register in which a data start address that indicates a start point of data write in the second memory and a start point of data write from the second memory by using the data management unit, is recorded.
14. The apparatus of claim 10, wherein each of the interface signals is a NAND flash memory control signal selected from the group consisting of a single read signal RDS for reading data once from NAND flash memory, a single write signal WRS for writing data once in NAND flash memory, a multiple read signal RDM for reading data a plurality of times from NAND flash memory, a multiple write signal WRM for writing data a plurality of times in NAND flash memory, a chip enable (CE) signal for selecting a NAND flash memory chip for operation control from a plurality of NAND flash memory chips, a state check signal RB for checking a state of a NAND flash memory chip selected from the plurality of NAND flash memory chips, a wait signal WAIT for is delaying for a predetermined number of times of an internal clock period, and an end signal END for ending an operation of controlling NAND flash memory.
15. The apparatus of claim 10, further comprising a register bank unit in which a plurality of registers in which a value of a command parameter that constitutes the micro-commands is recorded, are arranged in an array shape, wherein the command interpretation unit reads the value recorded in a register corresponding to a number of a register defined due to the command parameter of the micro-commands and provides the read value to the command execution unit.
16. The apparatus of claim 10, further comprising a data management unit which reads data stored in the connected second memory and provides the read data to the command execution unit or which receives the data read from NAND flash memory through an inputoutput (IO) bus from the command execution unit and stores the data in the second memory, wherein the register unit comprises a third register in which a data start address that indicates a start point of data write in the second memory and a start point of data write from the second memory by using the data management unit, is recorded.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device (1) for automatically cleaning a surface submerged in a liquid, designed to be connected to a pump, comprising:
a hollow head (2) having a seat (11); and
first (5a) and second (5b) suction hoses opening onto said hollow head (2),
wherein the seat (11) delimits a space in which a flap valve (4, 41, 42) is housed, said flap valve (4, 41, 42) being adapted to cooperate with said seat (11) so as to adopt first and second closing positions in which it respectively closes the first (5a) and second (5b) suction hoses when said device (1) is operating,
wherein a sieve (9) is arranged inside the hollow head (2) so as to avoid the flap valve (4, 41, 42) from being stuck by any debris in said space,
wherein said flap valve (41, 42) is at least partially hollow,
wherein the flap valve (41, 42) comprises a spacer (50) arranged between the first (41a, 42a) and second (42a, 42b) faces thereof, and
wherein a length of said spacer (50) is adjustable.
2. The device according to claim 1, wherein a ratio between a width of the flap valve (4, 41, 42) and a width of said space at a section (S) of said space is greater than 70%.
3. The device according to claim 1, wherein said seat (11) has first (11a) and second (11b) faces, and said flap valve (4, 41, 42) has first (4a, 41a, 42a) and second (4b, 41b, 42b) faces, and said first faces or said second faces cooperating together for alternately sealing the first and second hoses pipes.
4. The device according to claim 3, wherein an angle between the first (41a, 42a) and second (42a, 42b) faces of the flap valve (41, 42) is adjustable.
5. The device according to claim 2, wherein the section (S) is perpendicular to a bisector (B) of the first (11a) and second (11b) faces of the seat (11).
6. The device according to claim 1, wherein the hollow head (2) has a flat surface opposite the submerged surface, and the first (5a) and second (5b) suction hoses have a slope between 20\xb0 and 30\xb0 with respect to a plane of the surface submerged in the liquid.
7. The device according to claim 6, wherein the slope is 25\xb0.
8. The device according to claim 1, wherein the surface submerged in the liquid is at least one of a bottom, walls, submerged area, and water line of a swimming pool.

1. A unified memory system comprising:
a memory accessed from a plurality of masters;
a speculative access control section for issuing, in response to a first access request to the memory from a CPU as one of the plurality of masters, a speculative second access request to the memory; and
a memory controller for receiving the first and second access requests and an access request to the memory from any of the plurality of masters other than the CPU and executing access to the memory,
wherein the speculative access control section issues the second access request according to speculative access information as information related to access to the memory.
2. The system of claim 1, wherein the CPU controls the speculative access control section using the speculative access information.
3. The system of claim 2, wherein the CPU uses memory access priorities of the plurality of masters as the speculative access information, and
the speculative access control section issues the second access request if the memory access priority of the CPU is higher than the memory access priority of any of the plurality of masters other than the CPU.
4. The system of claim 2, wherein the CPU determines a hit rate indicating the proportion in which data transfers already executed in response to speculative access requests were useful, as the speculative access information, and
the speculative access control section issues the second access request if the hit rate is higher than a predetermined value.
5. The system of claim 1, wherein the memory controller produces the speculative access information.
6. The system of claim 5, wherein the memory controller outputs the number of access requests from the plurality of masters as the speculative access information, and
the speculative access control section issues the second access request if the number of access requests is smaller than a predetermined value.
7. The system of claim 5, wherein the memory controller outputs the number of cycles required for completion of access to the memory as the speculative access information, and
the speculative access control section issues the second access request if no unexecuted normal access to the memory exists and the number of cycles is smaller than a predetermined value.
8. The system of claim 5, wherein the memory controller outputs requesting master information indicating a master that is under issuance of an access request to the memory, among the plurality of masters, as the speculative access information, and
the speculative access control section issues the second access request if the requesting master information does not indicate a predetermined master.
9. The system of claim 1, wherein the speculative access control section issues the second access request according to a parameter selected from a plurality of parameters as the speculative access information.
10. The system of claim 9, wherein the speculative access control section issues the second access request according to the result of weighted calculation of determination results on issuance of a second access request obtained based on a plurality of parameters selected.
11. The system of claim 1, further comprising a size determination section for setting the size of data to be transferred in response to the second access request at a value corresponding to the speculative access information.
12. The system of claim 1, wherein the speculative access control section issues a speculative third access request for accessing the memory after completion of access to the memory according to the second access request if the priority of access to the memory from the CPU is high.
13. The system of claim 12, further comprising a size determination section for setting the size of data to be transferred in response to the third access request at a value corresponding to the speculative access information.
14. The system of claim 12, wherein the speculative access control section determines a hit rate indicating the proportion in which data transfers already executed in response to speculative access requests were useful, and issues the third access request if the hit rate is higher than a predetermined value.
15. The system of claim 14, further comprising a size determination section for setting the size of data to be transferred in response to the third access request at a value corresponding to the hit rate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of detecting an unauthorized exchange of components comprising the steps of:
a control unit sending a message to a first component, said message including at least one randomly generated or not easily reproducible value used for checking said first component and a selection data field;
said first component accessing an assignment field and assigning an identification to each of said at least one randomly generated or not easily reproducible value when a defined value is transmitted in the selection data field;
said first component generating the identification on the basis of an algorithm when other values are transmitted in the selection data field;
said first component transmitting said identification back to said control unit; and
said control unit deciding, on the basis of the identification, whether the first component is a component which is authorized for use.
2. The method according to claim 1, wherein
the assignment field is a matrix from which said identification is generated on the basis of two randomly generated or not easily reproducible values.
3. The method according to claim 1, wherein:
the algorithm is filed in both the component and the control unit; and
said control unit uses said algorithm to determine whether the component is authorized.
4. The method according to claim 1, wherein the first component sends back a message to the control unit, in which the selection data field and then the determined identification are transmitted.
5. The method according to claim 1, wherein, on the basis of a function value or function result sent back by the first component using a message, the control unit carries out a comparison with the identification forwarded during a preceding message exchange, and decides therefrom whether the first component is that component which is authorized for the use in this technical system.
6. The method according to claim 1, wherein, on the basis of a message transmission from the control unit, the first component sends back the corresponding message with the identification.
7. The method according to claim 1, wherein:
the assignment field is also stored in the control unit;
the control unit uses the at least one randomly generated or not easily reproducible value to generate an identification which corresponds to the identification transmitted by said first component; and
said control unit determines whether said first component is authorized for use based on a comparison of said identifications.