1461149910-442d5a48-2604-4743-8393-9d1828bc15f9

1. A method for estimating high-order Mel Frequency Cepstral Coefficients, the method comprising:
a) in an MFCC vector of length N having L low-order coefficients (LOC), initializing any of N-L high-order coefficients (HOC) of said MFCC vector to a predetermined value, thereby forming a candidate MFCC vector;
b) synthesizing a speech signal frame from said candidate MFCC vector and a pitch value; and
c) computing an N-dimensional MFCC vector from said synthesized frame, thereby producing an output MFCC vector.
2. A method according to claim 1 and further comprising performing said steps b)-c) up to a predetermined number of additional iterations, wherein the HOC of said output MFCC vector of a given iteration is appended to said LOC to form a new candidate MFCC vector for the next iteration.
3. A method according to claim 1 wherein said initializing step comprises initializing where said predetermined value is zero.
4. A method according to claim 1 wherein said synthesizing step comprises synthesizing from said candidate MFCC vector and said pitch value that are derived from the same speech signal.
5.-20. (canceled)
21. High-order Mel Frequency Cepstral Coefficient estimation apparatus comprising:
means for forming a candidate MFCC vector from an MFCC vector of length N having L low-order coefficients (LOC), operative to initialize any of N-L high-order coefficients (HOC) of said MFCC vector to a predetermined value;
a synthesizer operative to synthesize a speech signal frame from said candidate MFCC vector and a pitch value; and
means for computing an N-dimensional MFCC vector from said synthesized frame, operative to produce an output MFCC vector.
22. A Distributed Speech Recognition system employing MFCC vector HOC estimation, the system comprising:
speech recognition front-end apparatus operative to extract from each frame of an input speech signal a LOC, a pitch value, and a voicing class;
HOC restoration apparatus operative to:
form a candidate MFCC vector from said LOC and a plurality of HOC;
synthesize a speech signal frame from said candidate MFCC vector and said pitch value; and
apply speech recognition front-end processing to said synthesized frame, thereby producing an output MFCC vector;

speech recognition back-end apparatus operative to produce text from a plurality of said output MFCC vectors; and
speech reconstruction apparatus operative to synthesize speech from plurality of said output MFCC vectors, said pitch values, and said voicing class values.
23. (canceled)
24. A system according to claim 22 wherein said HOC restoration apparatus is operative to perform said forming, synthesizing, and performing up to a predetermined number of additional iterations, wherein the HOC of said output MFCC vector of a given iteration is appended to said LOC to form a new candidate MFCC vector for the next iteration.
25.-26. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A tone burst generator comprising:
means for generating a continuous tone signal; and
a circuit converting said continuous tone signal into a tone burst signal having predetermined transition times, said circuit including:
a differential pair of a first and a second transistor;
a common current path coupling the continuous tone signal to the differential pair; and
means for turning on and off one of the transistors to provide a tone burst signal having said predetermined transitions.
2. The generator of claim 1, wherein said turning on and off means causes said tone burst signal to have a rise and fall time of not less than about 100 microseconds.
3. The generator of claim 1, said first transistor having a gate, wherein said turning on and off means applies a control signal to the gate of the first transistor to turn it on and off.
4. The generator of claim 1, wherein each of the two transistors in said pair is connected to a common node through a resistor, said common current path being connected to said common node.
5. The generator of claim 4, wherein said common current path connects said common node to a reference electrical potential.
6. The generator of claim 5, wherein the reference potential is a negative voltage or ground.
7. The generator of claim 1, wherein said turning on and off means applies a control signal to the first transistor, said generator further comprising a second current path connected to the second transistor so that a tone burst signal having said predetermined transitions is provided by the second current path.
8. The generator of claim 7, further including means for biasing the second transistor at a predetermined voltage.
9. The generator of claim 8, said control signal having two voltage levels, said predetermined voltage being between the two voltage levels.
10. The generator of claim 8, said biasing means including a voltage divider circuit.
11. The generator of claim 7, said second current path including a resistor for providing said voltage tone burst signal.
12. The generator of claim 1, said transistors being bipolar or field effect transistors.
13. Apparatus for transmission of telephone signals comprising:
a transmission circuit including at least one first connection transmitting the telephone signals from a telephone company station to a subscriber location and at least one second connection receiving telephone signals from the subscriber location and transmitting such signals to the telephone company station; and
at least one generator supplying to said at least one first connection a tone burst signal having predetermined transitions, said at least one generator comprising:
means for generating a continuous tone signal;
a differential pair of a first and a second transistor;
a common current path coupling the continuous tone signal to the differential pair; and
means for turning on and off one of the transistors to provide a tone burst signal having predetermined transitions to provide to said at least one first connection a tone burst signal having said predetermined transitions.
14. The apparatus of claim 13, further comprising at least one cancellation circuit to reduce any echo of said tone burst signal.
15. The apparatus of claim 13, wherein said turning on and off means causes said tone burst signal to have a rise and fall time of not less than about 100 microseconds.
16. The apparatus of claim 13, said first transistor having a gate, wherein said turning on and off means applies a control signal to the gate of the first transistor.
17. The apparatus of claim 13, wherein each of the two transistors in said pair is connected to a common node through a resistor, said common current path being connected to said common node.
18. The apparatus of claim 17, wherein said common current path connects said common node to a reference node at an electrical potential.
19. The apparatus of claim 18, wherein the reference potential is a negative voltage or ground.
20. The apparatus of claim 18, said transmission circuit comprising a plurality of said first connections, and a plurality of said tone burst generators, each of said plurality of tone burst generators supplying a tone burst signal to a corresponding first connection.
21. The apparatus of claim 20, wherein the common current paths of said plurality of generators are connected to the same reference node.
22. The apparatus of claim 13, wherein said turning on and off means applies a control signal to the first transistor, said apparatus further comprising a second current path connected to the second transistor so that a tone burst signal having said predetermined transitions is provided by the second current path.
23. The apparatus of claim 22, further including means for biasing the second transistor at a predetermined voltage.
24. The apparatus of claim 23, said control signal having two voltage levels, said predetermined voltage being between the two voltage levels.
25. The apparatus of claim 23, said biasing means including a voltage divider circuit.
26. The apparatus of claim 23, said transmission circuit comprising a plurality of said first connections, and a plurality of said tone burst generators, each of said plurality of tone burst generators supplying a tone burst signal to a corresponding first connection, the second transistor of each of said plurality of generators being biased by the same biasing means.
27. The apparatus of claim 22, said second current path including a resistor for providing said voltage tone burst signal.
28. The apparatus of claim 13, said transistors being bipolar or field effect transistors.
29. The apparatus of claim 13, said transmission circuit further comprising a subscriber line circuit connected to the transmission circuit for transmitting and receiving the telephone signals on the first and second connections to a tip line and a ring line, said subscriber line circuit being an integrated circuit or a transformer.

1461149899-de94dbc0-d0e7-4185-9351-5cef6e096fd1

What is claimed is:

1. A method of reproducing information by scanning information marks, disposed with a predetermined mark pitch therebetween and recorded on tracks inside a predetermined information recording region, by an optical spot, detecting an optical change of said information marks by said scanning operation, applying signal processing to a reproducing signal obtained by said detection operation so as to reduce inter-symbol interference of an interference amount varying from one of said information marks to another of said information marks, and reproducing the information corresponding to said information mark, comprising the steps of:
a) detecting the size of the optical change resulting from said information mark;
b) calculating a plurality of equalization coefficients used for an equalization processing for the size of said optical change detected for each of said information marks; and
c) reducing said inter-symbol interference on the basis of said equalization coefficients by said equalization processing;
wherein said equalization coefficient used for said equalization processing of the size of said optical change by a first information mark of a first length to reduce said inter-symbol interference in said step c) is greater than said equalization coefficient used for said equalization processing of the size of said optical change by a second information mark of a second length which is greater than said first information mark.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computerized wagering game system, comprising:
a gaming module comprising gaming code which is operable to present a wagering game on which monetary value can be wagered; and
a security module operable to check the authenticity of a wagering game component using at least one of two or more available encryption keys.
2. The computerized wagering game system of claim 1, wherein the wagering game component comprises at least one of a BIOS, an operating system, a data volume, wagering game code, and a peripheral device.
3. The computerized wagering game system of claim 1, wherein at least one of the two or more available encryption keys are stored in a trusted platform module.
4. The computerized wagering game system of claim 1, wherein the two or more available encryption keys are each used to check authentication of the game component until the component is authenticated or all of the two or more available keys have been tried.
5. The computerized wagering game system of claim 1, wherein checking the authenticity of the component by using at least one encryption key comprises verifying a digital signature of the wagering game system component.
6. The computerized wagering game system of claim 5, wherein the digital signature of the wagering game system component comprises a digital signature of a hash value of a volume of data.
7. The computerized wagering game system of claim 1, wherein the authentication is performed in at least one of a pre-boot execution environment, a BIOS environment, or a booting operating system environment.
8. A method of operating a computerized wagering game system, comprising:
presenting a wagering game on which monetary value can be wagered; and
checking the authenticity of a wagering game component using at least one of two or more available encryption keys.
9. The method of operating a computerized wagering game system of claim 8, wherein checking the authenticity of a wagering game component occurs in at least one of a pre-boot execution environment, a BIOS environment, or a booting operating system environment.
10. The method of operating a computerized wagering game system of claim 8, wherein the wagering game component comprises at least one of a BIOS, an operating system, wagering game code, a peripheral device, and a data volume.
11. The method of operating a computerized wagering game system of claim 8, wherein authentication comprises using each of the two or more available encryption keys to attempt authentication of the game component until the component is authenticated or all of the two or more available keys have been tried.
12. The method of operating a computerized wagering game system of claim 8, wherein checking the authenticity of the component by using at least one encryption key comprises verifying a digital signature of the wagering game system component.
13. The method of operating a computerized wagering game system of claim 12, wherein the digital signature of the wagering game system component comprises a digital signature of a hash value of a volume of data.
14. The method of operating a wagering game system of claim 8, wherein checking the authenticity of the wagering game system component occurs in a trusted platform module.
15. The method of operating a wagering game system of claim 8, wherein the two or more available keys are stored in a trusted platform module.
16. A machine-readable medium with instructions stored thereon, the instructions when executed operable to cause a computerized wagering game system to:
present a wagering game on which monetary value can be wagered; and
check the authenticity of a wagering game component using at least one of two or more available encryption keys.
17. The machine-readable medium of claim 16, wherein checking the authenticity of a wagering game component occurs in at least one of a pre-boot execution environment, a BIOS environment, or a booting operating system environment.
18. The machine-readable medium of claim 16, wherein authentication comprises using each of the two or more available encryption keys to attempt authentication of the game component until the component is authenticated or all of the two or more available keys have been tried.
19. The machine-readable medium of claim 16, wherein confirming the authenticity of the component by using at least one encryption key comprises verifying a digital signature of the wagering game system component.
20. The machine-readable medium of claim 19, wherein the digital signature of the wagering game system component comprises a digital signature of a hash value of a volume of data.