Author: claimsbot

1. A monolithic three dimensional NAND string, comprising:
a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, and wherein the plurality of control gate electrodes extend through at least one memory cell region and at least one dummy channel region;
an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;
a memory opening located in the at least one memory cell region and extending substantially perpendicular to the major surface of the substrate, the memory opening filled with a memory opening material comprising:
a semiconductor channel located at least partially in the memory opening, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the substrate, at least one first portion of the semiconductor channel located in a first device level, and at least one second portion of the semiconductor channel located in a second device level; and
at least one memory film located at least partially in the memory opening and adjacent to the semiconductor channel;

one of a source or drain electrode which contacts the semiconductor channel from above or below; and
at least one dummy opening located in the at least one dummy channel region, the at least one dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material;
wherein the dummy channel material has a higher Young’s modulus than the memory opening material to offset warpage of the substrate due to one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
2. The monolithic three dimensional NAND string of claim 1, further comprising an electrode shunt extending substantially parallel to the major surface of the substrate and connected to the one of the source or drain electrode, the electrode shunt comprising a conductive electrode shunt material, wherein the dummy channel region is located under the electrode shunt.
3. The monolithic three dimensional NAND string of claim 1, wherein the dummy channel material comprises a material under compressive stress and the plurality of control gate electrodes are under tensile stress.
4. The monolithic three dimensional NAND string of claim 1, wherein the dummy channel material comprises a single material or a combination of more than one material, and the single dummy channel material or the combination dummy channel material has a higher Young’s modulus than the memory opening material.
5. The monolithic three dimensional NAND string of claim 1, wherein:
the plurality of control gate electrodes comprise an electrically conductive material; and
the dummy channel material comprises an electrically insulating material, or an electrically insulating shell and an electrically conductive or semiconductor core.
6. The monolithic three dimensional NAND string of claim 5, wherein:
the semiconductor channel material comprises silicon;
the plurality of control gate electrodes comprise tungsten or a tungsten alloy; and
the dummy channel material comprises silicon nitride, or a silicon oxide shell and a tungsten core.
7. The monolithic three dimensional NAND string of claim 1, wherein the at least one memory film comprises:
a blocking dielectric located in contact with the plurality of control gate electrodes and the interlevel insulating layer;
at least one charge storage region located at least partially in contact with the blocking dielectric; and
a tunnel dielectric located between the at least one charge storage region and the semiconductor channel.
8. The monolithic three dimensional NAND string of claim 7, further comprising an insulating core fill layer contacting the semiconductor channel.
9. The monolithic three dimensional NAND string of claim 1,
wherein the semiconductor channel has a pillar shape and extends substantially perpendicular to the major surface of the substrate; and
further comprising one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above, and another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.
10. The monolithic three dimensional NAND string of claim 1,
wherein the semiconductor channel has U-shaped pipe shape,
wherein two wing portions of the U-shaped pipe shape semiconductor channel extend substantially perpendicular to the major surface of the substrate and a connecting portion of the U-shaped pipe shape semiconductor channel which connects the two wing portions extends substantially parallel to the major surface of the substrate; and
wherein the one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and
further comprising another one of a source or drain electrode which contacts the second wing portion of the semiconductor channel from above.
11. The monolithic three dimensional NAND string of claim 2, wherein:
the semiconductor channel has J-shaped pipe shape;
a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate; and
the one of a source or drain electrode comprises a drain electrode contacts the first wing portion of the semiconductor channel from above; and
further comprising a source electrode which contacts the connecting portion of the semiconductor channel from above.
12. The monolithic three dimensional NAND string of claim 11, wherein:
the source electrode comprises a rail shaped electrode which electrically contacts the electrode shunt;
the source electrode is located in a dielectric insulated trench;
the source electrode extends substantially parallel to the plurality of control gate electrodes and substantially perpendicular to the electrode shunt;
the drain electrode is electrically connected to a bit line which is located above the semiconductor channel;
the bit line extends substantially perpendicular to the plurality of control gate electrodes and to the source electrode, and substantially parallel to the electrode shunt.
13. A method of making a monolithic three dimensional NAND string, comprising:
forming a stack of alternating first layers and second layers, wherein the stack of alternating first layers and second layers extend substantially parallel to a major surface of a substrate;
etching the stack to form at least one memory opening and at least one dummy opening, the at least one memory opening and the dummy opening extending substantially perpendicular to the major surface of the substrate;
forming a memory opening material comprising a semiconductor channel and a memory film in the at least one memory opening;
forming a dummy channel material which is different from the memory opening material in the at least one dummy opening, wherein the dummy channel material has a higher Young’s modulus than the memory opening material; and
forming a bit line over the semiconductor channel and the memory film located in the at least one memory opening.
14. The method of claim 13, further comprising forming an electrode shunt extending over the dummy channel material located in the at least one dummy opening.
15. The method of claim 13, wherein the at least one dummy opening is substantially the same size and shape as the at least one memory opening.
16. The method of claim 13, wherein the first layers comprise sacrificial layers and the second layers comprise insulating layers, and the method further comprises:
forming at least one back side opening in the stack;
selectively removing the first layers through the back side opening to form a plurality of back side recesses between the second layers; and
forming a plurality of control gate electrodes in the back side recesses.
17. The method of claim 16, wherein the plurality of control gate electrodes are under one of compressive and tensile stress and the dummy channel material has a higher Young’s modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.
18. The method of claim 13, wherein the dummy channel material comprises a single material or a combination of more than one material, and the single dummy channel material or the combination dummy channel material has a higher Young’s modulus than the memory opening material.
19. The method of claim 16, wherein:
the plurality of control gate electrodes comprise an electrically conductive material; and
the dummy channel material comprises an electrically insulating material, or an electrically insulating shell and an electrically conductive or semiconductor core.
20. The method of claim 19, wherein:
the semiconductor channel material comprises silicon;
the plurality of control gate electrodes comprise tungsten or a tungsten alloy; and
the dummy channel material comprises silicon nitride, or a silicon oxide shell and a tungsten core.
21. The method of claim 13, wherein:
the dummy channel has a circular cross section when viewed from above; and
the semiconductor channel has a circular cross section when viewed from above.
22. The method of claim 13, wherein:
the semiconductor channel has J-shaped pipe shape;
a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate;
a source region is located in electrical contact with the connecting portion and a drain region is located in electrical contact with the wing portion of the J-shaped pipe shape semiconductor channel; and
the back side opening comprises a trench which extends substantially perpendicular to the bit line.
23. The method of claim 22, further comprising:
forming an insulating layer on sidewalls of the trench;
forming a source electrode in the trench in contact with the source region; and
forming a drain electrode in contact with the drain region located above the semiconductor channel and in electrical contact with the bit line.
24. The method of claim 13, wherein:
etching the stack to form at least one memory opening and at least one dummy opening comprises a single etching step or separate etching steps;
the step of forming the semiconductor channel and the memory film in the at least one memory opening occurs before or after the step of forming the dummy channel material in the at least one dummy opening;
the step of forming the semiconductor channel and the memory film in the at least one memory opening occurs while the at least one dummy opening is either masked or filled with the dummy channel material;
the step of forming the dummy channel material in the at least one dummy opening occurs while the at least one memory opening is either masked or filled with the semiconductor channel and the memory film; and
the memory film comprises a blocking dielectric formed in at least one of the memory opening or the back side opening, a tunnel dielectric formed in the memory opening and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.
25. A monolithic three dimensional NAND memory device, comprising:
a silicon substrate;
an array of monolithic three dimensional NAND strings having a plurality of device levels disposed above the silicon substrate; and
a driver circuit associated with the array located above or in the silicon substrate;
wherein each monolithic three dimensional NAND string of the array of monolithic three dimensional NAND strings comprises:
a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, and wherein the plurality of control gate electrodes extend through at least one memory cell region and at least one dummy channel region;
an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;
a memory opening located in the at least one memory cell region and extending substantially perpendicular to the major surface of the substrate, the memory opening filled with a memory opening material comprising:
a semiconductor channel located at least partially in the memory opening, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the substrate, at least one first portion of the semiconductor channel located in a first device level, and at least one second portion of the semiconductor channel located in a second device level, and
at least one memory film located at least partially in the memory opening; and

one of a source or drain electrode which contacts the semiconductor channel from above or below; and

at least one dummy opening located in the at least one dummy channel region, the at least one dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material;
wherein the plurality of control gate electrodes are under one of compressive and tensile stress and the dummy channel material has a higher Young’s modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for transferring data between asynchronous clock domains, the asynchronous clock domains including a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal, comprising the operations of:
determining a phase shift relationship between the source clock signal and a signal;
transferring data between the source clock domain and the receiving clock domain using a first domain transfer logic when the phase shift relationship is below a predetermined threshold; and
transferring the data between the source clock domain and the receiving clock domain using a second domain transfer logic when the phase shift relationship is above the predetermined threshold, wherein the second domain transfer logic delays data transfer an additional half period of the source clock signal.
2. A method as recited in claim 1, wherein the first domain transfer logic includes a first plurality of stage operations that include:
latching the data on a rising edge of the source clock signal to generate stage one data; and
latching the stage one data on a falling edge of the receiving clock signal to generate stage two data.
3. A method as recited in claim 2, further including the operation of storing the stage two data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain.
4. A method as recited in claim 1, wherein the second domain transfer logic includes a second plurality of stage operations that include:
latching the data on a rising edge of the source clock signal to generate stage one data;
latching the stage one data on a falling edge of the source clock signal to generate stage two data; and
latching the stage two data on a falling edge of the receiving clock signal to generate stage three data.
5. A method as recited in claim 4, further including the operation of storing the stage three data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain.
6. A method as recited in claim 1, wherein the signal is a data strobe signal.
7. A method as recited in claim 6, wherein the data strobe signal has a fixed relationship with the receiving clock signal.
8. A method as recited in claim 1, wherein the receiving clock signal is a data clock signal.
9. A method for transferring data between asynchronous clock domains, the asynchronous clock domains including a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal, comprising the operations of:
determining a phase shift relationship between the first clock signal and a signal;
transferring data between the source clock domain and the receiving clock domain when the phase shift relationship is below a predetermined threshold using a first plurality of stage operations including:
latching the data on a rising edge of the source clock signal to generate stage one data; and
latching the stage one data on a falling edge of the receiving clock signal to generate stage two data; and

transferring the data between the source clock domain and the receiving clock domain using a second plurality of stage operations when the phase shift relationship is above the predetermined threshold, wherein the second plurality of operations delay data transfer an additional half period of the first source clock signal.
10. A method as recited in claim 9, further including the operation of storing the stage two data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain when the phase shift relationship is below a predetermined threshold.
11. A method as recited in claim 9, wherein the second plurality of stage operations includes:
latching the data on a rising edge of the source clock signal to generate stage one data;
latching the stage one data on a falling edge of the source clock signal to generate stage two data; and
latching the stage two data on a falling edge of the receiving clock signal to generate stage thee data.
12. A method as recited in claim 11, further including the operation of storing the stage three data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain when the phase shift relationship is above the predetermined threshold.
13. A method as recited in claim 9, further comprising the operations of transferring negative edge data between the source clock domain and the receiving clock domain when the phase shift relationship is below a predetermined threshold using a third plurality of stage operations including:
latching the negative edge data on a rising edge of the source clock signal to generate stage one negative edge data;
latching the stage one negative edge data on a falling edge of the source clock signal to generate stage two negative edge data; and
latching the stage two negative edge data on a rising edge of the receiving clock signal to generate stage three negative edge data.
14. A method as recited in claim 9, further comprising the operations of transferring negative edge data between the source clock domain and the receiving clock domain when the phase shift relationship is above a predetermined threshold using a fourth plurality of stage operations including:
latching the negative edge data on a rising edge of the source clock signal to generate stage one negative edge data;
latching the stage one negative edge data on a rising edge of the source clock signal to generate stage two negative edge data; and
latching the stage two negative edge data on a rising edge of the receiving clock signal to generate stage three negative edge data.
15. A memory controller capable of transferring data between asynchronous clock domains, the asynchronous clock domains including a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal, comprising:
logic that determines a phase shift relationship between the first clock signal and first signal;
logic that transfers data between the source clock domain and the receiving clock domain using a first domain transfer logic when the phase shift relationship is below a predetermined threshold; and
logic that transfers the data between the source clock domain and the receiving clock domain using a second domain transfer logic when the phase shift relationship is above the predetermined threshold, wherein the second domain transfer logic delays data transfer an additional half period of the first source clock signal.
16. A memory controller as recited in claim 15, wherein the first domain transfer logic includes a first plurality of stage operations that include:
latching the data on a rising edge of the source clock signal to generate stage one data; and
latching the stage one data on a falling edge of the receiving clock signal to generate stage two data.
17. A memory controller as recited in claim 16, further including logic that stores the stage two data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain.
18. A memory controller as recited in claim 15, wherein the second domain transfer logic includes a second plurality of stage operations that include:
latching the data on a rising edge of the source clock signal to generate stage one data;
latching the stage one data on a falling edge of the source clock signal to generate stage two data; and
latching the stage two data on a falling edge of the receiving clock signal to generate stage thee data.
19. A memory controller as recited in claim 18, further including logic that stores the stage three data on a rising edge of the receiving clock to generate synchronized data operable to be supplied to circuitry disposed in the receiving clock domain.
20. A memory controller as recited in claim 15, wherein the signal is a data strobe signal that having a fixed relationship with the receiving clock signal.

1. A method of processing video data, the method comprising:
determining, based at least in part on a syntax element in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
when the nested SEI message is applicable to the default sub-bitstream, using the nested SEI message in an operation on the default sub-bitstream.
2. The method of claim 1, wherein a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier.
3. The method of claim 2, wherein the default sub-bitstream is a subset of an encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
4. The method of claim 1, wherein the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters.
5. The method of claim 4, wherein using the nested SEI message comprises using the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
6. The method of claim 1, wherein using the nested SEI message comprises using the nested SEI message in a decoding operation on the default sub-bitstream.
7. The method of claim 1, wherein:
the scalable nesting SEI message encapsulates a plurality of nested SEI messages, and
determining whether the nested SEI message is applicable to the default sub-bitstream comprises determining, based at least in part on the syntax element, whether each of the nested SEI messages is applicable to the default sub-bitstream.
8. The method of claim 1, wherein:
the syntax element in the scalable nesting SEI message is a first syntax element, and
the method further comprises determining, based at least in part on a second syntax element in the scalable nesting SEI message indicating that nested SEI messages encapsulated by the scalable nesting SEI message apply to a sub-bitstream extracted from the encoded video bitstream, that the scalable nesting SEI message includes the first syntax element.
9. The method of claim 1, wherein the method further comprises:
determining, based on one or more additional syntax elements in the scalable nesting SEI message, a temporal identifier of a second operation point and a maximum layer identifier of the second operation point; and
using the nested SEI message in an operation on an additional sub-bitstream, the additional sub-bitstream being an operation point representation of the second operation point.
10. A device comprising one or more processors configured to:
determine, based at least in part on a syntax element in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
when the nested SEI message is applicable to the default sub-bitstream, use the nested SEI message in an operation on the default sub-bitstream.
11. The device of claim 10, wherein a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier.
12. The device of claim 11, wherein the default sub-bitstream is a subset of the encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
13. The device of claim 10, wherein the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters.
14. The device of claim 13, wherein the one or more processors are configured to use the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
15. The device of claim 10, wherein the one or more processors are configured to use the nested SEI message in a decoding operation on the default sub-bitstream.
16. The device of claim 10, wherein:
the scalable nesting SEI message encapsulates a plurality of nested SEI messages, and
the one or more processors are configured to determine, based at least in part on the syntax element, whether each of the nested SEI messages is applicable to the default sub-bitstream.
17. The device of claim 10, wherein:
the syntax element in the scalable nesting SEI message is a first syntax element, and
the one or more processors are further configured to determine, based at least in part on a second syntax element in the scalable nesting SEI message indicating that nested SEI messages encapsulated by the scalable nesting SEI message apply to a sub-bitstream extracted from the encoded video bitstream, that the scalable nesting SEI message includes the first syntax element.
18. The device of claim 10, wherein the one or more processors are further configured to:
determine, based on one or more additional syntax elements in the scalable nesting SEI message, a temporal identifier of a second operation point and a maximum layer identifier of the second operation point; and
use the nested SEI message in an operation on an additional sub-bitstream, the additional sub-bitstream being an operation point representation of the second operation point.
19. A device comprising:
means for determining, based at least in part on a syntax element in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
means for using, when the nested SEI message is applicable to the default sub-bitstream, the nested SEI message in an operation on the default sub-bitstream.
20. The device of claim 19, wherein:
a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier, and the default sub-bitstream is a subset of an encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
21. The device of claim 19, wherein:
the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters, and
the device comprises means for using the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
22. A computer-readable storage medium that stores instructions that, when executed by one or more processors of a device, configure the device to:
determine, based at least in part on a syntax element in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
when the nested SEI message is applicable to the default sub-bitstream, use the nested SEI message in an operation on the default sub-bitstream.
23. The computer-readable storage medium of claim 22, wherein:
a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier, and
the default sub-bitstream is a subset of an encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
24. The computer-readable storage medium of claim 22, wherein:
the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters, and
the instructions further configure the device to use the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
25. A method of encoding video data, the method comprising:
including, in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, a syntax element that indicates whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
signaling the scalable nesting SEI message in the encoded video bitstream.
26. The method of claim 25, wherein a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier.
27. The method of claim 26, wherein the default sub-bitstream is a subset of the encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
28. The method of claim 25, wherein the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters.
29. The method of claim 28, further comprising using the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
30. The method of claim 25, wherein:
the scalable nesting SEI message encapsulates a plurality of nested SEI messages, and
the syntax element indicates whether each of the nested SEI messages is applicable to the default sub-bitstream.
31. The method of claim 25, wherein:
the syntax element in the scalable nesting SEI message is a first syntax element in the scalable nesting SEI message,
the method further comprises including a second syntax element in the scalable nesting SEI message, the second syntax element indicating whether nested SEI messages encapsulated by the scalable nesting SEI message apply to a sub-bitstream extracted from the encoded video bitstream or whether the nested SEI messages apply to specific layers and sub-layers of the encoded video bitstream, and
the scalable nesting SEI message includes the first syntax element only when the second syntax element indicates that the nested SEI messages apply to the sub-bitstream extracted from the encoded video bitstream.
32. The method of claim 25, wherein:
the operation point identified by one or more syntax elements of a NAL unit header of the SEI NAL unit is a first operation point, and
the method further comprises including, in the scalable nesting SEI message, one or more additional syntax elements that identify a temporal identifier of a second operation point and a maximum layer identifier of the second operation point.
33. A video encoding device comprising one or more processors configured to:
include, in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, a syntax element that indicates whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
signal the scalable nesting SEI message in the encoded video bitstream.
34. The video encoding device of claim 33, wherein a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier.
35. The video encoding device of claim 34, wherein the default sub-bitstream is a subset of the encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
36. The video encoding device of claim 33, wherein the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters.
37. The video encoding device of claim 36, wherein the one or more processors are further configured to use the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
38. The video encoding device of claim 33, wherein:
the scalable nesting SEI message encapsulates a plurality of nested SEI messages, and
the syntax element indicates whether each of the nested SEI messages is applicable to the default sub-bitstream.
39. The video encoding device of claim 33, wherein:
the syntax element in the scalable nesting SEI message is a first syntax element in the scalable nesting SEI message,
the one or more processors are further configured to include a second syntax element in the scalable nesting SEI message, the second syntax element indicating whether nested SEI messages encapsulated by the scalable nesting SEI message apply to a sub-bitstream extracted from the encoded video bitstream or whether the nested SEI messages apply to specific layers and sub-layers of the encoded video bitstream, and
the scalable nesting SEI message includes the first syntax element only when the second syntax element indicates that the nested SEI messages apply to the sub-bitstream extracted from the encoded video bitstream.
40. The video encoding device of claim 33, wherein:
the operation point identified by one or more syntax elements of a NAL unit header of the SEI NAL unit is a first operation point, and
the one or more processors are further configured to include, in the scalable nesting SEI message, one or more additional syntax elements that identify a temporal identifier of a second operation point and a maximum layer identifier of the second operation point.
41. A video encoding device comprising:
means for including, in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, a syntax element that indicates whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
means for signaling the scalable nesting SEI message in the encoded video bitstream.
42. The video encoding device of claim 41, wherein:
a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier, and
the default sub-bitstream is a subset of an encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
43. The video encoding device of claim 41, wherein:
the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters, and
the video encoding device comprises means for using the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.
44. A computer-readable storage medium that stores instructions that, when executed by a video encoding device, configure the video encoding device to:
include, in a scalable nesting supplemental enhancement information (SEI) message encapsulated by an SEI Network Abstraction Layer (NAL) unit, a syntax element that indicates whether a nested SEI message encapsulated by the scalable nesting SEI message is applicable to a default sub-bitstream of an encoded video bitstream, wherein the default sub-bitstream is an operation point representation of an operation point defined by a layer identifier specified in a NAL unit header of the SEI NAL unit and a temporal identifier specified in the NAL unit header; and
signal the scalable nesting SEI message in the encoded video bitstream.
45. The computer-readable storage medium of claim 44, wherein:
a first syntax element in the NAL unit header indicates the layer identifier and a second syntax element in the NAL unit header indicates the temporal identifier, and the default sub-bitstream is a subset of an encoded video bitstream and the default sub-bitstream does not include video coding layer (VCL) NAL units of the encoded video bitstream that have layer identifiers greater than the layer identifier indicated by the first syntax element of the NAL unit header or have temporal identifiers greater than the temporal identifier indicated by the second syntax element of the NAL unit header.
46. The computer-readable storage medium of claim 44, wherein:
the nested SEI message includes a set of hypothetical reference decoder (HRD) parameters, and
the instructions further configure the video encoding device to use the HRD parameters in the nested SEI message in an operation that tests whether the default sub-bitstream conforms to a video coding standard.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A bumper assembly comprising:
a backing, wherein said backing is substantially rigid;
an outer layer, wherein said outer layer semi-flexible, resilient, and non-conductive;
a cushion layer sandwiched between said backing and said outer layer, wherein said cushion layer is resiliently compressible.
2. The bumper assembly recited in claim 1, wherein said outer layer comprises hard plastic and said cushion layer comprises foam rubber.
3. The bumper assembly recited in claim 1, wherein said bumper assembly is installed as a substantially continuous ring about a go-kart.
4. The bumper assembly recited in claim 3, wherein said go-kart comprises a chassis, said chassis comprises said backing, wherein said outer layer comprises hard plastic, and wherein said cushion layer comprises foam rubber.
5. The bumper assembly recited in claim 4 wherein said outer layer comprises an outer lateral surface, and wherein at least one conductive contact is arranged on said outer lateral surface, and wherein said at least one conductive contact is electrically connected to a rechargeable battery of said go-kart.
6. The bumper assembly recited in claim 1, wherein said bumper assembly is arranged on a floor to define a track for vehicles, wherein said outer layer faces said track.
7. The bumper assembly recited in claim 6 further comprising a plurality of rods vertically extending from said floor at spaced intervals behind said backing for rigidly supporting said bumper assembly.
8. The bumper assembly recited in claim 7, wherein each of said rods includes a portion that extends down into said floor.
9. The bumper assembly recited in claim 8, wherein a brittleness of each of said rods enables said rods to shear or break between said backing and said floor if said rods experience a threshold force exerted by said backing
10. The bumper assembly recited in claim 7 further comprising a plurality of ties, wherein each of said ties corresponds with one of said rods, and each tie is operatively arranged for securing said outer layer, said cushion layer, and said backing to one of said rods.
11. The bumper assembly recited in claim 10, wherein said ties comprise plastic tie-wraps.
12. The bumper assembly recited in claim 7, wherein said backing comprises first and second backings, said cushion layer comprises first and second cushion layers, and said outer layer comprises first and second outer layers, wherein said first cushion layer is sandwiched between said first outer layer and said first backing for forming a first bumper portion and wherein said second cushion layer is sandwiched between said second outer layer and said second backing for forming a second bumper portion, and wherein said first and second bumper portions are arranged on oppositely disposed sides of said rods.
13. The bumper assembly recited in claim 12 further comprising a plurality of ties, wherein each of said ties corresponds to one of said rods, and wherein each of said ties is operatively arranged to secure both of said first and second bumper portions to common ones of said rods.
14. A system for electric vehicles comprising:
a track;
a pit area connected to said track and having at least one charging station, said charging station comprising:
a battery charger providing a voltage source;
at least one first contact electrically connected to said charging station, wherein said at least one first contact is arranged on a vertically oriented surface of said charging station; and,

an electric vehicle comprising:
a rechargeable battery;
a bumper having an outer lateral surface; and,
at least one second contact electrically connected to said rechargeable battery for completing a charging circuit between said battery charger and said battery when said second contact is engaged against and electrically connected to said first contact for recharging said battery.
15. The system of claim 14, wherein a cushion layer is provided behind said at least one first contact for enabling said at least one first contact to flex away from said bumper in case of interference between said at least one first contact and said at least one second contact for providing mating engagement of said first and second contacts against each other.
16. The system of claim 14, wherein said at least one first contact comprises two first contacts, said at least one second contact comprises two second contacts, and wherein a charging circuit for recharging said battery is completed only when each first contact is engaged against and conductively connected with respective ones of said second contacts.
17. A charging station comprising:
a battery charger providing a voltage source;
two conductive faceplates, wherein each conductive faceplate is electrically connected to said battery charger, wherein both of said conductive faceplates are arranged on a vertical surface.
18. The charging station recited in claim 17, wherein a cushion layer is provided behind said conductive faceplates for enabling said faceplates to move forward and back with respect to said vertical surface.