Author: claimsbot

1. A pixel, comprising:
an organic light emitting diode;
a second transistor coupled between a first power source and the organic light emitting diode for controlling an amount of current supplied from the first power source to the organic light emitting diode;
a third transistor coupled between a first electrode of the second transistor and the first power source, the third transistor configured to turn off when a light emission control signal is applied to a light emission control line coupled to a gate electrode of the third transistor;
a first transistor coupled between a gate electrode of the second transistor and a data line, the first transistor configured to turn on when a scan signal is applied to a scan line coupled to a gate electrode of the first transistor;
a first capacitor coupled between the gate electrode and the first electrode of the second transistor;
a second capacitor coupled between the first electrode of the second transistor and the first power source; and
a compensation circuit coupled between the organic light emitting diode and the gate electrode of the second transistor, the compensation circuit for adjusting a voltage at the gate electrode of the second transistor in accordance with degradation of the organic light emitting diode.
2. The pixel according to claim 1, wherein a capacitance of the second capacitor is greater than a capacitance of the first capacitor.
3. The pixel according to claim 2, wherein the capacitance of the second capacitor is 2 to 10 times the capacitance of the first capacitor.
4. The pixel according to claim 1, wherein the compensation circuit comprises:
a third capacitor having a first terminal coupled to the gate electrode of the second transistor;
a fourth transistor coupled between a second terminal of the third capacitor and an anode electrode of the organic light emitting diode, the fourth transistor configured to turn on when the scan signal is applied to the scan line coupled to a gate electrode of the fourth transistor; and
a fifth transistor coupled between the second terminal of the third capacitor and a reference power source, the fifth transistor configured to turn off when the light emission control signal is applied to the light emission control line coupled to a gate electrode of the fifth transistor.
5. The pixel according to claim 4, wherein a voltage of the reference power source is higher than a threshold voltage of the organic light emitting diode.
6. An organic light emitting display device, comprising:
a scan driver for applying scan signals to a plurality of scan lines and applying light emission control signals to a plurality of light emission control lines;
a data driver for supplying a reset power voltage and applying data signals to a plurality of data lines; and
a plurality of pixels arranged at crossing regions of the plurality of data lines and the plurality of scan lines, each of the plurality of pixels comprising:
an organic light emitting diode;
a second transistor coupled between a first power source and the organic light emitting diode, the second transistor for controlling an amount of current supplied from the first power source to the organic light emitting diode;
a third transistor coupled between a first electrode of the second transistor and the first power source, the third transistor configured to turn off when a light emission control signal is applied to a corresponding light emission control line coupled to a gate electrode of the third transistor;
a first transistor coupled between a gate electrode of the second transistor and a corresponding data line, the first transistor configured to turn on when a scan signal is applied to a corresponding scan line coupled to a gate electrode of the first transistor;
a first capacitor coupled between the gate electrode and the first electrode of the second transistor;
a second capacitor coupled between the first electrode of the second transistor and the first power source; and
a compensation circuit coupled between the organic light emitting diode and the gate electrode of the second transistor, the compensation circuit for adjusting a voltage at the gate electrode of the second transistor in accordance with degradation of the organic light emitting diode.
7. The organic light emitting display device according to claim 6, wherein a capacitance of the second capacitor is greater than a capacitance of the first capacitor.
8. The organic light emitting display device according to claim 7, wherein the capacitance of the second capacitor is 2 to 10 times the capacitance of the first capacitor.
9. The organic light emitting display device according to claim 6, wherein the scan driver is configured to apply a light emission control signal to an ith light emission control line during a second portion and a third portion of a period in which a scan signal is being applied to a corresponding ith scan line.
10. The organic light emitting display device according to claim 9, wherein the scan driver is configured to stop the application of the light emission control signal to the ith light emission control line after the application of the scan signal to the corresponding ith scan line is stopped.
11. The organic light emitting display device according to claim 9, wherein the data driver is configured to supply the reset power voltage to the plurality of data lines during a first portion and the second portion of the period, and configured to apply data signals to the plurality of data lines during the third portion of the period.
12. The organic light emitting display device according to claim 6, wherein the compensation circuit comprises:
a third capacitor having a first terminal coupled to the gate electrode of the second transistor;
a fourth transistor coupled between a second terminal of the third capacitor and an anode electrode of the organic light emitting diode, the fourth transistor configured to turn on when the scan signal is applied to the corresponding scan line coupled to a gate electrode of the fourth transistor; and
a fifth transistor coupled between the second terminal of the third capacitor and a reference power source, the fifth transistor configured to turn off when the light emission control signal is applied to the corresponding light emission control line coupled to a gate electrode of the fifth transistor.
13. The organic light emitting display device according to claim 12, wherein a voltage of the reference power source is higher than a threshold voltage of the organic light emitting diode.
14. The organic light emitting display device according to claim 6, wherein the reset power voltage is higher than the data signal.
15. The organic light emitting display device according to claim 14, wherein the reset power voltage is lower than a voltage of the first power source.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A N-(6-piperazin-1-ylpyridin-3-yl)benzenesulfonamide compound of the formula I
wherein
R1 is selected from the group consisting of hydrogen, linear C1-C3 alkyl and fluorinated linear C1-C3 alkyl;
R2 is hydrogen or methyl;
R3 is selected from the group consisting of hydrogen, halogen, C1-C2-alkyl, fluorinated C1-C2-alkyl, C1-C2-alkoxy and fluorinated C1-C2-alkoxy,
R4 is C1-C2-alkyl or fluorinated C1-C2-alkyl;
n is 0, 1 or 2;
and a physiologically tolerated salt thereof, or a N-oxide thereof.
2. The compound as claimed in claim 1, wherein R1 is hydrogen.
3. The compound as claimed in claim 1, wherein R2 is methyl.
4. The compound as claimed in claim 3, wherein the carbon atom that carries R2 has an S-configuration.
5. The compound as claimed in claim 3, wherein the carbon atom that carries R2 has an R-configuration.
6. The compound as claimed in claim 1, wherein R2 is hydrogen.
7. The compound as claimed in claim 1, wherein R3 is methyl.
8. The compound as claimed in claim 1, wherein R4 is methyl.
9. The compound as claimed in claim 8, wherein the carbon atom that carries R4 has an S-configuration.
10. The compound as claimed in claim 8, wherein the carbon atom that carries R4 has an R-configuration.
11. The compound as claimed in claim 1, wherein n is 1.
12. The compound as claimed in claim 1, wherein n is 2.
13. The compound of claim 1, selected from the group consisting of:
4-(2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-(3-methyl-piperazin-1-yl)-pyridin-3-ylbenzenesulfonamide
4-((R)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-((R)-3-methyl-piperazin-1-yl) pyridin-3-yl-benzenesulfonamide
4-((S)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-((S)-3-methyl-piperazin-1-yl) pyridin-3-yl-benzenesulfonamide
4-((R)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-((S)-3-methyl-piperazin-1-yl) pyridin-3-yl-benzenesulfonamide
4-((S)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-((R)-3-methyl-piperazin-1-yl)pyridin-3-yl-benzenesulfonamide
4-(2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-piperazin-1-yl-pyridin-3-ylbenzenesulfonamide
4-((R)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-piperazin-1-yl-pyridin-3-ylbenzenesulfonamide
4-((S)-2-Fluoro-1-methyl-ethyl)-N-2-methyl-6-piperazin-1-yl-pyridin-3-ylbenzenesulfonamide
and a physiologically tolerated salt thereof.
14. The compound of claim 1, selected from the group consisting of:
4-(2,2-Difluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((S)-2,2-Difluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((R)-2,2-Difluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
and a physiologically tolerated salt thereof.
15. The compound of claim 1, selected from the group consisting of:
4-(2,2,2-Trifluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((R)-2,2,2-Trifluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((S)-2,2,2-Trifluoro-1-methyl-ethyl)-N-(2-methyl-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
and a physiologically tolerated salt thereof.
16. The compound of claim 1, selected from the group consisting of:
4-(2-Fluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((R)-2-Fluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((S)-2-Fluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-(2,2-Difluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
4-((S)-2,2-Difluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl) benzenesulfonamide
4-((R)-2,2-Difluoro-1-methyl-ethyl)-N-(2-methoxy-6-piperazin-1-yl-pyridin-3-yl)benzenesulfonamide
N-(2-Methoxy-6-piperazin-1-yl-pyridin-3-yl)-4-(2,2,2-trifluoro-1-methyl-ethyl)benzenesulfonamide
N-(2-Methoxy-6-piperazin-1-yl-pyridin-3-yl)-4-((S)-2,2,2-trifluoro-1-methyl-ethyl)benzenesulfonamide
N-(2-Methoxy-6-piperazin-1-yl-pyridin-3-yl)-4-((R)-2,2,2-trifluoro-1-methyl-ethyl)benzenesulfonamide
and a physiologically tolerated salt thereof.
17. A pharmaceutical composition comprising at least one compound as claimed in claim 1, optionally together with at least one physiologically acceptable carrier or auxiliary substance.
18. The use of a compound as claimed in claim 1 for preparing a medicament.
19. A compound as claimed in claim 1 for the use as a medicament.
20. The use of a compound as claimed in claim 1 for treating a medical disorder susceptible to treatment with a dopamine D3 receptor ligand.
21. The use of a compound as claimed in claim 1 for preparing a medicament for treating a medical disorder susceptible to treatment with a dopamine D3 receptor ligand.
22. A method for treating a medical disorder susceptible to treatment with a dopamine D3 receptor ligand, said method comprising administering an effective amount of at least one compound as claimed in claim 1 to a subject in need thereof.
23. A method for treating a disorder of the central nervous system, said method comprising administering an effective amount of at least one compound as claimed in claim 1 to a subject in need thereof.
24. The method as claimed in claim 22, wherein the medical disorder is schizophrenia.
25. The method as claimed in claim 22, wherein the medical disorder is drug addiction.
26. The method as claimed in claim 22, wherein the medical disorder is diabetic nephropathy.
27. The method as claimed in claim 22, wherein the medical disorder is bipolar disorder.
28. A compound of the formula IV
wherein Ra is an N-protecting group and wherein n, R2, R3 and R4 are as defined in claim 1.

1. A computer implemented method for writing data, the method comprising:
receiving write data to be encoded into a write word;
receiving constraints on symbol values associated with the write word;
encoding the write data into the write word, the encoding comprising:
representing the write data and the constraints as a first linear system in a first field of a first size;
embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size;
solving the second linear system in the second field resulting in a solution; and
collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word; and
writing the write word to a memory.
2. The method of claim 1, wherein the first and second fields are Galois fields.
3. The method of claim 1, wherein the memory is a phase change memory (PCM).
4. The method of claim 1, wherein the constraints are due to physical defects in the memory.
5. The method of claim 1, wherein the second linear system is represented as Vandermonde matrix.
6. The method of claim 5, wherein the Vandermonde matrix contains powers of symbols denoting locations of constrained symbol values.
7. The method of claim 1, wherein the first linear system includes an underspecified system of equations.
8. The method of claim 1, wherein the collapsing includes multiplying a matrix times the solution.
9. The method of claim 1 wherein the collapsing the solution includes multiplying a matrix times the solution and adding it to a result of multiplying a different matrix times the write data.
10. A memory system comprising:
a memory including memory cells and constraints on symbol values stored in the memory cells; and
an encoder in communication with the memory, the encoder configured for:
receiving write data to be encoded into a write word that satisfies the constraints on the symbol values;
encoding the write data into the write word, the encoding comprising:

representing the write data and the constraints as a first linear system in a first field of a first size;
embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size;
solving the second linear system in the second field resulting in a solution; and
collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values in the write word; and

transmitting the write word to the memory.
11. The system of claim 10, wherein the first and second fields are Galois fields.
12. The system of claim 10, wherein the memory is a phase change memory (PCM).
13. The system of claim 10, wherein the constraints are constrained values.
14. The system of claim 10, wherein the second linear system is represented as Vandermonde matrix.
15. The system of claim 10, wherein the first linear system includes an underspecified system of equations.
16. The system of claim 10, wherein the collapsing includes multiplying a matrix times the solution.
17. A computer implemented method for transmitting data, the method comprising:
receiving data to be encoded into a word for transmission across a transmission medium;
receiving constraints on symbol values associated with the word;
encoding the data into the word, the encoding comprising:
representing the data and the constraints as a first linear system in a first field of a first size;
embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size;
solving the second linear system in the second field resulting in a solution; and
collapsing the solution into the first field resulting in the word, the word satisfying the constraints on symbol values associated with the word; and
outputting the word on the transmission medium.
18. The method of claim 17, wherein the first and second fields are Galois fields.
19. The method of claim 17, wherein the constraints are constrained values.
20. The method of claim 17, wherein the first linear system is represented as Vandermonde matrix.
21. The method of claim 17, wherein the second linear system includes an underspecified system of equations.
22. The method of claim 17, wherein the collapsing includes multiplying a matrix times the solution.
23. A computer implemented method for solving linear systems, the method comprising:
receiving a linear system of equations in a first field of a first size;
embedding the linear system of equations into a second field of a second size, the second size larger than the first size;
solving the linear system of equations in the second field resulting in a second field solution; and
collapsing the second field solution into the first field resulting in a first field solution; and
outputting the first field solution.
24. The method of claim 23, wherein the first and second fields are Galois fields.
25. The method of claim 23 wherein the constraints are constrained values.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A host processor so configured as to provide an application programming interface between a host computer driver and a telephone data processing system capable of processing both analog-type telephone calls and ISDN telephone calls, said application programming interface comprising:
a host interface that transfers signals to and from the host computer driver;
a modem interface that transfers signals to and from the host interface and that transfers commands and data associated with analog type telephone calls to and from a modem processor in the telephone data processing system, the modem processor processing analog type telephone calls; and
an ISDN interface that transfers signals to and from the host interface and that transfers commands and data associated with ISDN telephone calls to and from an ISDN processor in the telephone data processing system, the ISDN processor processing ISDN telephone calls.
2. A host processor as defined by claim 1 wherein the modem interface transfers commands and data to and from the modem processor to process multiple simultaneous analog-type telephone calls.
3. A host processor as defined by claim 1 wherein the ISDN interface transfers commands and data to and from the ISDN processor to process multiple simultaneous ISDN telephone calls.
4. A host processor as defined by claim 1 wherein the host interface transfers signals to and from the host driver to process multiple analog-type and ISDN telephone calls.
5. A host processor as defined by claim 1 wherein the signals transferred to and from the host computer driver are independent of the call type of the telephone call being processed.
6. An apparatus for providing an application programming interface between a host computer driver and a telephone data processing system capable of processing both analog-type telephone calls and ISDN telephone calls, said application programming interface comprising:
host interface means for implementing a host interface that transfers signals to and from the host computer driver;
modem interface means for implementing a modem interface that transfers signals to and from the host interface and that transfers commands and data associated with analog type telephone calls to and from a modem processor in the telephone data processing system, the modem processor processing analog type telephone calls; and
ISDN interface means for transferring signals to and from the host interface means and transferring commands and data associated with ISDN telephone calls to and from an ISDN processor in the telephone data processing system, the ISDN processor processing ISDN telephone calls.
7. An apparatus as defined by claim 6 wherein the modem interface means transfers commands and data to and from the modem processor to process multiple simultaneous analog-type telephone calls.
8. An apparatus as defined by claim 6 wherein the ISDN interface means transfers commands and data to and from the ISDN processor to process multiple simultaneous ISDN telephone calls.
9. An apparatus as defined by claim 6 wherein the host interface means transfers signals to and from the host driver to process multiple analog-type and ISDN telephone calls.
10. An apparatus as defined by claim 6 wherein the signals transferred to and from the host computer driver are independent of the call type of the telephone call being processed.