Author: claimsbot

1. A light emitting device package comprising:
a substrate with a recess;
a metal layer on the substrate; and
a light emitting device electrically connected to the metal layer and installed on the substrate,
wherein a side surface of the substrate has a convex structure, the convex structure having a first inclined surface and a second inclined surface contacting with each other,
wherein the metal layer comprises a plurality of protrusions, and
wherein the metal layer has a first metal portion in the recess and a second metal portion extending from the first metal portion and disposed on at least a portion of a bottom surface of the substrate
2. The light emitting device package according to claim 1, wherein a part of the second metal portion overlaps the first metal portion.
3. The light emitting device package according to claim 1, wherein the first inclined surface of the convex structure is substantially symmetrical to the first inclined surface of the convex structure with respect to a horizontal line.
4. The light emitting device package according to claim 1, wherein the first inclined surface has an acute angle with respect to the second inclined surface.
5. The light emitting device package according to claim 1, wherein at least one of the first and second inclined surfaces is flat.
6. The light emitting device package according to claim 1, wherein the first inclined surface contacts the bottom surface of the substrate, and
the first inclined surface has an obtuse angle with respect to the bottom surface of the substrate.
7. The light emitting device package according to claim 1, wherein the second inclined surface contacts a top surface of the substrate, and
the second inclined surface has an obtuse angle with respect to the top surface of the substrate.
8. The light emitting device package according to claim 1, wherein the convex structure is disposed along the side surface of the substrate.
9. The light emitting device package according to claim 1, wherein the convex structure protrudes from the side surface of the substrate toward a lateral direction
10. The light emitting device package according to claim 1, wherein the substrate has first and second portions having different thickness.
11. The light emitting device package according to claim 10, wherein the first portion has the recess and the second portion surrounds the first portion.
12. The light emitting device package according to claim 11, wherein a thickness of the light emitting device is smaller than a thickness of the first portion of the substrate.
13. The light emitting device package according to claim 1, wherein a depth of the recess is greater than a thickness of the light emitting device.
14. The light emitting device package according to claim 1, wherein the metal layer has a multiple structure.
15. The light emitting device package according to claim 1, wherein the side surface of the recess has an inclined surface.
16. The light emitting device package according to claim 15, wherein the metal layer is disposed on the inclined surface.
17. The light emitting device package according to claim 1, wherein the metal layer has a top surface and a bottom surface opposite to each other, at least one of the top surface and the bottom surface each having a roughness structure.
18. The light emitting device package according to claim 1, wherein the metal layer is disposed on an outer side surface of the substrate.
19. The light emitting device package according to claim 1, wherein the light emitting device is disposed on the first metal portion of the metal layer in the recess.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A kit of parts for gene delivery to a recipient cell in a host, using a gene delivery vehicle to which a humoral response can be raised, comprising a nucleic acid comprising a gene to be delivered to said recipient cell and further comprising a second composition of a second gene delivery vehicle essentially identical to said first gene delivery vehicle, but preferably lacking said gene to be delivered.
2. A kit of parts according to claim 1, wherein said second composition is a vaccine and wherein said first composition is a composition for gene therapy.
3. A kit of parts according to claim 2, wherein said vaccine is to be administered at a time before said gene therapy composition at a moment in time sufficient for the host to raise a neutralising humoral response to said second gene delivery vehicle.
4. A kit of parts according to any one of claims 1-3, wherein said second gene delivery vehicle comprises a nucleic acid encoding an indifferent protein.
5. A kit of parts according to any one of claims 1-4, wherein a gene delivery vehicle is of adenoviral origin.
6. A kit of parts according to any one of claims 2-5, wherein said gene therapy composition comprises a number of first gene delivery vehicles above the number that can be neutralised by a humoral response of said host.
7. A method for delivering a gene of interest to a recipient cell in a host using a gene delivery vehicle comprising a nucleic acid comprising said gene of interest, said method comprising administering to a host a vaccine composition comprising a gene delivery vehicle lacking said gene to be delivered, allowing for a neutralising humoral response to be raised by said host to said gene delivery vehicle lacking said gene to be delivered and administering a composition for gene therapy comprising essentially the same gene delivery vehicle having a nucleic acid comprising said gene to be delivered in an amount greater than the amount which can be neutralised by said humoral response.
8. A method for avoiding or diminishing liver toxicity in a host of a gene delivery composition upon administration, comprising administering to a host a vaccine composition comprising a gene delivery vehicle, preferably lacking said gene to be delivered, allowing for a neutralising humoral response to be raised by said host to said gene delivery vehicle lacking preferably said gene to be delivered and administering a composition for gene therapy comprising essentially the same gene delivery vehicle having a nucleic acid comprising said gene to be delivered in an amount greater than the amount which can be neutralised by said humoral response.
9. A method according to claim 7 or 8, wherein said gene delivery vehicle is of adenoviral origin.
10. A kit of parts according to any one of claims 1-6 in the preparation of a pharmaceutical for the use as a pharmaceutical.
11. Use of a kit of parts according to any one of claims 1-6 in the preparation of pharmaceutical for the treatment of diseases associated with uncontrolled proliferation of cells in a host, such as tumors or autoimmune diseases.
12. Use of a kit of parts according to any one of claims 1-6 in the preparation of a pharmaceutical for the treatment of diseases associated with genetic defects in a host.
13. A kit of parts according to any one of claims 1-6, wherein said gene of interest is interleukin-3.
14. A method for the preparation of a kit of parts according to anyone of claims 1-6, comprising preparing at least one gene delivery vehicle by inserting a gene of interest in a nucleic acid to be delivered to a host cell, packaging said nucleic acid in a vehicle capable of entering a host cell and bringing a resulting gene delivery vehicle in a medium suitable for administration to a host.
15. A method according to claim 14, wherein said nucleic acid is based on or derived from an adenovirus.
16. A method according to claim 14 or 15, wherein said vehicle comprises adenoviral structural proteins.
17. A method according to claim 16, wherein at least one vehicle comprises proteins from adenoviruses of different serotypes.
18. A method according to any one of claims 15-17, wherein said nucleic acid comprises at least one ITR and a packaging signal based on or derived from an adenovirus.
19. A method according to any one of claims 15-18, wherein said nucleic acid does not encode functional structural adenoviral proteins.
20. A method according to any one of claims 15-19, wherein said nucleic acid encodes E2A adenoviral gene product.
21. A method according to claim 20, wherein said E2A gene product is temperature sensitive.
22. A method according to any one of claims 14-21, wherein said packaging occurs in a packaging cell.
23. A method according to claim 22 wherein said packaging cell is derived from or based on a primary cell.
24. A method according to claim 23, wherein said cell is based on or derived from PER.C6.
25. A method according to any one of claims 15-18 wherein said nucleic acid comprising said gene of interest is produced by a recombination step from two adenoviral vectors.
26. A method according to any one of claims 15-25, wherein said adenovirus is an adenovirus serotype 5 or serotype 35.

1. Referenceless clock and data recovery circuitry, comprising:
a first timing loop including:
an oscillator to produce a plurality of first clock signals having the same frequency but differing phases in accordance with a frequency control signal;
phase interpolation circuitry to receive the first clock signals and produce an output clock signal based on the first clock signals and a phase control signal;
a transition density detector, coupled to the output clock signal and a data input signal, to produce a transition density signal indicative of the transition density of the data input signal relative to a frequency of the output clock signal;
a frequency comparator coupled to the first clock signal and the output clock signal to produce a frequency comparison signal indicative of the relative frequencies of the first clock signals and the output clock signal; and
a controller to generate the frequency control signal based on the transition density signal and the frequency comparison signal; and
a second timing loop including:
the phase interpolation circuitry;
a phase detector to receive a data input signal and the output clock signal and to produce a phase detection signal; and
a loop filter configured to produce the phase control signal by filtering the phase detection signal.
2. The clock and data recovery device of claim 1, wherein the clock circuitry comprises a multi-modulus divider.
3. The clock and data recovery device of claim 1, wherein the clock circuitry comprises:
a phase interpolator configured to receive the first clock signal and produce a second clock signal based on the phase control signal, where the second clock signal is interpolated from two phases of a plurality of phases of the first clock signal;
a prescaler configured to receive the second clock signal and produce the output clock signal by dividing the second clock signal by a value of a prescaler control signal produced by the controller.
4. The clock and data recovery device of claim 1, wherein the controller is further configured to search for a value of the frequency control signal that results in the measurements meeting lock criteria.
5. The clock and data recovery device of claim 4, wherein the controller is further configured to search by sweeping the frequency control signal through a range of values.
6. The clock and data recovery device of claim 1, further comprising:
a first counter coupled to the output clock signal and configured to produce counts of transitions of the output clock signal;
a second counter coupled to the first clock signal and configured to produce counts of transitions of the first clock signal; and
a third counter coupled to the data input signal and configured to produce counts of transitions of the data input signal, and
wherein the frequency comparison module receives the counts from the first counter and the second counter and transition density detector receives the counts from the first counter and the third counter.
7. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; and
tracking the data input signal, where tracking the data input signal comprises adjusting the circuit settings of a digital clock and data recovery circuit generating the output recovered clock signal to track a frequency of the data input signal and is performed after the searching meets a search criterion.
8. The method of claim 7, further comprising holding the circuit settings of the digital clock and data recovery circuit, where the holding the circuit settings of the digital clock and data recovery circuit is performed after the tracking does not meet a tracking criterion.
9. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the searching comprises
sweeping a setting through a range of values until the measured data transition density meets a criterion, with the measuring the data transition density indicative of transition density of the data input signal relative to the frequency of the output clock signal performed for each value of the setting.
10. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the method is performed by circuitry including a clock and data recovery circuit with a prescaler and a voltage-controlled oscillator having a range control and a frequency control, and wherein the searching for circuit settings that allow locking of the digital clock and data recovery circuit to the data input signal comprises:
sweeping a prescale control through a range of prescale control values;
sweeping a range control through a range of range control values for each value of the prescale control; and
sweeping a frequency control through a range of frequency control values for each value of the range control until the measured data transition density meets a criterion.
11. A method for clock and data recovery without use of an externally supplied reference clock signal, comprising:
measuring a frequency comparison indicative of the relative frequencies of a VCO clock signal and an output recovered clock signal;
measuring a data transition density indicative of transition density of a data input signal relative to the frequency of the output recovered clock signal;
searching for circuit settings that allow locking the output recovered clock signal to the data input signal, where the locking is based on the measured frequency comparison and the measured data transition density; wherein the method is performed by circuitry including a clock and data recovery circuit with a prescaler and a voltage-controlled oscillator having a range control and a frequency control, and wherein the searching for circuit settings that allow locking of the digital clock and data recovery circuit to the data input signal comprises:
sweeping a prescale control through a range of prescale control values;
sweeping a range control through a range of range control values for each value of the prescale control; and
sweeping a frequency control through a range of frequency control values for each value of the range control until the measured data transition density and the measured frequency comparison meet criteria.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A latch circuit comprising:
a sample section activated during a sample period by a sample signal to sample a pair of complementary data signals, to deliver said complementary data signals through a pair of sample output nodes;
a latch section activated during a hold period by a hold signal to latch said complementary data signals through said sample output nodes, to deliver said complementary data signals through a pair of latch output nodes, said sample signal and said hold signal occurring alternately with each other; and
a precharge section for precharging said latch output nodes during said sample period, wherein:
said latch section includes first and second inverters for receiving said complementary data signals through said sample output nodes, and a latch-section activating circuit for activating said first and second inverters during said hold period;
said first inverter includes a first transistor having a gate connected to one of said sample output nodes and connected between a high-potential power source line and one of said latch output nodes, a second transistor connected between said one of said latch output nodes and the other of said sample output nodes and being OFF during said sample period, and a third transistor having a gate connected to the other of said latch output nodes and connected between said other of said sample output nodes and a low-potential power source line; and
said second inverter includes a fourth transistor having a gate connected to said other of said sample output nodes and connected between said high-potential power source line and said other of said latch output nodes, a fifth transistor connected between said other of said latch output nodes and said one of said sample output nodes and being OFF during said sample period, and a sixth transistor having a gate connected to said one of said latch output nodes and connected between said one of said sample output nodes and said low-potential power source line.
2. The latch circuit according to claim 1, wherein said latch-section activating circuit includes a seventh transistor connected between said third transistor and said low-potential power source line and being ON during said hold period, and an eighth transistor connected between said sixth transistor and said low-potential power source line and being ON during said hold period.
3. The latch circuit according to claim 1, wherein said latch-section activating circuit includes a seventh transistor connected between a node connecting said third transistor and said sixth transistor in common and said low-potential power source line and being ON during said hold period.
4. The latch circuit according to claim 1, wherein:
said sample section includes first and second data signal input blocks;
said first data signal input block includes seventh and eighth transistors connected in series between said high-potential power source line and said one of said sample output nodes, said seventh transistor having a gate receiving one of said complementary data signals, said eighth transistor being ON during said sample period, and ninth and tenth transistors connected in series between said low-potential power source line and said one of said sample output nodes, said ninth transistor having a gate receiving the other of said complementary data signals, said tenth transistor being ON during said sample period; and
said second data signal input block includes eleventh and twelfth transistors connected in series between said high-potential power source line and said other of said sample output nodes, said eleventh transistor having a gate receiving said other of said complementary data, signals, said twelfth transistor being ON during said sample period, and thirteenth and fourteenth transistors connected in series between said low-potential power source line and said other of said sample output nodes, said thirteenth transistor having a gate receiving said one of said complementary data signals, said fourteenth transistor being ON during said sample period.
5. The latch circuit according to claim 1, wherein:
said sample section includes first and second data signal input blocks, and a sample-section activating block for activating said first and second data signal input blocks during said sample period;
said first data signal input block includes seventh transistor connected between said high-potential power source line and said one of said sample output nodes and having a gate receiving one of said complementary data signals, and an eighth transistor connected between said low-potential power source line and said one of said sample output nodes and having a gate receiving the other of said complementary data signals; and
said second data signal input block includes ninth transistor connected between said high-potential power source line and said other of said sample output nodes and having a gate receiving said other of said complementary data signals, and a tenth transistor connected between said low-potential power source line and said other of said sample output nodes and having a gate receiving said one of said complementary data signals.
6. The latch circuit according to claim 5, wherein said sample-section activating block includes an eleventh transistor connected in series with said seventh transistor between said high-potential power source line and said one of said sample output nodes and being ON during said sample period, a twelfth transistor connected in series with said eighth transistor between said low-potential power source line and said one of said sample output nodes and being ON during said sample period, a thirteenth transistor connected in series with said ninth transistor between said high-potential power source line and said other of said sample output nodes and being ON during said sample period, and a fourteenth transistor connected in series with said tenth transistor between said low-potential power source line and said other of said sample output nodes and being ON during said sample period.
7. The latch circuit according to claim 5, wherein said sample-section activating block includes an eleventh transistor connected between a node connecting said seventh transistor and said ninth transistor in common and said high-potential power source line and being ON during said sample period, and a twelfth transistor connected between a node connecting said eighth transistor and said tenth transistor in common and said low-potential power source line and being ON during said sample period.