1. A sliding cascode circuit comprising:
a first transistor having a gate, source and drain, with its source coupled to a first voltage supply and its gate adapted to receive an input signal;
a second transistor having a gate, source and drain, with its drain coupled to an output node, and its source coupled to the drain of the first transistor;
a first impedance coupled from the first voltage supply to the gate of the second transistor; and
a second impedance coupled from the gate of the second transistor to the output node;
wherein the first and second impedances have substantially the same value and form a feedback network that distributes voltage at the output node across the first and second transistors, thereby increasing maximum voltage swing of the circuit relative to a single transistor configuration.
2. The circuit of claim 1 further comprising: a third transistor having a gate, source and drain, with its drain coupled to a first bias voltage source, its source coupled to the gate of the second transistor, and its gate adapted to receive control signals that turn the third transistor on and off in order to set a DC operating point of the circuit.
3. The circuit of claim 1 wherein the first and second impedances are capacitors.
4. The circuit of claim 1 wherein the first and second impedances are resistors of substantially the same value.
5. The circuit of claim 2 wherein the first, second, and third transistors are PFETs.
6. An integrator with sliding cascode amplifier circuit, comprising:
a first transistor having a gate, source and drain, with its source coupled to a first voltage supply and its gate adapted to receive an input signal;
a second transistor having a gate, source and drain, with its drain coupled to an output node, and its source coupled to the drain of the first transistor;
a first impedance coupled from the first voltage supply to the gate of the second transistor, wherein said first impedance is a first capacitor;
a second impedance coupled from the gate of the second transistor to the output node, wherein said second impedance is a second capacitor; and
an integration capacitor coupled from the input node to the output node;
wherein the first and second impedances form a feedback network that distributes voltage at the output node across the first and second transistors, thereby increasing maximum voltage swing of the circuit relative to a single transistor configuration.
7. The circuit of claim 6 further comprising:
a cascode reset switch operatively coupled to the circuit and for coupling a reset voltage to the feedback network in response to a cascode reset signal; and
an integration reset switch operatively coupled to the circuit and for enabling an integration reset function in response to an integration reset signal.
8. The circuit of claim 7 further wherein the cascode reset switch is opened before the integration reset switch is opened to begin integration.
9. The circuit of claim 6 wherein the first and second impedances have substantially the same value, thereby enabling voltage at the output node to be evenly distributed across the first and second transistors.
10. The circuit of claim 6 wherein the first and second capacitors are substantially the same value.
11. The circuit of claim 6 further comprising:
a third transistor having a gate, source and drain, with its source coupled to a second voltage supply and its gate adapted to receive an amplifier bias voltage signal;
a fourth transistor having a gate, source and drain, with its drain coupled to the output node, and its source coupled to the drain of the third transistor;
a third impedance coupled from the second voltage supply to the gate of the fourth transistor; and
a fourth impedance coupled from the gate of the fourth transistor to the output node;
wherein the third and fourth impedances form a second feedback network that distributes voltage at the output node across the third and forth transistors, thereby further increasing the maximum voltage swing of the circuit.
12. The circuit of claim 11 further comprising:
a cascode reset switch operatively coupled to the circuit and for coupling a coupling a reset voltage to the second feedback network in response to a cascode reset signal; and
an integration reset switch operatively coupled to the circuit and for enabling an integration reset function in response to an integration reset signal.
13. The circuit of claim 12 further wherein the cascode reset switch is opened before the integration reset switch is opened to begin integration.
14. The circuit of claim 11 wherein the third and fourth impedances have substantially the same value, thereby enabling voltage at the output node to be evenly distributed across the third and fourth transistors.
15. The circuit of claim 11 wherein the third and fourth impedances are capacitors.
16. The circuit of claim 15 wherein the capacitors are substantially the same value.
17. A sliding cascode source follower circuit comprising:
a first transistor having a gate, source and drain, with its source providing an output node and adapted for coupling with a current source, and its gate adapted to receive an input signal;
a second transistor having a gate, source and drain, with its drain coupled to a first voltage supply, and its source coupled to the drain of the first transistor;
a first impedance coupled from the first voltage supply to the gate of the second transistor; and
a second impedance coupled from the gate of the second transistor to the output node;
wherein the first and second impedances form a feedback network that distributes an output voltage at the output node across the first and second transistors wherein said input signal at said gate of said first transistor is substantially similar to said output signal at said source of said first transistor, thereby increasing maximum voltage swing of the circuit relative to a single transistor configuration.
18. A sliding cascode circuit fabricated using a semiconductor process associated with a voltage rating for a single transistor the circuit comprising:
a first transistor having a gate, source and drain, with its source operatively coupled to a first voltage supply and its gate adapted to receive an input signal;
a second transistor having a gate, source and drain, with its drain operatively coupled to an output node, and its source operatively coupled to the drain of the first transistor;
a third transistor having a gate, source and drain, with its drain operatively coupled to a first bias voltage source, its source coupled to the gate of the second transistor, and its gate adapted to receive control signals that turn the third transistor on and off in order to set a DC operating point of the circuit; and
a feedback network operatively coupled to the first, second and third transistors, that distributes voltage at the output node across the first, second and third transistors, thereby increasing maximum voltage swing of the circuit relative to the voltage rating for a single transistor.
19. The circuit of claim 18 wherein the feedback network is configured to enable voltage at the output node to be evenly distributed across the first and second transistors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A display device comprising:
a plurality of pixel circuits, arranged in a matrix, each of which includes a light-emitting element that emits light with a luminance depending on an injected electric current, and a transistor that controls the electric current flowing through the light-emitting element, each of the pixel circuits performing prior to emission of light by the light-emitting element an electric charge accumulating operation in which a voltage between a gate and a source of the transistor is raised to a level higher than a driving threshold voltage of the transistor through accumulation of electric charges to a predetermined capacitor, and each of the pixel circuits performing a voltage detectingsupplying operation in which a voltage corresponding to the driving threshold voltage is detectedsupplied between the gate and the source of the transistor through adjustment of the voltage between the gate and the source; and
a driver circuit that controls at least a timing of detection and supply of a voltage corresponding to electric charge accumulation and the driving threshold voltage in the pixel circuit, wherein
the driver circuit controls so that the electric charge accumulation and the voltage detectionsupply start substantially simultaneously for a pixel circuit in a first row in the matrix and a pixel circuit in a second row in the matrix and adjacent to the pixel circuit in the first row in one direction along a column, and controls so that the electric charge accumulation and the voltage detectionsupply end substantially simultaneously for the pixel circuit in the first row and a pixel circuit in a third row and adjacent to the pixel circuit in the first row in another direction along the column.
2. The display device according to claim 1 wherein
the driver circuit controls so that amounts of time differences in end timings of the electric charge accumulation and the voltage detectionsupply between the pixel circuit in the first row and the pixel circuit in the second row are substantially equal to amounts of time differences in start timings of the electric charge accumulation and the voltage detectionsupply between the pixel circuit in the first row and the pixel circuit in the third row.
3. The display device according to claim 1, wherein
the light-emitting element has a characteristic that the light-emitting element emits light on receiving a supply of voltage in a forward direction which causes electric current in the light-emitting element, and accumulates electric charges corresponding to a level of supplied voltage on receiving a supply of voltage in a backward direction, and functions as the capacitance at the electric charge accumulation and the voltage detectionsupply.
4. The display device according to claim 1, wherein the light-emitting element is an organic light-emitting diode.
5. A method of driving a display device which includes plural pixel circuits, arranged in a matrix, each of which includes a light-emitting element that emits light with a luminance depending on an injected electric current and a transistor that controls the electric current flowing through the light-emitting element, and which is configured to accumulate electric charges to a predetermined capacitor and to employ the accumulated electric charges to detectsupply a voltage corresponding to a driving threshold voltage between a gate and a source of the transistor element prior to emission of light by the light-emitting element, the method comprising:
starting an electric charge accumulation and a voltage detectionsupply substantially simultaneously for the pixel circuit arranged in a first row in the matrix and for the pixel circuit arranged in a second row adjacent to the first row in one direction along a column direction; and
stopping the electric charge accumulation and the voltage detectionsupply substantially simultaneously for the pixel circuit arranged in the first row in the matrix and the pixel circuit arranged in a third row adjacent to the first row in another direction along the column direction.
6. The method according to claim 5, wherein the light-emitting element is an organic light-emitting diode.