Author: claimsbot

1. A microwave resonator for or on a textile machine for attachment to a measuring device for measuring the mass andor moisture content of textile fibre material comprising:
a resonator chamber through which textile fibre material is conveyable continuously, having a housing with wall elements including spaced, opposed first and second wall elements;
an inlet through-opening in said first wall element and an outlet through-opening in said second wall element; and
at least one tubular element coaxially connecting said inlet & out through-openings;

wherein the housing comprises a hollow profile with profile walls of which first and second opposite profile walls of the hollow profile form said first and second wall elements in which said connected through-openings are located.
2. A microwave resonator according to claim 1, in which the interior space defined by the hollow profile is closable by at least one closure element to form a cavity resonator.
3. A microwave resonator according to claim 1, in which the hollow profile is produced by a method comprising one or more techniques selected from the group consisting of non-machining shaping, plastic deformation, extrusion moulding, drawing, rolling and casting.
4. A microwave resonator according to claim 1, in which the hollow profile comprises a metallic material selected from the group consisting of aluminum, aluminum alloys, copper, steel, and iron-nickel steel (Invar).
5. A microwave resonator according to claim 1, in which the hollow profile is monolithic.
6. A microwave resonator according to claim 1, in which the hollow profile has at least one subsequently machined, joining seam.
7. A microwave resonator according to claim 1, in which the hollow profile is a tubular member having a cross-section configuration adapted circumferentially to enclose a resonator cavity.
8. A microwave resonator according to claim 7, in which the enclosed cavity is of rectangular or oval cross-section and the longer sides of the rectangle or oval run perpendicular to the axis of the tubular element and to the conveying direction of the textile fibre material, the shorter sides of the rectangle or oval running parallel to the axis of the tubular element and to the conveying direction of the textile fibre material.
9. A microwave resonator according to claim 8, in which the ratio of height to depth in the chamber of the resonator is about 1:6 to 10, the chamber having a height of about 110 to 130 mm and a depth of about 12 to 18 mm.
10. A microwave resonator according to claim 1, in which the resonator chamber is enclosed on all sides.
11. A microwave resonator according to claim 1, in which the resonator chamber is enclosed by an electrically conducting layer or wall.
12. A microwave resonator according to claim 1, in which the inner wall areas of the hollow profile are provided with an electrically conducting layer andor are coated for protection against oxidation.
13. A microwave resonator according to claim 1, in which the tubular element shuts off regions of the resonator chamber and is adapted to guide the textile fibre material through the resonator chamber.
14. A microwave resonator according to claim 1, further including a reference resonator in which a said tubular element is, in use, free from textile fibre material.
15. A microwave resonator according to claim 1, in which the tubular element comprises glass or quartz glass.
16. A microwave resonator according to claim 1, in which at least one end of the tubular element is provided with an outwardly flared member, forming respectively, an inlet funnel element that is flared outwardly to form an inlet funnel portion that converges in the direction of travel of the fibre material andor an outlet funnel element that is flared outwardly to form an outlet funnel portion that diverges in the direction of travel of the fibre material.
17. A microwave resonator according to claim 16, in which the inlet funnel element andor outlet funnel element are arranged outside the resonator chamber or in the region of the outer walls of the hollow profile.
18. A microwave resonator according to claim 16, in which the tubular element and the inlet funnel element andor outlet funnel element comprise the same material and are formed in one piece.
19. A microwave resonator according to claim 16, in which the tubular element and the inlet funnel element andor outlet funnel element are formed in at least two pieces.
20. A microwave resonator according to claim 16, in which there can be used alternative tubular elements with different internal diameters.
21. A microwave resonator according to claim 1, further having a reference resonator, the reference resonator and the measuring resonator being accommodated in a common, closed housing and for, temperature equalization, being continuously flushed with air.
22. A microwave resonator according to claim 21, in which the measuring resonator on the one hand and the reference resonator on the other hand are two independently separate components.
23. A microwave resonator according to claim 21, in which the measuring resonator and the reference resonator are a one-piece component, in which a partition wall is arranged.
24. A microwave resonator according to claim 1, in which the measuring resonator is a multi-cell cavity resonator, in which the multi-cell cavity has a number of pairs of through-openings connected by a tubular element corresponding to the number of cells.
25. A microwave resonator according to claim 1, in which two strands of fibres are conveyable side by side through each through-opening and through each tubular element.
26. A microwave resonator according to claim 1, in which the microwave measuring arrangement is used for control andor regulation of a processing device for at least one textile fibre sliver.
27. A microwave resonator according to claim 26, in which the microwave measuring arrangement is connected to an electronic control and regulating device to which there is further connected an actuating device for a variable speed device motor adapted to alter the thickness of a fibre silver.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory array comprising:
a semiconductor substrate;
an array of vertical transistors defined by a first set of trenches and a second set of trenches that is substantially orthogonal to the first set of trenches, each vertical transistor comprising a vertically extending pillar comprising a drain region and a body region of a respective vertical transistor of the array of vertical transistors, the first set of trenches extending a different depth into the semiconductor substrate than the second set of trenches;
a plurality of wordlines formed within at least a portion of the first set of trenches and between adjacent vertical transistors of the array of vertical transistors; and
a plurality of digit lines formed within at least a portion of the second set of trenches.
2. The memory array of claim 1, wherein the first set of trenches is etched into the semiconductor substrate and the second set of trenches is etched into the semiconductor substrate.
3. The memory array of claim 1, further comprising a plurality of body lines formed within at least a portion of the first set of trenches, the wordlines and the body lines being alternatingly disposed within the array of vertical transistors.
4. The memory array of claim 1, wherein the second set of trenches extends to a greater depth in the semiconductor substrate than the first set of trenches.
5. The memory array of claim 1, wherein the second set of trenches extends approximately twice as deep into the substrate as the first set of trenches.
6. The memory array of claim 1, further comprising storage capacitors electrically coupled to the drain region of each vertical transistor of the array of vertical transistors.
7. The memory array of claim 1, wherein the vertical transistors are field effect transistors.
8. An integrated circuit comprising:
a semiconductor substrate; and
a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar disposed between a first set of trenches etched into the semiconductor substrate and a second set of trenches etched into the semiconductor substrate, wherein trenches of the second set of trenches are etched into the semiconductor substrate to a greater depth than trenches of the first set of trenches.
9. The integrated circuit of claim 8, wherein the semiconductor pillar is a silicon pillar.
10. The integrated circuit of claim 8, wherein the trenches of the second set of trenches are etched into the semiconductor substrate approximately twice as deep as the trenches of the first set of trenches.
11. The integrated circuit of claim 8, further comprising an active area of a vertical transistor, the active area being disposed in a trench of the second set of trenches.
12. The integrated circuit of claim 11, further comprising an insulating material filling the trenches of the first set of trenches to approximately the height of the active area.
13. The integrated circuit of claim 12, further comprising a gate dielectric of the vertical transistor, the gate dielectric being disposed on the semiconductor pillar.
14. The integrated circuit of claim 13, further comprising a wordline formed at least partially within a trench of the second set of trenches, the wordline being disposed around the semiconductor pillar and electrically connecting a row of vertical transistors in a memory array.
15. The integrated circuit of claim 8, wherein the semiconductor substrate is a silicon on insulator substrate.
16. The integrated circuit of claim 8, wherein the semiconductor substrate is a bulk silicon substrate.
17. The integrated circuit of claim 8, further comprising a bit line formed within of at least a portion of the second set of trenches.
18. A method of forming an array of silicon pillars, the method comprising:
etching a first group of substantially parallel lines to a first depth in a silicon substrate; and
while etching a second group of substantially parallel lines to a second depth in the silicon substrate, further etching the first group of substantially parallel lines to a third depth that is greater than the first depth and greater than the second depth, wherein the second group of substantially parallel lines crosses the first group of substantially parallel lines, and wherein regions of the silicon substrate between the first group of substantially parallel lines and the second group of substantially parallel lines form an array of silicon pillars.
19. The method of claim 18, wherein the third depth is approximately equal to a sum of the first depth and the second depth.
20. The method of claim 18, further comprising forming bitlines within at least a portion of the etched second group of substantially parallel lines.
21. The method of claim 18, further comprising forming a sourcedrain region associated with each silicon pillar in the array of silicon pillars.
22. The method of claim 18, further comprising forming alternating body lines and wordlines in the first group of substantially parallel lines after etching the first group of substantially parallel lines to the third depth.

1. An automatic focusing method comprising:
determining a manner for auto focusing among at least an electromyogram signal manner and an ultrasonic image manner, wherein the electromyogram signal manner comprises a manner for calculating a distance to an object based on an electromyogram signal generated from an eyeball and the ultrasonic image manner comprises a manner for calculating a distance to an object based on at least one ultrasonic image of the eyeball;
calculating a distance from an eyeball of a user to an object at which the eyeball of the user looks according to the determined manner; and
adjusting, based on the calculated distance, a plane of focus including the object.
2. The automatic focusing method of claim 1, wherein calculating the distance comprises:
detecting the electromyogram signal generated from the eyeball; and
generating distance data based on the electromyogram signal.
3. The automatic focusing method of claim 1, wherein calculating the distance comprises:
collecting the ultrasonic images generated by ultrasonic imaging of the eyeball;
identifying a crystalline lens of the eyeball based on the ultrasonic images;
generating oblateness data by recognizing oblateness of the crystalline lens; and
generating distance data based on the oblateness data.
4. The automatic focusing method of claim 1, further comprising:
priorly providing an image including the plane of focus to the user.
5. The automatic focusing method of claim 4, wherein priorly providing the image including the plane of focus to the user comprises:
converting the image based on the plane of focus and a preset depth of field; and
providing the converted image to the user.
6. The automatic focusing method of claim 1, further comprising:
receiving a user input for automatic focusing.
7. The automatic focusing method of claim 6, wherein receiving the user input comprises:
detecting that the eyeball approaches a viewfinder.
8. The automatic focusing method of claim 6, wherein:
determining the manner for auto focusing comprises determining that the manner is the electromyogram signal manner,
wherein calculating the distance comprises detecting the electromyogram signal and generating distance data based on the electromyogram signal.
9. The automatic focusing method of claim 8, wherein:
determining the manner for auto focusing comprises determining that the manner is the ultrasonic image manner; and
calculating the distance comprises:
collecting the ultrasonic images by ultrasonic imaging of the eyeball;
identifying the crystalline lens included in the eyeball based on the ultrasonic images;
generating oblateness data by recognizing oblateness of the crystalline lens; and
generating distance data based on the oblateness data.
10. An automatic focusing apparatus comprising:
an eyeball measurement unit configured to detect a change generated in an eyeball of a user; and
a controller configured to:
determine a manner for auto focusing among at least electromyogram signal manner and ultrasonic image manner, wherein the electromyogram signal manner comprises a manner for calculating a distance to an object based on an electromyogram signal generated from an eyeball and the ultrasonic image manner comprises a manner for calculating a distance to an object based on at least one ultrasonic image of the eyeball;
calculate a distance from the eyeball of the user to an object at which the eyeball of the user looks according to the determined manner, and
adjust, based on the calculated distance, a plane of focus including the object.
11. The automatic focusing apparatus of claim 10, wherein the eyeball measurement unit comprises an electromyogram sensor configured to detect the electromyogram signal generated from the eyeball, and the controller is configured to generate the distance data based on the electromyogram signal.
12. The automatic focusing apparatus of claim 10, wherein the eyeball measurement unit comprises an ultrasonographic sensor configured to perform ultrasonic imaging of the eyeball and collect the ultrasonic images generated by ultrasonic imaging of the eyeball, and the controller is configured to identify a crystalline lens of the eyeball based on the ultrasonic images, generates oblateness data by recognizing oblateness of the crystalline lens, and generate distance data based on the oblateness data.
13. The automatic focusing apparatus of claim 10, further comprising:
a display unit configured to priorly provide an image including the plane of focus.
14. The automatic focusing apparatus of claim 13, wherein the controller is configured to convert the image based on the plane of focus and a preset depth of field and to control the display unit to provide the converted image to the user.
15. The automatic focusing apparatus of claim 14, wherein the display unit comprises a viewfinder, and the controller is configured to determine that a user input for automatic focusing is input when it is detected that the eyeball approaches the viewfinder.
16. The automatic focusing apparatus of claim 15, wherein the controller is configured to determine that the manner for auto focusing is the electromyogram signal manner and control an electromyogram sensor that is included in the eyeball measurement unit to detect an electromyogram signal generated from the eyeball.
17. The automatic focusing apparatus of claim 16, wherein the controller is configured to determine that the manner for auto focusing is the ultrasonic image manner, and collect the ultrasonic images generated by ultrasonic imaging of the eyeball by using an ultrasonographic sensor included in the eyeball measurement unit.
18. The automatic focusing apparatus of claim 10, wherein the controller is configured to detect a user input for automatic focusing before generating the distance data.
19. The automatic focusing apparatus of claim 10, wherein the controller is configured to provide automatic focusing for an electronic device including a camera.
20. The automatic focusing method of claim 1, further comprising providing automatic focusing for an electronic device including a camera.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory device, comprising:
a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells is replaced with a dummy memory cell from among the second plurality of dummy memory cells.
2. The device of claim 1, wherein the second plurality of dummy memory cells comprise:
a second plurality of drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
a second plurality of source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
3. The device of claim 2, wherein each of the at least one bad memory cell is replaced with a source dummy memory cell.
4. The device of claim 2, wherein each of the at least one bad memory cell is replaced with a source dummy memory cell adjacent to the first plurality of normal memory cells.
5. The device of claim 1, further comprising a peripheral circuit configured to control the operation of the first plurality of normal word lines and the second plurality of dummy word lines.
6. The device of claim 5, wherein, when a program operation is performed, the peripheral circuit is configured to apply a voltage to a normal word line that are electrically coupled to the at least one bad memory cell that is substantially the same as the voltage applied to a non-selected normal word line from among the first plurality of normal word lines.
7. The device of claim 5, wherein, when a read operation is performed, the peripheral circuit is configured to apply a voltage to a normal word line that are electrically coupled to the at least one bad memory cell that is substantially the same as the voltage applied to a non-selected normal word line from among the first plurality of normal word lines.
8. The device of claim 5, wherein, when an erase operation is performed, the peripheral circuit is configured to apply a ground voltage to a normal word line that are electrically coupled to the at least one bad memory cell.
9. A semiconductor memory device, comprising:
a plurality of cell strings electrically coupled to a plurality of drain select lines, respectively, the plurality of drain select lines extending in a row direction and arranged in a column direction, each of the plurality of cell strings including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cell is replaced with a dummy memory cell from among the second plurality of dummy memory cells.
10. The device of claim 9, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of the first cell string, and
a second bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of a second cell string from among the plurality of cell strings.
11. The device of claim 9, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of a second cell string from among the plurality of cell strings, and
a second bad memory cell among the at least one bad memory cell is replaced with a dummy memory cell of a third cell string from among the plurality of cell strings.
12. The device of claim 9, wherein the second plurality of dummy memory cells of each of the plurality of cell strings include:
a second plurality of drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
a second plurality of source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
13. The device of claim 12, wherein a source dummy memory cell adjacent to the first plurality of normal memory cells from among the source dummy memory cells of each cell string is provided as a spare cell for replacing the at least one bad memory cell.
14. The device of claim 12, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with the spare cell of the first cell string, and
a second bad memory cell from among the at least one bad memory cell is replaced with the spare cell of a second cell string from among the plurality of cell strings.
15. The device of claim 12, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with the spare cell of a second cell string from among the plurality of cell strings, and
a second bad memory cell among the at least one bad memory cell is replaced with the spare cell of a third cell string from among the plurality of cell strings.
16. A memory system, comprising:
a semiconductor memory device; and
a controller configured to control at least one operation of the semiconductor memory device,
wherein the semiconductor memory device comprises:
a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are replaced with a dummy memory cell from among the second plurality of dummy memory cells.
17. The system of claim 16, wherein the second plurality of dummy memory cells comprise:
drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
18. The system of claim 17, wherein each of the at least one bad memory cells is replaced with a source dummy memory cell.
19. The system of claim 17, wherein each of the at least one bad memory cells is replaced with a source dummy memory cell adjacent to the first plurality of normal memory cells.
20. The system of claim 16, wherein the controller is configured to convert a logical address received from an external device into a physical address that indicates a dummy memory cell from among the plurality of dummy memory cells.