1. A reduced performance circuit salvage method comprising:
preparing a chip for testing;
testing said chip; and
performing a functional component configuration process on said chip and based upon results of said testing configuring said chip as a reduced performance circuit, wherein tasks are performed at a different performance level in said chip configured as said reduced performance circuit and said chip still be classified as a useful chip, and wherein said functional component configuration process comprises:
receiving art indication of a defective functional component;
determining if said defective functional component is one of a plurality of similar functional components;
disabling said defective functional component if it is one of said plurality of similar functional components;
enabling one or more non-defective functional components; and
providing notification of said disabling and said enabling to a second component other than said defective functional component, wherein said second component is configured to communicate information to at least one of said plurality of similar functional components and bypass said defective functional component to which said second component would otherwise communicate information.
2. The reduced performance circuit salvage method of claim 1 wherein said testing comprises:
identifying a defective functional component;
determining if there is a non-defective functional component included in said integrated circuit, wherein said non-defective functional component performs a similar function as said defective functional component;
designating said defective functional component for non use if said non-defective component is included in said integrated circuit; and
marking said integrated circuit as defective if said non-defective component that perform said similar function in not is included in said integrated circuit.
3. The reduced performance circuit salvage method of claim 1 wherein one of a plurality of homogenous execution components of said chip is disabled or enabled and said disabling said defective functional component results in said chip performing said tasks slower.
4. The reduced performance circuit salvage method of claim 1 further comprising reconfiguring said chip to permit other functional components to perform functions of said disabled functional component at said different performance level, wherein said different performance level corresponds to the number of enabled said non-defective functional components.
5. The reduced performance circuit salvage method of claim 1 wherein said indication of a defective functional component is received from a testing system.
6. A die classification process comprising:
fabricating a plurality of die with similar configurations;
preventing a component from participating in productive contribution within one of said plurality of die without eliminating the ability of said one of said plurality of die to perform a function associated with said component and
classifying said plurality of die in classes based on differentiated performance levels for said functionality, wherein die in said classes are considered useful wherein a first die and a second die included in said plurality of die are included in different products that are sold at different prices in correlation to a performance level at which functionality is provided, and wherein a determination of which manufacturer data sheet information applies to a die included in said plurality of die is not made until after testing is performed.
7. The die classification process of claim 6 wherein said plurality of die are fabricated on a single wafer.
8. The die classification process of claim 6 wherein similar configuration is determined by reviewing manufacturer data sheet information on said plurality of die.
9. The die classification process of claim 6 wherein similar configuration is determined if dies have substantially the same fabrication costs.
10. The die classification process of claim 6 wherein said component is prevented from participating in productive contribution by disabling said component.
11. The die classification process of claim 6 wherein each one of said plurality of dies are fabricated with the same design and are distributed with different performance levels.
12. A die classification process comprising:
fabricating a plurality of die with similar configurations, wherein similar configuration is determined if dies have substantially the same fabrication costs;
preventing a component from participating in productive contribution within one of said plurality of die without eliminating the ability of said one of said plurality of die to perform a function associated with said component; and
classifying said plurality of die based on differentiated performance levels for said functionality, wherein a first die and a second die included in said plurality of die are included in different products that are sold at different prices in correlation to a performance level at witch functionality is provided.
13. The die classification process of claim 12 wherein said component is prevented from participating in productive contribution by disabling said component.
14. The die classification process of claim 12 wherein a determination of which data sheet information applies to a die included in said plurality of die is not made until after testing is performed.
15. The die classification process of claim 12 wherein each one of said plurality of dies are fabricated with the same design and are distributed with different performance levels.
16. The die classification process of claim 12 wherein said one of said plurality of die is reconfigured to permit other functional components to perform functions of said disabled functional component.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
(a) a plurality of cuboidal battery cells;
(b) a cooling system comprising a thermally conductive plate with channels for cooling fluid;
(c) a battery housing comprising:
(1) a first plurality of walls;
(2) a second plurality of walls,
wherein the second plurality of walls meets the first plurality of walls to form a housing comprising a grid with a first side located opposite to a second side, said grid outlining cuboidal spaces within, the housing further comprising a third side, a fourth side, a fifth side, and a sixth side,
wherein the third side, the fourth side, the fifth side, and the sixth side form a border around the grid with the third side opposite the fifth side and the fourth side opposite the sixth side;
(3) a plurality of channels formed by the first plurality of walls and the second plurality of walls,
wherein the plurality of channels extends through the housing from the first side to the second side, the plurality of channels has a first plurality of openings on the first side, the plurality of channels has a second plurality of openings on the second side,
(4) a first plurality of open chambers set on the outside face of the second side, wherein each open chamber is separated from an adjacent open chamber by the second plurality of walls and bordered by a first border in plane with the first side and a second border in plane with the second side, a third border in plane with the third side and a fourth border in plane with the fifth side: and
(5) a second plurality of open chambers set on the outside face of the fourth side, wherein each open chamber is separated from an adjacent open chamber by the second plurality of walls and bordered by a fifth border in plane with the first side and a sixth border in plane with the second side, a seventh border in plane with the third side and an eighth border in plane with the fifth side,
wherein each one of the plurality of batteries is located within one of the plurality of channels,
the plurality of batteries are positioned so that each bottom of each battery of said plurality of batteries is in-plane with the second side of the battery housing and each said battery is directly in contact with the thermally conductive plate,
and the battery housing covers only a portion of each side of each said battery.
2. The apparatus of claim 1 further comprising:
a securing mechanism configured to secure the plurality of battery cells within the plurality of channels.
3. The apparatus of claim 2, wherein the securing mechanism comprises an adhesive configured to attach the plurality of battery cells to the first plurality of walls and the second plurality of walls.
4. The apparatus of claim 3, wherein the adhesive is selected from one of a group comprising a thermal plastic material, polyvinyl acetate, an epoxy material, polyurethane, and a cyanoacrylate polymer.
5. The apparatus of claim 2, wherein the plurality of battery cells are electrically connected to each other.
6. The apparatus of claim 1, wherein at least a portion of the plurality of battery cells is located within the plurality of channels.
7. The apparatus of claim 1, wherein the first plurality of walls and the second plurality of walls are comprised of a material that is configured to conduct heat.
8. The apparatus of claim 1, wherein at least some of the first plurality of chambers are provided with corresponding holes in second border.
9. The apparatus of claim 1, wherein at least some of the second plurality of chambers are provided with corresponding holes in the second border.
10. The apparatus of claim 1, wherein at least some of the first plurality of chambers and the second plurality of chambers are provided with corresponding holes in the second border.
11. The apparatus of claim 1, wherein the first plurality of walls and the second plurality of walls are spaced such that the plurality of channels has about equal dimensions.