Author: claimsbot

1. An image forming apparatus comprising:
a developing device which develops an electrostatic image on an image bearing member with a developer including toner and carrier;
a movable member which supports said developing device and is movable between a developing position at which said movable member is opposed to said image bearing member and a non-developing position at which said movable member is not opposed said image bearing member;
a replenishment device which feeds a developer for replenishment to said developing device;
a developer replenishment path which is supported by said movable member and allows the developer for replenishment to be fed from said replenishment device to said developing device; and
a conveyance screw arranged within the developer replenishment path so as not to come into contact with an internal wall of the developer replenishment path,
wherein X (g) representing a quantity of the developer for replenishment present in a clearance section between said developer replenishment path and said conveyance screw,
Y (g) representing a quantity of the developer in said developing device,
Q(\u03bcCmg) representing an absolute value of a electric charge per unit weight of toner in said developing device, and
A(\u03bcCmg) representing an absolute value of an electric charge per unit weight of the toner relative to a 1% variation in the toner density,
X (g), Y (g), Q(\u03bcCmg) and A(\u03bcCmg) satisfies a relationship of X\u2266(Y\xd7Q)(500\xd7A).
2. An image forming apparatus according to claim 1, wherein said developing device includes five or more developing devices,
wherein each of the five or more developing devices accommodates a developer of a different color from others,
the five or more developing devices include at least four color developing devices of a developing device containing yellow developer, a developing device containing magenta developer, a developing device containing cyan developer and a developing device containing black developer, and
the relationship is satisfied in the other developing device beside the four color developing devices.
3. An image forming apparatus according to claim 2, wherein said movable member is a member, and
wherein the five or more developing devices are provided on said movable member so that said five or more developing devices are moved to the developing position in turn.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data reception device for receiving a data packet containing a plurality of packets, wherein
first time information regarding time at which the plurality of packets are generated is added to each of the plurality of packets, the data reception device comprising:
a receive data buffer unit for storing the plurality of packets contained in the data packet;
a receive data amount measuring unit for measuring a data amount stored in the receive data buffer unit;
a variable clock generation unit for generating a clock whose frequency is variable;
a time information output unit for outputting second time information counted in accordance with a frequency of the clock generated by the variable clock generation unit; and
a first time information comparison unit for comparing the first time information added to the plurality of packets with the second time information outputted from the time information output unit and for controlling timing of outputting the plurality of the packets stored in the receive data buffer unit, wherein
the receive data amount measuring unit controls a frequency of the clock generated by the variable clock generation unit in accordance with values measured by the receive data amount measuring unit.
2. The data reception device according to claim 1, wherein the second time information outputted by the time information comparison unit is delayed by a predetermined offset time.
3. The data reception device according to claim 2, wherein the time information output unit comprises:
a timer unit for outputting third time information counted in accordance with a frequency of the clock generated by the variable clock generation unit;
a time information extraction unit for extracting the first time information added to the plurality of packets stored in the receive data buffer unit;
an initialization unit for coinciding the third time information outputted by the timer unit with the first time information extracted by the time information extraction unit; and
an offset unit for outputting the second time information by delaying, by the predetermined offset time, the third time information outputted by the timer unit.
4. The data reception device according to claim 3, wherein the offset unit changes the predetermined offset time in accordance with conditions of a transmission line where the data reception device is connected.
5. The data reception device according to claim 3, wherein the offset unit changes the predetermined offset time in accordance with a data amount accumulated in the receive data buffer unit.
6. The data reception device according to claim 3, wherein the offset unit changes the predetermined offset time in accordance with a kind of a communication protocol.
7. The data reception device according to claim 3, comprising a second time information comparison unit for comparing the third time information outputted by the timer unit with the first time information extracted by the time information extraction unit and for controlling, based on a comparison result, a frequency of the clock generated by the variable clock generation unit.
8. The data reception device according to claim 7, wherein until a predetermined time from a time point of starting reception of the data packet has passed, a frequency of the clock generated by the variable clock generation unit is controlled by the second time information comparison unit, and
after the predetermined time from the time point of starting reception of the data packet has passed, the frequency of the clock generated by the variable clock generation unit is controlled by the receive data amount measuring unit.
9. The data reception device according to claim 3, wherein after a predetermined time has passed, the receive data amount measuring unit starts controlling a frequency of the clock generated by the variable clock generation unit after predetermined time has passed.
10. The data reception device according to claim 1, wherein the receive data amount measuring unit controls the frequency of the clock generated by the variable clock generation unit by using an average value, as a measured value, of data amounts accumulated in the receive data buffer unit.
11. The data reception device according to claim 1, wherein the plurality of packets contained in the data packet are MPEG2-TS packets.
12. The data reception device according to claim 1, wherein as the data packet, audio signals and video signals are encoded to be generated as a plurality of MPEG2-TS packets to each of which first time information regarding time at encoding time is added, and the plurality of MPEG2-TS packets having the added first time information are combined and transmitted from the data transmission device which is operable to generate the data packet.
13. An integrated circuit for receiving a data packet containing a plurality of packets, wherein
first time information regarding time at which the plurality of packets are generated is added to each of the plurality of packets, the integrated circuit comprising:
a receive data amount measuring unit for measuring a data amount stored in a receive data buffer unit, which is connected to the integrated circuit, for storing the plurality of packets contained in the data packet;
a variable clock generation unit for generating a clock whose frequency is variable;
a time information output unit for outputting second time information counted in accordance with a frequency of the clock generated by the variable clock generation unit; and
a first time information comparison unit for comparing the first time information added to the plurality of packets with the second time information outputted by the time information output unit and for controlling timing of outputting the plurality of packets stored in the receive data buffer unit, wherein
the receive data amount measuring unit controls a frequency of the clock generated by the variable clock generation unit in accordance with values measured by the receive data amount measuring unit.

1. In a system for receiving a composite information modulated carrier signal comprising a main signal modulated carrier component which travels a direct path to said receiving system and a multipath signal modulated carrier component which travels a reflected path to said receiving system, including a demodulator chain having adaptive circuitry controllable in response to a control signal to compensate for the multipath component, a control signal generator, comprising:
a phase error estimator, for generating a phase error signal representing an estimate of the phase error between the information modulated composite carrier signal and the main signal modulated carrier component; and
a controller, responsive to the phase error signal ,for generating said control signal wherein said controller comprises:
a frequency analysis circuit responsive to said phase error signal for generating frequency components representing the magnitudes of the phase error signal at each of a plurality of respective frequencies;
an analysis circuit for comparing frequency components of said phase error signal to threshold values; and
a control circuit responsive to said comparison for generating said control signal.
2. The system of claim 1 wherein said phase error estimator comprises:
a phase error estimator for generating a phase error signal representing an estimate of the phase error between the composite signal and the main component resulting from presence of said multipath component.
3. The system of claim 2 wherein the frequency analysis circuit comprises a discrete Fourier transform circuit.
4. The system of claim 3 wherein the discrete Fourier transform circuit comprises a fast Fourier transform circuit.
5. In a system for receiving a composite signal including a main component and a multipath component, including a demodulator chain having adaptive circuitry controllable in response to a control signal to compensate for the multipath component, a control signal generator, comprising:
a phase error estimator, for generating a signal representing an estimate of the phase error between the composite signal and the main component; and
a controller, responsive to the phase error signal ,for generating said control signal wherein said controller comprises:
a frequency analysis circuit responsive to said phase error signal for determining frequency components of the phase error signal;
an analysis circuit for comparing frequency components of said phase error signal to threshold values; and
a control circuit responsive to said comparison for generating said control signal;
wherein the frequency analysis circuit comprises a discrete Fourier transform circuit; and
wherein the frequency analysis circuit further comprises a decimator, responsive to the phase error signal, and coupled to the discrete Fourier transform circuit.
6. The system of claim 5 wherein the frequency analysis circuit further comprises a magnitude determining circuit, responsive to the discrete Fourier transform circuit.
7. The system of claim 5 wherein the frequency analysis circuit further comprises a magnitude-squared determining circuit, responsive to the discrete Fourier transform circuit.
8. The system of claim 5 wherein the analysis circuit comprises circuitry for comparing the magnitudes of respective frequency components from the discrete Fourier transform circuit to corresponding threshold values.
9. In a system for receiving a composite signal including a main component and a multipath component, including a demodulator chain having adaptive circuitry controllable in response to a control signal to compensate for the multipath component, a control signal generator, comprising:
a phase error estimator, for generating a signal representing an estimate of the phase error between the composite signal and the main component; and
a controller, responsive to the phase error signal ,for generating said control signal wherein said controller comprises:
a frequency analysis circuit responsive to said phase error signal for determining frequency components of the phase error signal;
an analysis circuit for comparing frequency components of said phase error signal to threshold values; and
a control circuit responsive to said comparison for generating said control signal;
wherein the frequency analysis circuit comprises a discrete Fourier transform circuit;
wherein the analysis circuit comprises circuitry for comparing the magnitudes of respective frequency components from the discrete Fourier transform circuit to corresponding threshold values; and
wherein the threshold values depend on the current state of the adaptive circuitry.
10. The system of claim 8 wherein the analysis circuit comprises circuitry for comparing a function of one or more of the magnitudes of respective frequency components from the discrete Fourier transform circuit to corresponding threshold values.
11. The system of claim 10 wherein the threshold values depend on the current state of the adaptive circuitry.
12. The system of claim 5 wherein the analysis circuit comprises circuitry for comparing the magnitudes-squared of respective frequency components from the discrete Fourier transform circuit to corresponding threshold values.
13. The system of claim 12 wherein the threshold values depend on the current state of the adaptive circuitry.
14. The system of claim 12 wherein the analysis circuit comprises circuitry for comparing a function of one or more of the magnitudes of respective frequency components from the discrete Fourier transform circuit to corresponding threshold values.
15. The system of claim 14 wherein the threshold values depend on the current state of the adaptive circuitry.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A flame resistant LED construction comprising:
a substrate;
one or more LEDs that emit light mounted on the substrate; and
an intumescent material adjacent to the LEDs such that at least a portion of the light emitted from the LED is unobstructed, wherein a sufficient amount of the intumescent material is in proximity to the LED that a flame on the LED is extinguished by the expansion of the intumescent material.
2. The flame resistant LED of claim 1 wherein the substrate is a circuit board.
3. The flame resistant LED of claim 1 wherein the intumescent material comprises one or more sheets of intumescent material.
4. The flame resistant LED of claim 3 wherein the one or more sheets of intumescent material define one or more openings, the one or more openings adapted to receive the one or more LEDs.
5. The flame resistant LED of claim 1 wherein the one or more LEDs are a plurality of LEDs arranged in one or more rows.
6. The flame resistant LED of claim 5 wherein the intumescent material comprises two or more sheets of intumescent material, wherein a sheet of intumescent material is positioned on each side of the one or more rows.
7. The flame resistant LED of claim 1 wherein the intumescent material is adhered to the substrate.
8. The flame resistant LED of claim 1 wherein the intumescent material expands at a temperature greater than or equal to about 250\xb0 F. and forms an insulating char which at least partially encompasses the one or more LEDs.
9. The flame resistant LED of claim 1 wherein the intumescent material expands at a temperature greater than or equal to about 275\xb0 F. and forms an insulating char which at least partially encompasses the one or more LEDs.
10. The flame resistant LED of claim 1 wherein the intumescent material expands at a temperature greater than or equal to about 300\xb0 F. and forms an insulating char which at least partially encompasses the one or more LEDs.
11. The flame resistant LED of claim 1 wherein the LED has a top which is located at a first distance from the substrate and the intumescent material is in the form of a sheet having a thickness which is less than the first distance.
12. A flame resistant LED construction comprising:
a substrate;
one or more LEDs that emit light mounted on the substrate;
an intumescent material adjacent to the LED such that at least a portion of the light emitted from the LED is unobstructed, wherein a sufficient amount of the intumescent material is in proximity to the LED that when the intumescent attains a temperature greater than or equal to about 250\xb0 F. the intumescent material expands and forms an insulating char which at least partially encompasses the one or more LEDs.
13. The flame resistant LED of claim 12 wherein a sufficient amount of the intumescent material is in proximity to the LED that when the LED attains a temperature greater than or equal to about 275\xb0 F. the intumescent material expands and forms an insulating char which at least partially encompasses the one or more LEDs.
14. The flame resistant LED of claim 12 wherein a sufficient amount of the intumescent material is in proximity to the LED that when the intumescent material attains a temperature greater than or equal to about 300\xb0 F. the intumescent material expands and forms an insulating char which at least partially encompasses the one or more LEDs.
15. The flame resistant LED of claim 12 wherein the intumescent material comprises one or more sheets of intumescent material.
16. The flame resistant LED of claim 15 wherein the one or more sheets of intumescent material define one or more openings, the one or more openings adapt to receive the one or more LEDs.
17. The flame resistant LED of claim 12 wherein the one or more LEDs are a plurality of LEDs arranged in one or more rows.
18. The flame resistant LED of claim 17 wherein the intumescent material comprises two or more sheets of intumescent material, wherein a sheet of intumescent material is positioned on each side of the one or more rows.
19. A method of making a flame resistant LED construction comprising:
adapting one or more sheets of intumescent material to receive a predetermined pattern of one or more LEDs that are mounted on a substrate;
placing the one or more sheets of intumescent material on the substrate onto which the one or more LED’s are mounted;
wherein a sufficient amount of the intumescent material is in proximity to the LED that when the intumescent material in proximity to the LED attains a temperature greater than or equal to about 250\xb0 F. the intumescent material expands and forms an insulating char which at least partially encompasses the one or more LEDs.
20. The method of claim 19 wherein the sheet of intumescent material is adapted to receive a predetermined pattern of one or more LEDs by punching holes in a matching pattern in the sheet of intumescent material.
21. The method of claim 19 wherein the predetermined pattern of one or more LEDs mounted on the substrate comprise one or more rows of LEDs and the one or more sheets of intumescent material is adapted to receive the predetermined pattern by forming strips of the intumescent material to be placed on either side of the one or more rows of LEDs.