Author: claimsbot

1. A plastic resin composition comprising a titanium dioxide pigment comprising titanium dioxide particles and a dense hydrous silica coating formed on the surface of the titanium dioxide particles and an organic compound coating formed on the dense hydrous silica coating without any interlayers; and
a LDPE resin.
2. A plastic resin composition according to claim 1, wherein the organic compound is at least one selected from the group consisting of polyols, organosilicon compounds, alkanolamines and derivatives thereof, lauric acid and metal salts thereof, oleic acid and metal salts thereof, paraffin wax and derivatives thereof and polyethylene wax and derivatives thereof.
3. A plastic resin composition according to claim 1, wherein the organic compound is a polyol andor an organosilicon compound.
4. A plastic resin composition according to claim 1, wherein the organic compound is at least one selected from the group consisting of trimethylolpropane, trimethylolethane, alkylsilanes of 4-10 carbon atoms and hydrolyzates thereof and dimethylpolysiloxane.
5. A plastic resin composition according to claim 1, wherein the coating amount of the dense hydrous silica is in the range of 0.5-6% by weight in terms of SiO2 based on the titanium dioxide particles.
6. A plastic resin composition according to claim 1, wherein the coating amount of the organic compound is in the range of 0.5-5% by weight based on the titanium dioxide particles.
7. A process for producing a plastic resin composition comprising
forming a dense hydrous silica coating on titanium dioxide particles and thereafter forming an organic compound coating on the surface of the dense hydrous silica coating and obtaining a titanium dioxide pigment, and
blending the titanium dioxide pigment in a molten LDPE resin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A carrier for the production of an epoxidation catalyst, which carrier is obtained by preparing a carrier precursor containing (a) \u03b1-alumina, (b) silicon or a compound thereof, and (c) at least one element selected from the class consisting of germanium, tin, lead, phosphorus, antimony, and bismuth or a compound thereof and subsequently subjecting said precursor to a heat treatment in a non-oxidative gas.
2. A carrier according to claim 1, wherein said non-oxidative gas is at least one member selected from the group consisting of a reducing gas, an inert gas, and a gas having an oxygen concentration of not more than 10 vol. %.
3. A carrier according to claim 2, wherein said non-oxidative gas is at least one member selected from the group consisting of hydrogen gas, carbon monoxide gas, nitrogen oxide gas, dinitrogen oxide gas, ammonia, and a mixture of such gas with an inert gas.
4. A carrier according to claim 2, wherein said inert gas is at least one member selected from the group consisting of nitrogen gas, argon gas, rare gas, carbon dioxide gas, and alkane gas.
5. A carrier according to claim 3, wherein said non-oxidative gas is a mixture of hydrogen and an inert gas.
6. A carrier according to claim 5, wherein said non-oxidative gas is a mixture of hydrogen gas having a hydrogen concentration in the range of 0.1\u201350 vol. % and nitrogen gas.
7. A carrier according to claim 2, wherein said non-oxidative gas is a gas having an oxygen concentration of not more than 10 vol. %.
8. A carrier according to claim 5, wherein said non-oxidative gas is a mixture of hydrogen gas having a hydrogen concentration in the range of 0.1\u201315 vol. % and nitrogen gas.
9. A carrier according to claim 1, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
10. A carrier according to claim 1, wherein said carrier precursor contains (a) \u03b1-alumina, (b) silicon or a compound thereof, and (c) at least one element selected from the class consisting of antimony, phosphorus, and bismuth or a compound thereof.
11. A carrier according to claim 1, wherein said carrier precursor contains (a) \u03b1-alumina, (b) silicon or a compound thereof, and (c) antimony or an antimony compound.
12. A carrier according to claim 1, wherein said carrier has a BET specific surface area in the range of 0.1\u201310 m2g, a water absorption ratio in the range of 10\u201350%, an average pore diameter in the range of 0.1\u20135 \u03bcm, and an apparent porosity in the range of 20\u201380%.
13. A catalyst, comprising silver and a carrier set forth in claim 1, wherein the silver is deposited on the carrier.
14. A catalyst according to claim 13, wherein the amount of the silver is in the range of 1\u201330 mass %.
15. A catalyst according to claim 14, further comprising a reaction promoter, wherein the reaction promoter is a metal element selected from the group consisting of alkali metals and thallium, and is also deposited on the carrier; and the amount of the reaction promoter is 0.0001\u20135 mass % (calculated as M2O, M being an alkali metal or thallium).
16. A method for the production of an epoxide by subjecting a corresponding unsaturated hydrocarbon having 2\u20134 carbon atoms to gas phase partial oxidation with a molecular oxygen-containing gas in the presence of a catalyst set forth in claim 13.
17. A carrier according to claim 2, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
18. A carrier according to claim 3, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
19. A carrier according to claim 4, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
20. A carrier according to claim 5, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
21. A carrier according to claim 6, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
22. A carrier according to claim 7, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.
23. A carrier according to claim 8, wherein the heat treatment in a non-oxidative gas is carried out at a temperature in the range of 400\u20131700\xb0 C.

1. A mixed-voltage inputoutput buffer, comprising:
a first N-type transistor coupled to an input circuit;
a second N-type transistor coupled to said first N-type transistor and an inputoutput pad;
a dynamic gate-controlled circuit externally connected to a high-level voltage and coupled to said inputoutput pad, a gate of said first N-type transistor and a gate of said second N-type transistor;
an output circuit externally connected to a low-level voltage and coupled to said first N-type transistor and said input circuit, wherein said output circuit is a voltage slew-rate control output circuit; and
a pre-driver circuit coupled to said output circuit and said dynamic gate-controlled circuit and controlling a voltage of said output circuit according to an output-enable signal and input data.
2. The mixed-voltage inputoutput buffer according to claim 1, wherein said dynamic gate-controlled circuit further comprises:
a level shifter coupled to said pre-driver circuit and receiving a voltage signal sent out by said pre-driver circuit and pulling up a level of said voltage signal;
a first inverter, wherein one end of said first inverter is coupled to said level shifter, and an other end is coupled to a second inverter and a gate of a third N-type transistor; and
a gate-tracking circuit coupled to said second inverter, said third N-type transistor, said gate of said first N-type transistor, said gate of said second N-type transistor and said inputoutput pad.
3. The mixed-voltage inputoutput buffer according to claim 2, wherein said gate-tracking circuit further comprises two first P-type transistors, which are coupled to each other.
4. The mixed-voltage inputoutput buffer according to claim 1, wherein said output circuit further comprises a pull-up P-type transistor and a pull-down N-type transistor.
5. The mixed-voltage inputoutput buffer according to claim 1, wherein said voltage slew-rate control output circuit further comprises a plurality of parallel pull-up P-type transistors and a plurality of parallel pull-down N-type transistors.
6. The mixed-voltage inputoutput buffer according to claim 1, wherein when said output-enable signal is high, said inputoutput buffer transmits an output signal from an output end of said pre-driver circuit transmits to said inputoutput pad.
7. The mixed-voltage inputoutput buffer according to claim 1, wherein said input circuit further comprises:
a second P-type transistor coupled to said output circuit and said first N-type transistor;
a third inverter coupled to said second P-type transistor, said output circuit and said first N-type transistor; and
a fourth inverter coupled to said second P-type transistor and said third inverter.
8. The mixed-voltage inputoutput buffer according to claim 1, wherein when said output-enable signal is low, said inputoutput buffer transmits said input signal from said inputoutput pad to an input end of said input circuit, and said pre-driver circuit turns off said output circuit, and said gate of said first N-type transistor maintains biased at said low-level voltage, and said gate of said second N-type transistor varies with a voltage of said inputoutput pad.
9. The mixed-voltage inputoutput buffer according to claim 8, wherein when said input signal received by said inputoutput buffer is at 0V voltage, said gate of said second N-type transistor is biased at said low-level voltage to enable said inputoutput pad to transmit a 0V input signal to said input circuit.
10. The mixed-voltage inputoutput buffer according to claim 8, wherein when said input signal received by said inputoutput buffer is at said high-level voltage, said gate of said second N-type transistor is biased at double said low-level voltage to enable said inputoutput pad to transmit an input signal of said low-level voltage to said input circuit via said first and second N-type transistors.
11. The mixed-voltage inputoutput buffer according to claim 6, wherein when said output signal transmitted by the output end of said pre-driver circuit is at said low-level voltage, said pre-driver circuit turns on a pull-up P-type transistor of said output circuit and turns off a pull-down N-type transistor of said output circuit, and said gate of said first N-type transistor and said gate of said second N-type transistor are biased at double said low-level voltage to enable the output end of said pre-driver circuit to transmit an output signal of said low-level voltage to said inputoutput pad.
12. The mixed-voltage inputoutput buffer according to claim 6, wherein when said output signal transmitted by the output end of said pre-driver circuit is at 0V, said pre-driver circuit turns off a pull-up P-type transistor of said output circuit and turns on a pull-down N-type transistor of said output circuit, and said gate of said first N-type transistor and said gate of said second N-type transistor are biased at said low-level voltage to enable the output end of said pre-driver circuit to transmit a 0V output signal to said inputoutput pad.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A sequential semiconductor device tester comprising:
a test pattern generating module for generating test pattern data; and
a set of m test execution modules including first through mth test execution modules connected in series, wherein the test pattern data is received by the first test execution module from test pattern generating module and the test pattern data is then sequentially relayed to the second through mth test execution modules connected in series to test a set of n DUTs connected to each of the first through mth test execution modules and generate test result data for each of the set of n DUTs.
2. The tester in accordance with claim 1, wherein the test pattern generating module comprises:
a test pattern data generator for generating the test pattern data; and
a test pattern generating module communication interface for transmitting the test pattern data to the first test execution module and for receiving the test result data from each of the set of m test execution modules.
3. The tester in accordance with claim 1, wherein the each of the set of m test execution modules comprises:
a test execution module communication interface for transceiving the test pattern data and the test result data; and
a test execution unit for applying the test pattern data received through the test execution module communication interface to the DUT and receiving an output of the DUT corresponding to the test pattern data from the DUT to generate the test result data.
4. The tester in accordance with claim 1, wherein the test pattern generating module or the first through mth test execution modules transmits the test result data to an external apparatus.
5. The tester in accordance with claim 1, wherein the test pattern data or the test result data comprises control data for controlling each of the first through mth test execution modules.
6. The tester in accordance with claim 5, wherein the control data comprises an identification information of each of the first through mth test execution modules.
7. The tester in accordance with claim 6, wherein each of the first through mth test execution modules relays the test pattern data and the test result data to other test execution modules based on the identification information except the test pattern data or the test result data designated thereto.
8. The tester in accordance with claim 2, wherein the test pattern generating module communication interface receives a test pattern program for generating the test pattern data from an external apparatus.
9. The tester in accordance with claim 2, wherein the test pattern generating module communication interface receives a test pattern of an application environment for generating the test pattern data from an external apparatus, and wherein the test pattern data generator generates the test pattern data based on the test pattern of the application environment.
10. The tester in accordance with claim 2, wherein the test pattern data generator generates the test pattern data based on a test pattern of an application environment stored therein.
11. The tester in accordance with claim 2, wherein the test pattern generating module further comprises a synchronization buffer for transceiving the test pattern data and the test result data with a plurality of the first test execution modules synchronously.
12. The tester in accordance with claim 1, wherein the test pattern data comprises a control command for testing the DUT, a clock signal, write data to be written to the DUT and expected data for the test result data.
13. The tester in accordance with claim 12, wherein each of the set of m test execution modules comprises a test execution unit for applying the test pattern data to the DUT and receiving an output of the DUT corresponding to the test pattern data from the DUT to generate the test result data, the test execution unit comprising:
a clock generator for generating a synchronous clock based on the clock signal;
a control command interpreter for interpreting the control command based on the synchronous clock to be applied to the DUT;
a driver for applying the write data to the DUT based on the control command and the synchronous clock; a comparator for comparing the test result data to the expected data to determine a defectiveness of the DUT; and
a test result storage for storing a result of the determination of the comparator.
14. The tester in accordance with claim 1, wherein the test pattern generating module is accommodated in a single test pattern generating board and the first through mth test execution modules are accommodated in a single test execution board, the single test pattern generating board and the single test execution board are connected to each other via a connector.