1. A bug infestation-resistant bed comprising:
a rectangular metal frame comprising four elongate, rigid frame members, wherein:
each of the four rigid frame members extends between and rigidly couples at each of two adjacent corners of the frame,
a first pair of the rigid frame members form end rails, each end rail of the first pair of end rails being disposed at one or another of opposing ends of the frame,
a second pair of the rigid frame members form side rails, each side rail of the second pair of side rails being disposed at one or another of opposing sides of the frame, and
each rigid frame member extends perpendicularly relative to each directly adjacent rigid frame member;
one or more elongate, rigid metal support members extending transversely across the frame between the opposing side rails, wherein each opposing end of each of the one or more rigid support members overlaps and couples with a respective one or other of the opposing side rails;
four metal legs, wherein:
each of the four metal legs is rigidly coupled at and extends downwardly from a respective one of four corners of the frame, and
each of the four metal legs is either or both of powder coated and painted, forming a suitably smooth surface finish to inhibit frictional engagement by the feet of a bedbug; and
a metal, wire mesh infill expanse coupled with each of the end rails and the side rails, wherein the wire mesh forms a planar support surface extending within a perimeter of the frame.
2. The bed of claim 1, wherein each of the four corners of the rectangular frame comprises respective ends of a side rail and an adjacent end rail rigidly coupled in a right-rectangular arrangement.
3. The bed of claim 1 further comprising:
a mattress extended across and supported by the infill expanse, wherein the mattress comprises either or both of a dense, seamless foam material and a seam-welded slip-cover.
4. The bed of claim 1, wherein one or more of the frame members, the support members, and the four legs possess a perpendicular transverse cross-sectional angle.
5. The bed of claim 1, wherein each of the four legs includes a stop rigidly coupled within an open angled interior region of the leg, wherein the stop is disposed and configured to rest atop an outside corner of a frame of a second such bed when the bed is vertically stacked upon the second bed, and to establish and maintain a spaced apart and planar-parallel relationship between the infill expanse of the bed and an infill expanse of the second bed.
6. The bed of claim 3, wherein the four legs are splayed outwardly from the frame at an effective vertical stacking angle of between approximately three and approximately eight degrees from vertical.
7. The bed of claim 1, wherein the color of the powder coated andor painted frame is white, off-white, or similarly light.
8. The bed of claim 1, wherein the infill, expanse is formed of crisscross-woven wires.
9. The bed of claim 3, wherein the mattress is configured dimensionally to extend substantially co-extensively with the infill expanse when disposed upon the bed for use.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A non-volatile semiconductor memory device comprising:
a memory cell array comprising a plurality of bit-lines, a plurality of word-lines intersecting the bit-lines, a source-line, and a plurality of NAND strings, each NAND string comprising a plurality of memory cells connected in series, each memory cell comprising a control gate connected to one of the word-lines, each NAND string comprising ends connected to the source-line and one of the bit-lines, respectively; and
a data write portion configured to repeat a write loop of writing data in units of a page comprising a plurality of memory cells connected to one word-line,
the data write portion comprising, in the write loop,
a first operation mode of sequentially performing a program operation of recording data to a memory cell and a first verify operation of verifying data record in the memory cell, and
a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation of verifying data record in the memory cell,
the data write portion comprising,
in the first verify operation,
precharging a bit-line connected to a predetermined first memory cell of the memory cells and a bit-line connected to a second memory cell in the same page as the first memory cell, the second memory cell being adjacent to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell,
then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell,
precharging the bit-line connected to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell.
2. The non-volatile semiconductor memory device according to claim 1, wherein
each memory cell stores N values per cell (N is an integer of two or more), and
the data write portion applies, in the second verify operation of the write loop that may provide most of the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
3. The non-volatile semiconductor memory device according to claim 1, wherein
in a predetermined write loop performed in the second operation mode, the verify pulse necessary for the first verify operation is substantially the same as the verify pulse necessary for the second verify operation.
4. The non-volatile semiconductor memory device according to claim 1, wherein
each memory cell stores N values per cell (N is an integer of two or more),
the data write portion applies, in the first verify operation of the write loop that may provide the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
5. The non-volatile semiconductor memory device according to claim 1, wherein
in the change direction of the threshold voltage of the memory cell by the program operation, with a preliminary verify voltage being defined as a predetermined voltage lower than the desired threshold voltage corresponding to data to be written to the first memory cell,
the data write portion verifies, in a predetermined write loop, whether the threshold voltage of the first memory cell has reached the preliminary verify voltage, and according to the verify result, sets the program pulse necessary for the program operation in the next write loop.
6. The non-volatile semiconductor memory device according to claim 5, wherein
the increment between the program pulse used in a predetermined write loop and the program pulse used in a next write loop is a first increment for the threshold voltage of the first memory cell having not reached the preliminary verify voltage in the predetermined write loop, and the increment is a second increment for the threshold voltage of the first memory cell having reached the preliminary verify voltage in the predetermined write loop, and the second increment is smaller than the second increment.
7. The non-volatile semiconductor memory device according to claim 1, wherein
each memory cell stores N values per cell (N is an integer of two or more), the data write portion uses a stepped verify pulse to perform the first and second verify operations, and the steps of the verify pulse correspond to the respective verify voltages necessary to verify respective data storage.
8. A non-volatile semiconductor memory device comprising:
a memory cell array comprising a plurality of bit-lines, a plurality of word-lines intersecting the bit-lines, a source-line, and a plurality of NAND strings, each NAND string comprising a plurality of memory cells connected in series, each memory cell comprising a control gate connected to one of the word-lines, each NAND string comprising ends connected to the source-line and one of the bit-lines, respectively; and
a data write portion configured to repeat a write loop of writing data in units of a page comprising a plurality of memory cells connected to one word-line,
the data write portion comprising, in the write loop,
a first operation mode of sequentially performing a program operation of recording data to a memory cell and a first verify operation of verifying data record in the memory cell, and
a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation of verifying data record in the memory cell,
the data write portion comprising,
in the first verify operation,
precharging a bit-line connected to a predetermined first memory cell of the memory cells and a bit-line connected to a second memory cell in the same page as the first memory cell, the second memory cell being adjacent to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell,
then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell,
precharging the bit-line connected to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell, and
the data write portion performing in the second operation mode in the write loop of the repeated write loops which the write loop may provide, in each data, most of the memory cells in which the data write is completed.
9. The non-volatile semiconductor memory device according to claim 8, wherein
each memory cell stores N values per cell (N is an integer equal of two or more),
the data write portion alternately repeats a first operation mode period of performing one or more continuous write loops in the first operation mode and a second operation mode period of performing one or more continuous write loops in the second operation mode, and
in one data write, the second operation mode period appears in the range from one to N\u22121 times.
10. The non-volatile semiconductor memory device according to claim 8, wherein
each memory cell stores N values per cell (N is an integer of two or more), and
the data write portion applies, in the second verify operation of the write loop that may provide most of the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
11. The non-volatile semiconductor memory device according to claim 8, wherein
in a predetermined write loop performed in the second operation mode, the verify pulse necessary for the first verify operation is substantially the same as the verify pulse necessary for the second verify operation.
12. The non-volatile semiconductor memory device according to claim 8, wherein
each memory cell stores N values per cell (N is an integer of two or more),
the data write portion applies, in the first verify operation of the write loop that may provide the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
13. The non-volatile semiconductor memory device according to claim 8, wherein
in the change direction of the threshold voltage of the memory cell by the program operation, with a preliminary verify voltage being defined as a predetermined voltage lower than the desired threshold voltage corresponding to data to be written to the first memory cell,
the data write portion verifies, in a predetermined write loop, whether the threshold voltage of the first memory cell has reached the preliminary verify voltage, and according to the verify result, sets the program pulse necessary for the program operation in the next write loop.
14. The non-volatile semiconductor memory device according to claim 13, wherein
the increment between the program pulse used in a predetermined write loop and the program pulse used in a next write loop is a first increment for the threshold voltage of the first memory cell having not reached the preliminary verify voltage in the predetermined write loop, and the increment is a second increment for the threshold voltage of the first memory cell having reached the preliminary verify voltage in the predetermined write loop, and the second increment is smaller than the second increment.
15. A non-volatile semiconductor memory device comprising:
a memory cell array comprising a plurality of bit-lines, a plurality of word-lines intersecting the bit-lines, a source-line, and a plurality of NAND strings, each NAND string comprising a plurality of memory cells connected in series, each memory cell comprising a control gate connected to one of the word-lines, each NAND string comprising ends connected to the source-line and one of the bit-lines, respectively; and
a data write portion configured to repeat a write loop of writing data in units of a page comprising a plurality of memory cells connected to one word-line,
the data write portion comprising, in the write loop,
a first operation mode of sequentially performing a program operation of recording data to a memory cell and a first verify operation of verifying data record in the memory cell, and
a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation of verifying data record in the memory cell,
the data write portion comprising,
in the first verify operation,
precharging a bit-line connected to a predetermined first memory cell of the memory cells and a bit-line connected to a second memory cell in the same page as the first memory cell, the second memory cell being adjacent to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell,
then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell,
precharging the bit-line connected to the first memory cell, and
sensing a current through the bit-line connected to the first memory cell to verify data of the first memory cell,
each memory cell storing N values (N is an integer equal of two or more),
the data write portion alternately repeating a first operation mode period of performing one or more continuous write loops in the first operation mode and a second operation mode period of performing one or more continuous write loops in the second operation mode, and
in one data write, the second operation mode period appearing in the range from one to N\u22121 times.
16. The non-volatile semiconductor memory device according to claim 15, wherein
each memory cell stores N values per cell (N is an integer of two or more), and
the data write portion applies, in the second verify operation of the write loop that may provide most of the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
17. The non-volatile semiconductor memory device according to claim 15, wherein
in a predetermined write loop performed in the second operation mode, the verify pulse necessary for the first verify operation is substantially the same as the verify pulse necessary for the second verify operation.
18. The non-volatile semiconductor memory device according to claim 15, wherein
each memory cell stores N values per cell (N is an integer of two or more),
the data write portion applies, in the first verify operation of the write loop that may provide the memory cells in which the write of the n-th data (1<n<N) is completed, the verify pulse only necessary for the verify of the n-th data to the word-line.
19. The non-volatile semiconductor memory device according to claim 15, wherein
in the change direction of the threshold voltage of the memory cell by the program operation, with a preliminary verify voltage being defined as a predetermined voltage lower than the desired threshold voltage corresponding to data to be written to the first memory cell,
the data write portion verifies, in a predetermined write loop, whether the threshold voltage of the first memory cell has reached the preliminary verify voltage, and according to the verify result, sets the program pulse necessary for the program operation in the next write loop.
20. The non-volatile semiconductor memory device according to claim 19, wherein
the increment between the program pulse used in a predetermined write loop and the program pulse used in a next write loop is a first increment for the threshold voltage of the first memory cell having not reached the preliminary verify voltage in the predetermined write loop, and the increment is a second increment for the threshold voltage of the first memory cell having reached the preliminary verify voltage in the predetermined write loop, and the second increment is smaller than the second increment.