Author: claimsbot

1. A power module comprising:
a plate-shaped output electrode;
a pair of power devices stacked with the output electrode arranged between the pair of power devices, the output electrode being laminated to the pair of power devices in part of a stacked area of the power devices; and
an N-electrode laminated to one of the power devices, and a P-electrode laminated to the other power device, the N-electrode and the P-electrode being laminated to surfaces of the power devices that face one another, in a region of the stacked area where the output electrode is not laminated to the power devices,
wherein the output electrode is anisotropic such that thermal conductivity in a direction orthogonal to a stacking direction in which the N-electrode and the P-electrode are stacked is greater than thermal conductivity in the stacking direction, and the output electrode extends in the orthogonal direction from the stacked area where the pair of power devices are stacked, and the N-electrode and the P-electrode extend in the orthogonal direction while maintaining an opposing positional relationship.
2. The power module according to claim 1, wherein the output electrode is laminated to the pair of power devices in part of the stacked area of the power devices, and the N-electrode and the P-electrode are laminated to the surfaces of the power devices that face one another, in a region of the stacked area where the output electrode is not laminated to the power devices.
3. The power module according to claim 1, wherein at least one of the N-electrode or the P-electrode is anisotropic such that the thermal conductivity in the orthogonal direction is greater than the thermal conductivity in the stacking direction.
4. The power module according to claim 1, wherein the N-electrode and the P-electrode are stacked with the pair of power devices arranged between the N-electrode and the P-electrode.
5. The power module according to claim 1, further comprising a cooler that is mounted to the output electrode in a region where the output electrode extends in the orthogonal direction from the stacked area.
6. The power module according to claim 1, further comprising a condenser that is connected between portions of the N-electrode and the P-electrode that extend in the orthogonal direction.
7. The power module according to claim 1, further comprising a thermoelectric transducer that is incorporated on the opposite side of one of the power devices from the side with the surface to which output electrode is laminated.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for loading data from a remote data source record by record, in a computer system network connecting a source site and a target site via a database connection communication line, the method comprising the following steps:
(a) coupling the source site to at least one data source and to a software server having multi-database access to DBMSs;
(b) at the target site requesting data loading from the source site via a block of Structured Query Language (SQL) statements; and
(c) transporting data record by record via the database connection communication line according to a multi-database access communication protocol, wherein the target site loading records concurrently with the unloading of records in the source site.
2. The method according to claim 1, wherein a data record is transported across the database connection communication line as soon as one or more data records are unloaded from the source site, and data loading at the target site beginning as soon as a record was transported to the target site.
3. The method according to claim 1, wherein the data loading is performed in a pipeline manner, loading data records in multiple partitions with a plurality of parallel streams, pointed to by a plurality of data source partition cursors.
4. The method according to claim 1, wherein the block of SQL statements comprises dynamic executable SQL statements performing in the EXECUTE IMMEDIATE mode.
5. The method according to claim 1, wherein the block of SQL statements comprises:
a SQL DECLARE CURSOR FOR SELECT statement, for defining a cursor referencing separately each SELECT statement result record unloading from the server site, and
a LOAD command and an operator INCURSOR with the cursor name for pointing to the receiving record at the target site.
6. The method according to claim 1, wherein the server site has access to multiple data sources, physically distributed and disparate DBMSs, residing on different hardware systems and possibly storing data in a different format.
7. The method according to claim 6, wherein the server site loads data from multiple data sources, further comprising a step for using a means for consolidating data from multiple data sources.
8. The method according to claim 1, wherein the database connection communication line utilizing the TCPIP protocol, and the software server has multi-database access to DBMSs including a Distributed Relational Database Architecture(DRDA).
9. A system for loading data from a remote data source record by record, comprising:
a source site coupled to at least one data source and having a software server with multi-database access to DBMSs;
a target site requesting data loading from the source site via a block of Structured Query Language (SQL) statements; and
a database connection communication line for transporting data record by record and according to a multi-database access communication protocol, wherein the target site loading records concurrently with the unloading of records in the source site.
10. The system according to claim 9, wherein a data record is transported across the database connection communication line as soon as one or more data records are unloaded from the source site, and data loading at the target site beginning as soon as a record was transported to the target site.
11. The system according to claim 9, wherein the data loading is performed in a pipeline manner, loading data records in multiple partitions with a plurality of parallel streams, pointed to by a plurality of data source partition cursors.
12. The system according to claim 9, wherein the block of SQL statements comprises dynamic executable SQL statements performing in the EXECUTE IMMEDIATE mode.
13. The system according to claim 9, wherein the block of SQL statements comprises:
a SQL DECLARE CURSOR FOR SELECT statement, for defining a cursor referencing separately each SELECT statement result record unloading from the server site, and
a LOAD command and an operator INCURSOR with the cursor name for pointing to the receiving record at the target site.
14. The system according to claim 9, wherein the server site has access to multiple data sources, physically distributed and disparate DBMSs, residing on different hardware systems and possibly storing data in a different format.
15. The system according to claim 14, wherein the server site loads data from multiple data sources, further comprising a means for consolidating data from multiple data sources.
16. The system according to claim 9, wherein the database connection communication line utilizing the TCPIP protocol, and the software server has multi-database access to DBMSs including a Distributed Relational Database Architecture (DRDA).
17. A program storage device readable by a computer tangibly embodying a program of instructions executable by the computer to perform method steps for loading data from a remote data source record by record, in a computer system network connecting a source site and a target site via a database connection communication line, the method comprising the following steps:
(a) coupling the source site to at least one data source and to a software server having multi-database access to DBMSs;
(b) at the target site requesting data loading from the source site via a block of Structured Query Language (SQL) statements; and
(c) transporting data record by record via the database connection communication line according to a multi-database access communication protocol, wherein the target site loading records concurrently with the unloading of records in the source site.
18. The method according to claim 17, wherein a data record is transported across the database connection communication line as soon as one or more data records are unloaded from the source site, and data loading at the target site beginning as soon as a record was transported to the target site.
19. The method according to claim 17, wherein the data loading is performed in a pipeline manner, loading data records in multiple partitions with a plurality of parallel streams, pointed to by a plurality of data source partition cursors.
20. The method according to claim 17, wherein the block of SQL statements comprises dynamic executable SQL statements performing in the EXECUTE IMMEDIATE mode.
21. The method according to claim 17, wherein the block of SQL statements comprises:
a SQL DECLARE CURSOR FOR SELECT statement, for defining a cursor referencing separately each SELECT statement result record unloading from the server site, and
a LOAD command and an operator INCURSOR with the cursor name for pointing to the receiving record at the target site.
22. The method according to claim 17, wherein the server site has access to multiple data sources, physically distributed and disparate DBMSs, residing on different hardware systems and possibly storing data in a different format.
23. The method according to claim 22, wherein the server site loads data from multiple data sources, further comprising a step for using a means for consolidating data from multiple data sources.
24. The method according to claim 17, wherein the database connection communication line utilizing the TCPIP protocol, and the software server has multi-database access to DBMSs including a Distributed Relational Database Architecture (DRDA).

1. A method of forming contact openings in a semiconductor device comprising the steps of:
providing a semiconducting substrate;
forming an etch stop layer on said semiconducting substrate;
forming a dielectric layer on said etch stop layer;
forming a bottom anti-reflective coating (BARC) on said dielectric layer;
forming and patterning a mask on said BARC layer; and,
forming at least a first contact opening exposing said etch stop layer by a first etching process.
2. The method of claim 1, further comprising the step of removing said etch stop layer exposed in said first contact opening by a second etching process.
3. The method of claim 1, wherein said first contact opening comprising a tapered cross section with a top opening larger than a bottom opening.
4. The method of claim 1, wherein the etch stop layer comprises a lowermost silicon oxynitride portion and an uppermost silicon nitride portion.
5. The method of claim 4, wherein the lowermost silicon oxynitride portion is formed having a thickness of about 100 Angstroms to about 500 Angstroms and the uppermost silicon nitride layer portion is formed having a thickness of about 200 Angstroms to about 1000 Angstroms.
6. The method of claim 1, wherein the BARC layer comprises a silicon oxynitride layer and an overlying capping silicon oxide layer.
7. The method of claim 6, wherein the BARC layer is formed having a thickness of about 400 Angstroms to about 700 Angstroms and the capping silicon oxide layer is formed having a thickness of about 100 to about 400 Angstroms.
8. The method of claim 1, wherein the first etching process comprises forming a second contact opening, wherein the second contact opening is etched to a greater depth than the first contact opening.
9. The method of claim 8, wherein the first contact opening extends to a top portion of a polysilicon gate and the second contact opening extends to one of a source and drain region.
10. The method of claim 1, wherein the second etching process is carried out wherein a self-bias voltage is maintained below about 100 Volts.
11. The method of claim 10, wherein the second etching process comprises a reactive ion etch (RIE) etcher selected from the group consisting of an inductively coupled power (ICP), Transformer coupled power (TCP) magnetic-enhanced reactive ion etcher (MERIE).
12. The method of claim 1, wherein the semiconductor substrate further comprises CMOS transistors formed underlying the etching stop layer.
13. A method of forming contact openings in a semiconductor device in a bi-level etching process comprising the steps of:
providing a semiconducting substrate comprising CMOS transistors formed on the substrate;
forming an etch stop layer on the semiconducting substrate including the CMOS transistors;
forming at least one dielectric layer on the etch stop layer;
forming a bottom anti-reflective coating (BARC) layer on the at least one dielectric layer;
forming and patterning an etching mask on said BARC layer; and,
forming first and second contact openings exposing said etch stop layer said second contact opening having a depth greater than the than the first contact opening.
14. The method of claim 13, further comprising a second etching process to etch through a thickness portion the etch stop layer.
15. The method of claim 13, wherein the first and second etching processes comprise a dry etching process.
16. The method of claim 13, wherein the first and second contact openings comprising a tapered cross section with a top opening larger than a bottom opening.
17. The method of claim 13, wherein the etch stop layer comprises a lowermost silicon oxynitride portion and an uppermost silicon nitride portion.
18. The method of claim 13 wherein the BARC layer comprises a lower silicon oxynitride layer and an upper capping silicon oxide layer.
19. The method of claim 13, wherein the first contact opening extends to a top portion of a polysilicon gate and the second contact opening extends to one of a source and drain region.
20. The method of claim 14, wherein the second etching process is carried out wherein a self-bias voltage is maintained below about 100 Volts.
21. The method of claim 20, wherein the second etching process comprises a reactive ion etch (RIE) etcher selected from the group consisting of an inductively coupled power (ICP), transformer coupled power (TCP), and magnetic-enhanced reactive ion etcher (MERIE).
22. The method of claim 20, wherein the second etching process is carried out in and magnetic-enhanced reactive ion etcher (MERIE).
23. A semiconductor device comprising:
a semiconducting substrate comprising CMOS transistors disposed on the substrate;
a contact etch stop layer disposed on the semiconducting substrate including the CMOS transistors;
at least one dielectric layer on the etch stop layer;
a first contact opening extending to a first level through the etch stop layer thickness and a second contact opening extending to a second level through the etch stop layer the second level deeper than the first level.
24. The semiconductor device of claim 23, wherein the first and second contact openings comprising a tapered cross section with a top opening larger than a bottom opening.
25. The semiconductor device of claim 23, wherein the etch stop layer comprises a lowermost silicon oxynitride portion and an uppermost silicon nitride portion.
26. The semiconductor device of claim 24, wherein the lowermost silicon oxynitride portion is formed having a thickness of about 100 Angstroms to about 500 Angstroms and the uppermost silicon nitride layer portion is formed having a thickness of about 200 Angstroms to about 1000 Angstroms.
27. The semiconductor device of claim 23, wherein the first contact opening extends to a top portion of a polysilicon gate and the second contact opening extends to one of a source and drain region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory circuit comprising:
a write signal driving circuit connected to a data input signal line to which write data is inputted from the outside, a write enable signal line for permitting the write data to be written, a first write signal line, and a second write signal line to output a first write signal and a second write signal from said first write signal line and said second write signal line, respectively, based on the write data from said data input signal line and a write enable signal from said write enable signal line;
a write signal amplifying circuit connected to a column signal line for selecting a column of said memory circuit to write or read data, said first write signal line, said second write signal line, a first bit signal line and a second bit signal line to output the first write signal and the second write signal inputted from said first write signal line and said second write signal line as a first driving write signal and a second driving write signal from said first bit signal line and said second bit signal line, respectively, based on a column signal inputted from said column signal line;
a memory cell circuit connected to said first bit signal line and said second bit signal line to store data, based on the first driving write signal and the second driving write signal line inputted from said first bit signal line and said second bit signal line, and to output the stored data as a first read signal and a second read signal from said first bit signal line and said second bit signal line; and
a global signal driving circuit connected to said first bit signal line, said first write signal line, said column signal line and a global signal line for outputting data stored in said memory cell circuit to the outside to output the first read signal as a global signal from said global signal line when the first read signal is inputted from said first bit signal line, and to inhibit the first driving write signal from being outputted to said global signal line, based on the first write signal inputted from said first write signal line, when the first driving write signal is inputted from said first bit signal line, with the column signal inputted from said column signal line.
2. The memory circuit according to claim 1, wherein said global signal driving circuit comprises:
a first transistor having a first gate terminal connected to said first bit signal line and a first source terminal connected to a power source to output the first read signal or the first driving write signal inputted from said first gate terminal from a first drain terminal thereof; and
a second transistor having a second gate terminal connected to said first write signal line and a second source terminal connected to said first drain terminal to output the first read signal inputted from said first source terminal from a second drain terminal thereof, and to inhibit the first driving write signal from being outputted from said second drain terminal, based on the first write signal inputted from said first gate terminal, when the first driving write signal is inputted from said first source terminal.
3. The memory circuit according to claim 2, wherein said global signal driving circuit further comprises:
a third transistor having a third gate terminal connected to said column signal line and a third source terminal connected to said second drain terminal to inhibit the first read signal or the first driving write signal from being outputted from a third drain terminal thereof, based on the column signal inputted from said third gate terminal, when said memory circuit is not selected.
4. The memory circuit according to claim 1, wherein said global signal driving circuit comprises:
a first transistor having a first gate terminal connected to said first bit signal line and a first source terminal connected to a power source to output the first read signal or the first driving write signal inputted from said first gate terminal from a first drain terminal thereof;
a second transistor having a second gate terminal connected to said column signal line and a second source terminal connected to said first drain terminal to inhibit the first read signal or the first driving write signal from being outputted from a second drain terminal thereof, based on the column signal inputted from said second gate terminal, when said memory circuit is not selected;
an output circuit having a third transistor having a third gate terminal connected to said second drain terminal, a third drain terminal connected to said global signal line and a third source terminal, and a fourth transistor having a fourth gate terminal connected to said global signal line, a fourth drain terminal connected to said second drain terminal and said third gate terminal, and a fourth source terminal connected to said third source terminal to output the first read signal or the first driving write signal inputted from said third gate terminal to said global signal line; and
an inhibit circuit having an inverter connected to said first write signal line to invert the first write signal inputted from said first write signal line, and a fifth transistor having a fifth gate terminal to which the inverted first write signal outputted from said inverter circuit is inputted, a fifth drain terminal connected to said third source terminal and said fourth source terminal and a fifth source terminal grounded to inhibit the first driving write signal from said output circuit from being outputted to said global signal line, based on the first write signal inputted from said first write signal line.
5. A control method of a memory circuit having a write signal driving circuit inputted thereto write data and outputting a write signal, a write signal amplifying circuit inputted thereto the write signal and outputting a driving write signal, a memory cell circuit inputted thereto the driving write signal and storing data and outputting a read signal and a global signal driving circuit inputted thereto the read signal and outputting a global signal, the control method comprising the steps of:
by said write signal driving circuit connected to a data input signal line to which the write data is inputted from the outside, a write enable signal line for permitting the write data to be written, a first write signal line and a second write signal line, outputting a first write signal and a second write signal from said first write signal line and said second write signal line, respectively, based on the write data from said data input signal line and a write enable signal from said write enable signal line;
by said write signal driving circuit connected to a column signal line for selecting a column of said memory circuit to write or read data, said first write signal line, said second write signal line, a first bit signal line and a second bit signal line, outputting the first write signal and the second write signal inputted from said first write signal line and said second write signal line as a first driving write signal and a second driving write signal from said first bit signal line and said second bit signal line, based on a column signal inputted from said column signal line;
by said memory cell circuit connected to said first bit signal line and said second bit signal line, storing data, based on the first driving write signal and the second driving write signal inputted from said first bit signal line and said second bit signal line, and outputting the stored data as a first read signal and a second read signal from said first bit signal line and said second bit signal line; and
by said global signal driving circuit connected to said first bit signal line, said first write signal line, said column signal line and a global signal line for outputting data stored in said memory cell circuit to the outside, outputting the first read signal as the global signal from said global signal line when the first read signal is inputted from said first bit signal line, and inhibiting the first driving write signal from being outputted to said global signal line, based on the first write signal inputted from said first write signal line, when the first driving write signal is inputted from said first bit signal line, with the column signal inputted from said column signal line.
6. The control method according to claim 5, wherein said global signal driving circuit comprises:
a first transistor having a first gate terminal connected to said first bit signal line and a first source terminal connected to a power source to output the first read signal or the first driving write signal inputted from said first gate terminal from a first drain terminal thereof; and
a second transistor having a second gate terminal connected to said first write signal line and a second source terminal connected to said first drain terminal to output the first read signal inputted from said first source terminal from a second drain terminal thereof, and to inhibit the first driving write signal from being outputted from said second drain terminal, based on the first write signal inputted from said first gate terminal, when the first driving write signal is inputted from said first source terminal.
7. The control method according to claim 6, wherein said global signal driving circuit further comprises:
a third transistor having a third gate terminal connected to said column signal line and a third source terminal connected to said second drain terminal to inhibit the first read signal or the first driving write signal from being outputted from a third drain terminal thereof, based on the column signal inputted from said third gate terminal, when said memory circuit is not selected.
8. The control method according to claim 5, wherein said global signal driving circuit further comprises:
a first transistor having a first gate terminal connected to said first bit signal line and a first source terminal connected to a power source to output the first read signal or the first driving write signal inputted from said first gate terminal from a first drain terminal thereof;
a second transistor having a second gate terminal connected to said column signal line and a second source terminal connected to said first drain terminal to inhibit the first read signal or the first driving write signal from being outputted from a second drain terminal thereof, based on the column signal inputted from said second gate terminal, when said memory circuit is not selected;
an output circuit having a third transistor having a third gate terminal connected to said second drain terminal, a third drain terminal connected to said global signal line and a third source terminal, and a fourth transistor having a fourth gate terminal connected to said global signal line, a fourth drain terminal connected to said second drain terminal and said third gate terminal, and a fourth source terminal connected to said third source terminal to output the first read signal or the first driving write signal inputted from said third gate terminal to said global signal line; and
an inhibit circuit having an inverter connected to said first write signal line to invert the first write signal inputted from said first write signal line, and a fifth transistor having a fifth gate terminal to which the inverted first write signal outputted from said inverter circuit is inputted, a fifth drain terminal connected to said third source terminal and said fourth source terminal and a fifth source terminal grounded to inhibit the first driving write signal from said output circuit from being outputted to said global signal line, based on the first write signal inputted from said first write signal line.