Author: claimsbot

1. A semiconductor memory device comprising:
a memory cell,

wherein
the memory cell includes
a first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first voltage is supplied to the source terminal,
a second PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the source terminal is in a floating state,
a first NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the source terminal is in a floating state, and
a second NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second voltage lower than the first voltage is supplied to the source terminal,

the drain terminal of the first PMOS transistor, the drain terminal of the first NMOS transistor, the gate terminal of the second PMOS transistor, and the gate terminal of the second NMOS transistor are connected together, and
the drain terminal of the second PMOS transistor, the drain terminal of the second NMOS transistor, the gate terminal of the first PMOS transistor, and the gate terminal of the first NMOS transistor are connected together.
2. A semiconductor memory device comprising:
a memory cell,

wherein
the memory cell includes
a first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first voltage is supplied to the source terminal,
a second PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the drain terminal is in a floating state,
a first NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the drain terminal is in a floating state, and
a second NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second voltage lower than the first voltage is supplied to the source terminal,

the drain terminal of the first PMOS transistor, the gate terminal of the second PMOS transistor, and the gate terminal of the second NMOS transistor are connected together, and
the drain terminal of the second NMOS transistor, the gate terminal of the first PMOS transistor, and the gate terminal of the first NMOS transistor are connected together.
3. A semiconductor memory device comprising:
a memory cell,

wherein
the memory cell includes
a first PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first voltage is supplied to the source terminal,
a second PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the drain terminal is in a floating state,
a first NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first bit line is connected to the source terminal, and a word line is connected to the gate terminal,
a second NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second bit line complementary to the first bit line is connected to the source terminal, and the word line is connected to the gate terminal,
a third NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where the drain terminal of the first NMOS transistor is connected to the drain terminal of the third NMOS transistor, and
a fourth NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second voltage lower than the first voltage is supplied to the source terminal,

the drain terminal of the first PMOS transistor, the gate terminal of the second PMOS transistor, and the gate terminal of the fourth NMOS transistor are connected together, and
the drain terminal of the fourth NMOS transistor, the drain terminal of the second NMOS transistor, the gate terminal of the first PMOS transistor, and the gate terminal of the third NMOS transistor are connected together.
4. A semiconductor memory device comprising:
a memory cell,

wherein
the memory cell includes only the following four transistors,
a PMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first voltage is supplied to the source terminal,
a first NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a first bit line is connected to the source terminal, and a word line is connected to the gate terminal,
a second NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second bit line complementary to the first bit line is connected to the source terminal, and the word line is connected to the gate terminal, and
a third NMOS transistor having a source terminal, a gate terminal, and a drain terminal, where a second voltage lower than the first voltage is supplied to the source terminal,

the drain terminal of the PMOS transistor, the drain terminal of the first NMOS transistor, and the gate terminal of the third NMOS transistor are connected together, and
the drain terminal of the third NMOS transistor, the drain terminal of the second NMOS transistor, and the gate terminal of the PMOS transistor are connected together.
5. A semiconductor memory device comprising:
a memory cell,

wherein
the memory cell includes
a latch including a first and a second inverter, where an output of the first inverter is connected via a first memory node to an input of the second inverter, and an output of the second inverter is connected via a second memory node to an input of the first inverter, and
a circuit configured to read and write the latch, and

in any of the memory cells, the first inverter includes a PMOS transistor whose source or drain is cut off, and the second inverter includes an NMOS transistor whose source or drain is cut off.
6. The semiconductor memory device of claim 5, wherein
in the memory cell, either of the PMOS transistor of the first inverter and the NMOS transistor of the second inverter is excluded.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A nonvolatile memory device, comprising:
an active region being defined by an isolation layer formed in a substrate and having a recess therein in a channel width direction, wherein an upper portion of the active region having the recess projects over an upper portion of the isolation layer;
a lower insulation layer formed along a surface of the active region and a top surface of the isolation layer;
a charge storage layer formed over the lower insulation layer;
an upper insulation layer formed over the charge storage layer; and
a gate electrode formed over the upper insulation layer.
2. A nonvolatile memory device, comprising:
an active region being defined by an isolation layer formed in a substrate and having a recess therein in a channel width direction, wherein an upper portion of the active region having the recess projects over an upper portion of the isolation layer;
a tunneling insulation layer formed along a surface of the active region and a top surface of the isolation layer;
a floating gate formed over the tunneling insulation layer;
a dielectric layer formed over the floating gate; and
a control gate formed over the dielectric layer.
3. The nonvolatile memory device of claim 1, wherein the recess is formed in a \u2018U\u2019 type or a \u2018W\u2019 type.
4. The nonvolatile memory device of claim 1, wherein the active region is defined as a line type or an island type in a channel length direction.
5. The nonvolatile memory device of claim 1, wherein the lower insulation layer is formed to contact with portions of an inner wall, a bottom portion of the recess, and an outer wall of the active region.
6. The nonvolatile memory device of claim 1, wherein the lower insulation layer and the upper insulation layer include one of a silicon oxide (SiO2) layer, a layer having higher dielectric coefficient than that of the SiO2 layer and a stack structure thereof.
7. The nonvolatile memory device of claim 1, wherein the charge storage layer includes a nitride layer or a metal oxide-based layer.
8. The nonvolatile memory device of claim 1, wherein the charge storage layer includes a silicate layer.
9. A method for fabricating a nonvolatile memory device, the method comprising:
forming an isolation layer to define an active region in a substrate;
forming a recess in the active region;
exposing inner and outer walls of the active region by removing a portion of the isolation layer;
forming a lower insulation layer along a surface of the active region and a top surface of the isolation layer;
forming a charge storage layer over the lower insulation layer;
forming an upper insulation layer over the charge storage layer; and
forming a gate electrode over the upper insulation layer.
10. A method for fabricating a nonvolatile memory device, the method comprising:
forming an isolation layer to define an active region in a substrate;
forming a recess in the active region;
exposing inner and outer walls of the active region by removing a portion of the isolation layer;
forming a tunneling insulation layer along a surface of the active region and a top surface of the isolation layer;
forming a floating gate over the tunneling insulation layer;
forming a dielectric layer over the floating gate; and
forming a control gate over the dielectric layer.
11. The method of claim 9, wherein forming the isolation layer comprises:
forming a hard mask layer over the substrate;
forming a trench by etching portions of the hard mask layer and the substrate; and
forming the isolation layer to fill the trench.
12. The method of claim 11, wherein forming the recess comprises:
removing the hard mask layer over the active region;
forming a spacer on an inner wall of the isolation layer over the active region;
etching the active region to form the recess using the spacer as an etch barrier; and
removing the spacer.
13. The method of claim 12, wherein the spacer includes a nitride layer or an oxide layer.
14. The method of claim 9, further comprising depositing an insulation layer to fill the recess before exposing the inner and outer walls of the active region.
15. The method of claim 14, wherein exposing the inner and outer walls of the active region exposes the outer walls of the active region by removing a portion of the isolation layer simultaneously with exposing inner walls of the active region by removing the insulation layer.
16. The method of claim 15, wherein the insulation layer is made of the same material as the isolation layer.
17. The method of claim 9, wherein the active region is formed in a line type or an island type.
18. The method of claim 9, wherein the isolation layer includes a high density plasma (HDP) layer or a stack structure of the HDP layer and a spin on glass (SOG) layer.
19. The method of claim 9, wherein the lower insulation layer and the upper insulation layer include one of a SiO2 layer, a layer having higher coefficient than that of the SiO2 layer and a stack structure thereof.
20. The method of claim 9, wherein the charge storage layer includes a nitride layer and a metal oxide-based layer.
21. The method of claim 9, wherein the charge storage layer includes a silicate layer.

1. A method of simulating memory allocation errors in a software application, the method including:
determining a range of memory block sizes in a memory allocation function which results in a memory allocation failure, the range of memory block sizes defined by a first simulation criteria and including all memory block sizes between a minimum threshold and a maximum threshold;
initializing an application, and simultaneously executing the memory allocation function;
triggering a memory allocation failure if the application requires a memory value within the range of memory block sizes; and
varying the range of memory block sizes based on a second simulation criteria,
wherein the first simulation criteria and second simulation criteria are determined by a pre-determined range of memory block sizes for a memory failure simulation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A scanning exposure photo-mask having an exposure pattern which has a longitudinal direction, said scanning exposure photo-mask being placed in an exposure system so that said longitudinal direction of said pattern is parallel to a longitudinal direction of a slit of said exposure system.
2. The scanning exposure photo-mask as claimed in claim 1, wherein said exposure pattern comprises plural line-shaped patterns extending in a first direction along which said slit extends and said line-shaped patterns are aligned in a second direction perpendicular to said first direction.
3. The scanning exposure photo-mask as claimed in claim 2, wherein said exposure pattern comprises one of a word line pattern and a bit line pattern.
4. A scanning exposure system having a slit plate having a slit and a photo-mask stage mounted thereon with a scanning exposure photo-mask as claimed in claim 1.
5. The scanning exposure system as claimed in claim 4, wherein said photo-mask stage allows mounting said scanning exposure photo-mask in different two directions perpendicular to each other.
6. The scanning exposure system as claimed in claim 5, wherein said photo-mask stage and an objective stage mounting an objective sample for exposure are capable of allowing that said longitudinal direction of said exposure pattern of said photo-mask and a longitudinal direction of an exposed pattern on said objective sample are directed in correspondence with said longitudinal direction of said slit.
7. The scanning exposure system as claimed in claim 6, wherein said objective stage is moved by a rotational driving unit for rotating said objective stage by at least an angle of 90 degrees and an X-Y driving unit for moving said objective stage in plane.
8. A method of scanning an exposure beam defined by a slit with reference to a photo-mask having an exposure pattern which has a longitudinal direction, so that said longitudinal direction of said exposure pattern is kept in parallel to a longitudinal direction of said slit during a scanning operation.
9. The method as claimed in claim 8, wherein said slit is fixed in position, and said photo-mask is moved in a direction perpendicular to said longitudinal direction, and an objective sample for exposure is moved in an opposite direction to said direction of movement of said photo-mask.