Author: claimsbot

1. A 4-2 compressor comprising:
a first input terminal (Ai);
a second input terminal (Bi);
a third input terminal (Ci);
a fourth input terminal (Di);
a carry input terminal (Xi);
a summation output terminal (So);
a first carry output terminal (Co);
a second carry output terminal (Xo);
a first inverter (1016) having an input connected to said first input terminal and an output;
a first transfer gate (1010) having a first control input connected to said first input terminal, a second control input connected to said output of said first inverter, an input connected to said fourth input terminal and an output;
a second inverter (1008) having an input connected to said fourth input terminal and an output;
a second transfer gate (1012) having a first control input connected to said output of said first inverter, a second control input connected to said first input terminal, an input connected to said output of said second inverter and an output;
a third transfer gate (1018) having a first control input connected to said first input terminal, a second control input connected to said output of said first inverter, an input connected to said output of said second inverter and an output;
a fourth transfer gate (1020) having a first control input connected to said output of said first inverter, a second control input connected to said first input terminal, an input connected to said fourth input terminal and an output;
a third inverter (1024) having an input connected to said second input terminal and an output;
a fifth transfer gate (1026) having a first control input connected to said second input terminal, a second control input connected to said output of said third inverter, an input connected to said third input terminal and an output;
a fourth inverter (1028) having an input connected to said third input terminal and an output;
a sixth transfer gate (1029) having a first control input connected to said output of said third inverter, a second control input connected to said second input terminal, an input connected to said output of said fourth inverter and an output;
a seventh transfer gate (1030) having a first control input connected to said second input terminal, a second control input connected to said output of said third inverter, an input connected to said output of said fourth inverter and an output;
an eighth transfer gate (1032) having a first control input connected to said output of said third inverter, a second control input connected to said second input terminal, an input connected to said third input terminal and an output;
a ninth transfer gate (1034) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said fourth input terminal and an output;
a tenth transfer gate (1036) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said second input terminal and an output;
a fifth inverter (1022) having an input connected to said output of said third transfer gate and said output of said fourth transfer gate and an output;
an eleventh transfer gate (1040) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said output of said fifth inverter and an output;
a sixth inverter having an input connected to said output of said first transfer gate and said output of said second transfer gate and an output;
a twelfth transfer gate (1042) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said output of said sixth inverter and an output;
a thirteenth transfer gate (1044) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said output of said sixth inverter and an output;
a fourteenth transfer gate (1046) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said output of said fifth inverter and an output;
a seventh inverter having an input connected to said output of said ninth transfer gate and to said output of said tenth transfer gate and an output connected to said second carry output terminal;
a fifteenth transfer gate (1048) having a first control input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate, a second control input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate, an input connected to said carry input terminal and an output;
a sixteenth transfer gate (1050) having a first control input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate, a second control input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate, an input connected to said output of said first inverter and an output;
an eighth inverter (1108) having an input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate and an output;
a ninth inverter (1110) having an input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate and an output;
a seventeenth transfer gate (1052) having a first control input connected to said output of said eighth inverter, a second control input connected to said output of said ninth inverter, an input connected to said carry input terminal and an output;
an N-channel field effect transistor having a gate connected to said output of said eighth inverter and a source-drain path connected between said output of said eighth inverter and said output of said seventeenth transfer gate;
a P-channel field effect transistor having a gate connected to said output of said ninth inverter and a source-drain path connected between said output of said ninth inverter and said output of said seventeenth transfer gate;
a tenth inverter (1052) having an input connected to said output of said fifteenth transfer gate and said output of said sixteenth transfer gate and an output connected to said first carry output terminal; and
an eleventh inverter (1062) having an input connected to said output of said seventeenth transfer gate and an output connected to said summation output terminal.
2. A multiplier comprising:
a Booth encoder circuit (102) having data inputs and generating a plurality of partial product outputs;
a Wallace tree (104) having a plurality of 4-2 compressor circuits (104a\u2013104m) disposed in a plurality of layers, a first layer including a plurality 4-2 compressor circuits (104a\u2013104g) receiving said partial products from said Booth encoder circuit, each 4-2 compressor circuit having
a first input terminal (Ai),
a second input terminal (Bi),
a third input terminal (Ci),
a fourth input terminal (Di),
a carry input terminal (Xi),
a summation output terminal (So),
a first carry output terminal (Co),
a second carry output terminal (Xo),
a first inverter (1016) having an input connected to said first input terminal and an output,
a first transfer gate (1010) having a first control input connected to said first input terminal, a second control input connected to said output of said first inverter, an input connected to said fourth input terminal and an output,
a second inverter (1008) having an input connected to said fourth input terminal and an output,
a second transfer gate (1012) having a first control input connected to said output of said first inverter, a second control input connected to said first input terminal, an input connected to said output of said second inverter and an output,
a third transfer gate (1018) having a first control input connected to said first input terminal, a second control input connected to said output of said first inverter, an input connected to said output of said second inverter and an output,
a fourth transfer gate (1020) having a first control input connected to said output of said first inverter, a second control input connected to said first input terminal, an input connected to said fourth input terminal and an output,
a third inverter (1024) having an input connected to said second input terminal and an output,
a fifth transfer gate (1026) having a first control input connected to said second input terminal, a second control input connected to said output of said third inverter, an input connected to said third input terminal and an output,
a fourth inverter (1028) having an input connected to said third input terminal and an output,
a sixth transfer gate (1029) having a first control input connected to said output of said third inverter, a second control input connected to said second input terminal, an input connected to said output of said fourth inverter and an output,
a seventh transfer gate (1030) having a first control input connected to said second input terminal, a second control input connected to said output of said third inverter, an input connected to said output of said fourth inverter and an output,
an eighth transfer gate (1032) having a first control input connected to said output of said third inverter, a second control input connected to said second input terminal, an input connected to said third input terminal and an output,
a ninth transfer gate (1034) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said fourth input terminal and an output,
a tenth transfer gate (1036) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said second input terminal and an output,
a fifth inverter (1022) having an input connected to said output of said third transfer gate and said output of said fourth transfer ate and an output,
an eleventh transfer gate (1040) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said output of said fifth inverter and an output,
a sixth inverter having an input connected to said output of said first transfer gate and said output of said second transfer gate and an output,
a twelfth transfer gate (1042) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said output of said sixth inverter and an output,
a thirteenth transfer gate (1044) having a first control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, a second control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, an input connected to said output of said sixth inverter and an output,
a fourteenth transfer gate (1046) having a first control input connected to said output of said seventh transfer gate and said output of said eighth transfer gate, a second control input connected to said output of said fifth transfer gate and said output of said sixth transfer gate, an input connected to said output of said fifth inverter and an output,
a seventh inverter having an input connected to said output of said ninth transfer gate and to said output of said tenth transfer gate and an output connected to said second carry output terminal,
a fifteenth transfer gate (1048) having a first control input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate, a second control input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate, an input connected to said carry input terminal and an output,
a sixteenth transfer gate (1050) having a first control input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate, a second control input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate, an input connected to said output of said first inverter and an output,
an eighth inverter (1108) having an input connected to said output of said eleventh transfer gate and said output of said twelfth transfer gate and an output,
a ninth inverter (1110) having an input connected to said output of said thirteenth transfer gate and said output of said fourteenth transfer gate and an output,
a seventeenth transfer gate (1052) having a first control input connected to said output of said eighth inverter, a second control input connected to said output of said ninth inverter, an input connected to said carry input terminal and an output,
an N-channel field effect transistor having a gate connected to said output of said eighth inverter and a source-drain path connected between said output of said eighth inverter and said output of said seventeenth transfer gate,
a P-channel field effect transistor having a gate connected to said output of said ninth inverter and a source-drain path connected between said output of said ninth inverter and said output of said seventeenth transfer gate,
a tenth inverter (1052) having an input connected to said output of said fifteenth transfer gate and said output of said sixteenth transfer gate and an output connected to said first carry output terminal, and
an eleventh inverter (1062) having an input connected to said output of said seventeenth transfer gate and an output connected to said summation output terminal; each 4-2 compressor circuit forming the following logical operations:
So=((Bi\u2295Ci)\u2295(Di\u2295Ai))\u2295{overscore (Xi)};
Co=((Bi\u2295Ci)\u2295(Di\u2295Ai))\xb7{overscore (Xi)}+{overscore (((Bi\u2295Ci)\u2295(Di\u2295Ai)))}{overscore (((Bi\u2295Ci)\u2295(Di\u2295Ai)))}\xb7Ai; and
Xo=(Bi\u2295Ci)\xb7{overscore (Di)}+{overscore ((Bi\u2295Ci))}\xb7{overscore (Bi)};
a carry look ahead adder (108) receiving outputs from a last layer of 4-2 compressor circuits (104m), forming a product as a final sum.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An effort-saving paper punch which comprises
a base with a plurality of punching holes disposed towards a punching end;
a plurality of spring-loaded punching members disposed corresponding to the plurality of punching holes;
a pair of vertical supports mounted on the base;
a lever pivotably connected to the pair of vertical supports by means of a lever pivot to pivot between a resting position and a punching position, and the lever pivot is fixed in position in relation to the lever;
characterized in that:
a lever pivot slot is provided at each of the vertical supports for receiving the lever pivot in a way which enables the lever pivot to move towards the punching end in the resting position and away from the punching end in the punching position;
a longitudinal contact member is fixedly disposed underneath the lever at a position corresponding to the punching members so that a first end of the longitudinal contact member which is farther away from the punching end abuts against the punching members in the resting position; and as the lever pivots from the resting position to the punching position, the first end of the longitudinal contact member moves farther away from the punching end until a second end of the longitudinal contact member which is nearer to the punching end abuts against the punching members in the punching position.
2. The effort-saving paper punch as in claim 1, characterized in that the longitudinal contact member is in form of a U-shaped depression on the lever.
3. The effort-saving paper punch as in claim 1, characterized in that the longitudinal contact surface is in form of a U-shaped bracket mounted underneath the lever.
4. The effort-saving paper punch as in claim 1, characterized in that the longitudinal contact member is in form of an integral element with its lateral length sufficient to cover all punching members.
5. The effort-saving paper punch as in claim 1, characterized in that the longitudinal contact member is in form of separate elements, each of which has a lateral length sufficient to cover one of the punching members.
6. The effort-saving paper punch as in claim 1, characterized in that the lever slot is slanted with its lower end disposed nearer the punching end of the paper punch and its upper end disposed farther from the punching end of the paper punch.
7. The effort-saving paper punch as in claim 1, characterized in that each of the punching members is horizontally adjustable in position.
8. The effort-saving paper punch as in claim 1, characterized in that each of the punching members comprises a spring-loaded punch, a bracket for receiving the punch and allowing the punch to move vertically for punching, and a fastening member removably attached to the bracket and slidable along a horizontal guiding slot provided on a guiding plate mounted on the base for moving the punching member along the horizontal guiding slot; the punching holes on the base are configured correspondingly to allow the punching members to punch at any possible positions.
9. The effort-saving paper punch as in claim 8, characterized in that the fastening member is in form of a screw.
10. The effort-saving paper punch as in claim 8, characterized in that the guiding plate is provided with dimensional markers to indicate corresponding punching positions.
11. The effort-saving paper punch as in claim 1, characterized in that three punching members are provided; the punching member in middle is horizontally slidable between an operational position and a non-operational position; the longitudinal contact member is configured to abut against the punching member in middle when the punching member in middle is in the operational position, and not to abut against the punching member in middle when the punching member in middle is in the non-operational position.

1. A computer-implemented image processing method, comprising:
receiving, using at least one processing circuit, a plurality of image frames of a video;
constructing, using at least one processing circuit, a plurality of statistical models of the plurality of image frames at a plurality of pixel granularity levels;
constructing, using at least one processing circuit, a plurality of probabilistic models of an input image frame at a plurality of channel granularity levels based on the plurality of statistical models;
merging at least some of the plurality of probabilistic models based on a weighted average to form a single probability image; and
determining background pixels, based on a probability threshold value, from the single probability image, wherein the plurality of statistical models comprise spatio-temporal (S-T) histogram for each of the pixels from the plurality of image frames, wherein a horizontal axis of the S-T histogram represents channel value bins, and wherein a vertical axis of the S-T histogram represents counts of image frames per bin.
2. The method of claim 1, wherein the plurality of probabilistic models comprise:
a probability image from each of the S-T histogram, wherein each of the probability images comprises a plurality of pixels each indicating a probability of a corresponding pixel in the input image being a background pixel; and
compact probability images from the probability images.
3. The method of claim 2, wherein the compact probability images are obtained from one of a mean, a median, or a minimum operation over the probability images.
4. The method of claim 2, wherein the compact probability images include:
a compact S-T probability image;
a compact aggregate background probability image across a first-order approximation of a background region; and
a compact aggregate foreground probability image across a first-order approximation of a foreground region,
wherein the compact S-T probability image is given a higher weight in the weighted average.
5. The method of claim 1, wherein the weighted average gives a higher weight to the probabilistic models at a lower pixel granularity level.
6. The method of claim 1, further comprising:
subsampling pixels in the single probability image,
wherein the background pixels are determined from the subsampled single probability image.
7. The method of claim 1, further comprising automatically replacing the determined background pixels with desired pixel values.
8. The method of claim 1, further comprising alpha-blending the determined background pixels with foreground pixels.
9. The method of claim 1, wherein each pixel of each of the plurality of image frames has a blue channel, a green channel, a red channel, and an alpha channel.
10. The method of claim 1, wherein each pixel of each of the plurality of image frames has a blue channel, a green channel, and a red channel.
11. The method of claim 1, further comprising:
adding and subtracting image frames to the plurality of image frames; and
updating the plurality of statistical models and the plurality of probabilistic models based on the plurality of image frames with the added and subtracted image frames.
12. The method of claim 1, further comprising:
sampling one of the plurality of image frames at a probability equal to a desired statistics update frequency.
13. An image processing system comprising at least one processing circuit configured to:
receive a plurality of image frames of a video;
construct a plurality of statistical models of the plurality of image frames at a plurality of pixel granularity levels;
construct a plurality of probabilistic models of an input image frame at a plurality of channel granularity levels based on the plurality of statistical models;
merge at least some of the plurality of probabilistic models based on a weighted average to form a single probability image; and
determine background pixels, based on a probability threshold value, from the single probability image wherein the plurality of statistical models comprise spatio-temporal (S-T) histogram for each of the pixels from the plurality of image frames, wherein a horizontal axis of the S-T histogram represents channel value bins, and wherein a vertical axis of the S-T histogram represents counts of image frames per bin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of providing communication circuit status information via a network interface session, wherein the method comprises:
receiving a status report request from a network service provider technician;
determining a network service provider for whom the technician requesting the status report works;
the status report request identifying at least one communication circuit identifier for which the network service provider technician request status;
determining an entity operating the at least one communication circuit;
comparing the entity to the network service provider;
terminating access to the communications circuit status information if the entity is not the network service provider;
communicating the at least one communication circuit identifier to a circuit database server;
receiving a circuit verification for each at least one communication circuit identifier;
communicating the status report to the circuit database server;
receiving circuit status information from the circuit database server;
creating a status report comprising the circuit status information; and
transmitting the status report to a follow-on system.
2. The method of claim 1, further comprising receiving technician identification parameters.
3. The method of claim 2, further comprising communicating the technician identification parameters to a technician authorization database.
4. The method of claim 3, further comprising receiving a technician access authorization from the technician authorization database.
5. The method of claim 1, wherein the status report comprises an installation date for the at least one communication circuit identifier.
6. The method of claim 1, wherein the follow-on system comprises a remotely located computer for display of said status report.
7. The method of claim 1, wherein the follow-on system comprises a storage system.
8. The method of claim 1 wherein the follow-on system comprises an email system.
9. The method of claim 1, wherein the circuit verification comprises a circuit existence identifier and circuit ownership identifier value pair.