Author: claimsbot

1. A driver device to drive light emission elements arranged in a branch connection to a common terminal, comprising:
a scan-circuit portion including scan circuits that are connected to one another in a cascade manner and include output terminals connected to the light emission elements on a one-to-one basis, wherein a first-clock terminal, from which to output a first clock signal, is connected to odd-numbered scan circuits, and a second-clock terminal, from which to output a second clock signal, is connected to even-numbered scan circuits, and wherein the scan circuit portion is configured to scan and drive the light emission elements sequentially from a first scan circuit to a last scan circuit once the second-clock signal is applied to the first scan circuit;
a data-drive portion configured to drive the common terminal;
a clock-driver circuit including a first output terminal from which to output a first-clock pulse, a second output terminal from which to output a second-clock pulse that is different in phase from the first-clock pulse, and a third output terminal from which to output a third-clock pulse synchronized with the first-clock pulse and the second-clock pulse; and
a waveform-shaper circuit including a first resister connected between a node and a point between the first output terminal and the first-clock terminal, a second resistor connected between the node and a point between the second output terminal and the second-clock terminal, a capacitor connected between the third output terminal and the node, the waveform-shaper circuit configured to re-shape a waveform of the first clock signal to be outputted to the first-clock terminal and a waveform of the second clock signal to be outputted to the second-clock terminal.
2. The driver device according to claim 1, wherein in the scan-circuit portion,
each of the odd-numbered scan circuits includes a three-terminal switch element having a first terminal connected to a first power source, a second terminal connected to the first-clock terminal, and a control terminal connected to a corresponding one of the odd-numbered light emission elements and configured to control an ONOFF state between the first terminal and the second terminal in the odd-numbered scan circuit, and
each of the even-numbered scan circuits includes a three-terminal switch element having a first terminal connected to the first power source, a second terminal connected to the second-clock terminal, and a control terminal connected to a corresponding one of the even-numbered light emission elements and configured to control an ONOFF state between the first terminal and the second terminal in the even-numbered scan circuit.
3. The driver device according to claim 2, wherein
the control terminal of the three-terminal switch element in the first scan circuit is connected to the second-clock terminal via an opposite-direction diode, and
the control terminal of the three-terminal switch element of each scan circuit is connected respectively to the control terminal of the three-terminal switch element of a sequentially next scan circuit via a forward-direction diode.
4. The driver device according to claim 3, wherein the control terminal of the three-terminal switch element in each scan circuit is connected, via a resister, to a second power source with a potential different from a potential of the first power source.
5. The driver device according to claim 4, wherein
the first power source is configured to supply a source voltage,
the second power source is at a ground potential, and
the clock-driver circuit includes
a first three-state-type output buffer configured to output the first-clock pulse through the first output terminal,
a second three-state-type output buffer configured to output the second-clock pulse through the second output terminal, and
a third three-state-type output buffer configured to output the third-clock pulse through the third output terminal.
6. The driver device according to claim 2, wherein the three-terminal switch element includes a thyristor.
7. The driver device according to claim 1, wherein the light emission elements include three-terminal light emission elements.
8. The driver device according to claim 7 wherein the three-terminal light emission elements are light emission thyristors.
9. A print head comprising:
the light emission elements according to claim 1; and
the driver device according to claim 1.
10. An image formation apparatus comprising the print head according to claim 9 configured to emit light to form a letent image on an image carrier.
11. A driver device to drive main light emission portions each including light emission elements arranged in a branching connection to a common terminal, comprising:
scan-circuit portions each including scan circuits that are connected to one another in a cascade manner and include output terminals connected to the light emission elements on a one-to-one basis, wherein a first-clock terminal, from which to output a first clock signal, is connected to odd-numbered scan circuits in each scan portion, and a second-clock terminal, from which to output a second clock signal, connected to even-numbered scan circuits in each scan portion, wherein each scan-circuit portion is configured to scan and drive the light emission elements sequentially from a first scan circuit to a last scan circuit once the second-clock signal is applied to the first scan circuit; and
data-drive portions wherein each data-drive portion is configured to drive the common terminal of a corresponding scan-circuit portion;
a clock-driver circuit including first output terminals from which to output first-clock pulses, second output terminals from which to output second-clock pulses that are different in phase from the first-clock pulses, and a third output terminal from which to output a third-clock pulse synchronized with the first-clock pulses and the second-clock pulses; and
a waveform-shaper circuit including first resisters each connected between a corresponding node and a point between the corresponding first output terminal and the corresponding first-clock terminal, second resisters each connected between the corresponding node and a point between the corresponding second output terminal and the corresponding second-clock terminal, capacitors each connected between the corresponding third output terminal and the corresponding node, wherein the waveform-shaper circuit is configured to re-shape waveforms of the first clock signals to be outputted to the first-clock terminals and waveforms of the second clock signals to be outputted to the second-clock terminals.
12. The driver device according to claim 11, wherein in the scan-circuit portion,
each of the odd-numbered scan circuits includes a three-terminal switch element having a first terminal connected to a first power source, a second terminal connected to the first-clock terminal, and a control terminal connected to a corresponding one of the odd-numbered light emission elements and configured to control an ONOFF state between the first terminal and the second terminal in the odd-numbered scan circuit, and
each of the even-numbered scan circuits includes a three-terminal switch element having a first terminal connected to the first power source, a second terminal connected to the second-clock terminal, and a control terminal connected to a corresponding one of the even-numbered light emission elements and configured to control an ONOFF state between the first terminal and the second terminal in the even-numbered scan circuit.
13. The driver device according to claim 12, wherein
the control terminal of the three-terminal switch element in the first scan circuit is connected to the second-clock terminal via an opposite-direction diode, and
the control terminal of the three-terminal switch element of each scan circuit is connected to the control terminal of the three-terminal switch element of a sequentially next scan circuit via a forward-direction diode.
14. The driver device according to claim 13, wherein the control terminal of the three-terminal switch element in each scan circuit is connected, via a resister, to a second power source with a potential different from a potential of the first power source.
15. The driver device according to claim 14 wherein
the first power source is configured to supply a source voltage,
the second power source is at a ground potential, and
the clock-driver circuit includes
a first three-state-type output buffer configured to output the first-clock pulse through the first output terminal,
a second three-state-type output buffer configured to output the second-clock pulse through the second output terminal, and
a third three-state-type output buffer configured to output the third-clock pulse through the third output terminal.
16. The driver device according to claim 12, wherein the three-terminal switch element includes a thyristor.
17. The driver device according to claim 11, wherein the light emission elements include three-terminal light emission elements.
18. The driver device according to claim 17 wherein the three-terminal light emission elements are light emission thyristors.
19. A print head comprising:
the main light emission portions according to claim 11; and
the driver device according to claim 11.
20. An image formation apparatus comprising the print head according to claim 19 configured to emit light to form a letent image on an image carrier.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for implementing a graphic user interface for an electronic device, comprising the steps of:
a) rendering an image of a graphical user interface on a display screen, said graphical user interface comprising a first display for displaying an application and a second display for displaying a status bar, wherein said first display region and said second display region are displayed concurrently;
b) receiving input comprising information relating to an event, wherein said event is unrelated to said application in operation in said first display of said graphical user interface;
c) displaying an indication of said information in said status bar of said graphic user interface and also in response to said event displaying a graphical interface tool in said status bar that provides to a user a selection with respect to said event; and,
d) taking an action with respect to said event, wherein said action is responsive to said selection from said user, said selection comprising a command related to the disposition of said event;

wherein steps a)-d) are performed while said application is operating and without interfering with said other application.
2. A method as described in claim 1 wherein said portable electronic device is enabled as a portable telephone device.
3. A method as described in claim 1 wherein said event is an incoming telephone call.
4. A method as described in claim 1 wherein said information related to said event is caller identification information.
5. A method as described in claim 1 wherein said input from said user, comprising a command, is an instruction to answer an incoming telephone call.
6. A method as described in claim 1 wherein said input from said user, comprising a command, is an instruction to reject an incoming telephone call.
7. A method as described in claim 1 wherein said input from said user, comprising a command, is entered by selection of a graphic selection tool in said graphic user interface.
8. A method as described in claim 1 wherein said action responsive to said event is capable of execution without disturbing said application, wherein said application is displaying information on said portable computer system.
9. A method as described in claim 1 wherein said graphic user interface is implemented in a touch-screen display.
10. A method for implementing a graphic user interface for a portable telephone device, comprising the steps of:
a) rendering an image of a graphical user interface on a display screen, said graphical user interface comprising a first display region for displaying an application in operation and a second display region for displaying a status bar, wherein said first display region and said second display region are displayed concurrently;
b) receiving input comprising information relating to an incoming telephone call;
c) displaying an indication of said information in said status bar of said graphic user interface and also in response to said incoming telephone call displaying a graphical interface tool in said status bar that provides to a user a selection with respect to said call;
d) responsive to a selection from said user, said selection comprising a command related to the disposition of said incoming telephone call, taking an action with respect to said telephone call; and,

wherein steps a)-d) are performed while said application is operating and without interfering with said other application.
11. A method as described in claim 10 wherein said information related to said incoming telephone call is caller identification information.
12. A method as described in claim 10 wherein said input from said user, comprising a command, is an instruction to answer said incoming telephone call.
13. A method as described in claim 10 wherein said input from said user, comprising a command, is an instruction to reject said incoming telephone call.
14. A method as described in claim 10 wherein said input from said user, comprising a command, is entered by selection of a graphic selection tool in said graphic user interface.
15. A method as described in claim 10 wherein said action responsive to said incoming telephone call is capable of execution without disturbing said application, wherein said application is displaying information on said portable computer system.
16. A method as described in claim 10 wherein said graphic user interface is implemented in a touch-screen display.

What is claimed is:

1. A method for thickness estimation of a conductive top layer of a substrate sample, said method comprising:
(a) receiving said substrate sample after said substrate sample has undergone a top layer removal process removing a portion of said conductive top layer of said substrate sample;
(b) obtaining initial resistance and reactance measurements from said substrate sample using an eddy current probe positioned at an initial distance relative to said substrate sample;
(c) obtaining terminating resistance and reactance measurements from said substrate sample using said eddy current probe positioned at a modified distance relative to said substrate sample;
(d) calculating an intersecting line using said initial and terminating resistance and reactance measurements;
(e) determining an intersecting point between a previously defined natural intercepting curve and said intersecting line, wherein said natural intercepting curve is defined by a plurality of initial resistance and reactance measurements obtained from at least one calibration sample individually or collectively having a known range of top layer thicknesses;
(f) locating a reactance voltage of said intersecting point along a digital calibration curve to identify a closest-two of said known range of top layer thicknesses, wherein said digital calibration curve is defined by a plurality of initial reactance measurements and corresponding top layer thicknesses of said at least one calibration sample; and
(g) estimating a thickness of said conductive top layer of said substrate sample by approximating a location of said reactance voltage relative to said closest-two of said known range of top layer thicknesses of said at least one calibration sample.
2. The method according to claim 1, said method further comprising:
scanning a plurality of locations of said substrate sample to generate a thickness profile, wherein said thickness profile is generated by performing operations (b) through (g) for each of said plurality of locations of said substrate sample; and
providing said thickness profile to a top layer removal system that is adapted to provide said top layer removal process.
3. The method according to claim 2, wherein said top layer removal system comprises a chemical-mechanical polishing (CMP) system.
4. The method according to claim 2, said method further comprising:
providing said thickness profile to a metal deposition system that is adapted to provide metal layer deposition on semiconductor wafer products.
5. The method according to claim 2, said method further comprising:
providing said thickness profile to at least one metal deposition system that is adapted to provide metal layer deposition on semiconductor wafer products, wherein said metal deposition system is a system selected from the group consisting of an electro-chemical process (ECP) system, chemical vapor deposition (CVD) system, physical vapor deposition (PVD) system, plasma enhanced CVD (PECVD) system, low pressure CVD (LPCVD) system, rapid thermal CVD (RTCVD) system, and an atmospheric pressure CVD (APCVD) system.
6. The method according to claim 1, wherein said terminating resistance and reactance measurements are obtained after increasing the relative distance between said eddy current probe and said substrate sample.
7. The method according to claim 1, wherein said terminating resistance reactance measurements are obtained after decreasing the relative distance between said eddy current probe and said substrate sample.
8. The method according to claim 1, wherein said approximating is accomplished by performing an interpolation between said closest-two of said known range of top layer thicknesses of said at least one calibration sample.
9. The method according to claim 1, wherein said approximating is accomplished by curve-fitting said reactance voltage to said digital calibration curve.
10. The method according to claim 1, wherein said initial and modified distances relative to said substrate are obtained using a proximity sensor selected from the group consisting of a capacitance sensor, optical laser, Hall effect sensor, thermal IR sensor, and an ultrasound sensor.
11. The method according to claim 1, wherein said at least one calibration sample includes a top layer of a different conductance than said conductive top layer of said substrate sample.
12. A system for thickness estimation of a conductive top layer of a substrate sample, said system comprising:
an eddy current probe comprising an eddy current sense coil;
a controller providing relative motion between said eddy current probe and said substrate sample;
a processor for processing measurements detected by said eddy current sense coil, wherein said processor is configured to estimate a thickness of said conductive top layer of said substrate sample by a method comprising:
(a) receiving said substrate sample after said substrate sample has undergone a top layer removal process removing a portion of said conductive top layer of said substrate sample;
(b) obtaining initial resistance and reactance measurements from said substrate sample using an eddy current probe positioned at an initial distance relative to said substrate sample;
(c) obtaining terminating resistance and reactance measurements from said substrate sample using said eddy current probe positioned at a modified distance relative to said substrate sample;
(d) calculating an intersecting line using said initial and terminating resistance and reactance measurements;
(e) determining an intersecting point between a previously defined natural intercepting curve and said intersecting line, wherein said natural intercepting curve is defined by a plurality of initial resistance and reactance measurements obtained from at least one calibration sample individually or collectively having a known range of top layer thicknesses;
(f) locating a reactance voltage of said intersecting point along a digital calibration curve to identify a closest-two of said known range of top layer thicknesses, wherein said digital calibration curve is defined by a plurality of initial reactance measurements and corresponding top layer thicknesses of said at least one calibration sample; and
(g) estimating a thickness of said conductive top layer of said substrate sample by approximating a location of said reactance voltage relative to said closest-two of said known range of top layer thicknesses of said at least one calibration sample.
13. The system according to claim 12, wherein a plurality of locations of said substrate sample are scanned to generate a thickness profile, wherein said thickness profile is generated by performing operations (b) through (g) for each of said plurality of locations of said substrate sample, and wherein said thickness profile is communicated to a top layer removal system that is adapted to provide said top layer removal process.
14. The system according to claim 13, wherein said top layer removal system comprises a chemical-mechanical polishing (CMP) system.
15. The system according to claim 13, wherein said thickness profile is communicated to a metal deposition system that is adapted to provide metal layer deposition on semiconductor wafer products.
16. The system according to claim 13, wherein said thickness profile is communicated to at least one metal deposition system that is adapted to provide metal layer deposition on semiconductor wafer products, wherein said metal deposition system is a system selected from the group consisting of an electro-chemical process (ECP) system, chemical vapor deposition (CVD) system, physical vapor deposition (PVD) system, plasma enhanced CVD (PECVD) system, low pressure CVD (LPCVD) system, rapid thermal CVD (RTCVD) system, and an atmospheric pressure CVD (APCVD) system.
17. The system according to claim 12, wherein said terminating resistance and reactance measurements are obtained after increasing the relative distance between said eddy current probe and said substrate sample.
18. The system according to claim 12, wherein said terminating resistance reactance measurements are obtained after decreasing the relative distance between said eddy current probe and said substrate sample.
19. The system according to claim 12, wherein said approximating is accomplished by performing an interpolation between said closest-two of said known range of top layer thicknesses of said at least one calibration sample.
20. The system according to claim 12, wherein said approximating is accomplished by curve-fitting said reactance voltage to said digital calibration curve.
21. The system according to claim 12, wherein said initial and modified distances relative to said substrate are obtained using a proximity sensor selected from the group consisting of a capacitance sensor, optical laser, Hall effect sensor, thermal IR sensor, and an ultrasound sensor.
22. The system according to claim 12, wherein said at least one calibration sample includes a top layer of a different conductance than said conductive top layer of said substrate sample.
23. A method for thickness estimation of a conductive top layer of a substrate sample, said method comprising:
(a) receiving said substrate sample after said substrate sample has undergone a top layer removal process removing a portion of said conductive top layer of said substrate sample;
(b) means for obtaining initial resistance and reactance measurements from said substrate sample using an eddy current probe positioned at an initial distance relative to said substrate sample;
(c) means for obtaining terminating resistance and reactance measurements from said substrate sample using said eddy current probe positioned at a modified distance relative to said substrate sample;
(d) means for calculating an intersecting line using said initial and terminating resistance and reactance measurements;
(e) means for determining an intersecting point between a previously defined natural intercepting curve and said intersecting line, wherein said natural intercepting curve is defined by a plurality of initial resistance and reactance measurements obtained from at least one calibration sample individually or collectively having a known range of top layer thicknesses;
(f) means for locating a reactance voltage of said intersecting point along a digital calibration curve to identify a closest-two of said known range of top layer thicknesses, wherein said digital calibration curve is defined by a plurality of initial reactance measurements and corresponding top layer thicknesses of said at least one calibration sample; and
(g) means for estimating a thickness of said conductive top layer of said substrate sample by approximating a location of said reactance voltage relative to said closest-two of said known range of top layer thicknesses of said at least one calibration sample.
24. A monitoring system providing a thickness profile of a conductive top layer of a substrate sample, said system comprising:
an eddy current probe support;
a plurality of eddy current probes comprising separate eddy current sense coils, wherein said plurality of eddy current probes are configured with said eddy current probe support;
a controller configured with said eddy current probe support providing relative motion between each of said plurality of said eddy current probes and said substrate sample;
a processor for processing measurements detected by each of said plurality of eddy current sense coils, wherein said processor is configured to estimate a thickness profile of said conductive top layer of said substrate sample by a method comprising:
(a) receiving said substrate sample after said substrate sample has undergone a top layer removal process removing a portion of said conductive top layer of said substrate sample;
(b) obtaining initial resistance and reactance measurements from said substrate sample using one of said plurality of eddy current probes positioned at an initial distance relative to said substrate sample;
(c) obtaining terminating resistance and reactance measurements from said substrate sample using said one of said plurality of eddy current probes positioned at a modified distance relative to said substrate sample;
(d) calculating an intersecting line using said initial and terminating resistance and reactance measurements;
(e) determining an intersecting point between a previously defined natural intercepting curve and said intersecting line, wherein said natural intercepting curve is defined by a plurality of initial resistance and reactance measurements obtained from at least one calibration sample individually or collectively having a known range of top layer thicknesses;
(f) locating a reactance voltage of said intersecting point along a digital calibration curve to identify a closest-two of said known range of top layer thicknesses, wherein said digital calibration curve is defined by a plurality of initial reactance measurements and corresponding top layer thicknesses of said at least one calibration sample;
(g) estimating a thickness of said conductive top layer of said substrate sample by approximating a location of said reactance voltage relative to said closest-two of said known range of top layer thicknesses of said at least one calibration sample; and
(h) estimating said thickness profile of said conductive top layer of said substrate sample by repeating operations (b) through (g) for each of said plurality of eddy current probes.
25. The system according to claim 24, wherein said top layer removal process is provided by a chemical-mechanical polishing (CMP) system.
26. The system according to claim 25, wherein said monitoring system is integrated with said chemical-mechanical polishing (CMP) system.
27. The system according to claim 24, wherein said controller rotates said eddy current probe support over said substrate to scan a plurality of locations of said substrate, and wherein an enhanced thickness profile is generated by performing operations (b) through (h) for each of said plurality of locations of said substrate sample.
28. The system according to claim 24, wherein said controller linearly translates said eddy current probe support over said substrate sample to scan a plurality of locations of said substrate sample, and wherein an enhanced thickness profile is generated by performing operations (b) through (h) for each of said plurality of locations of said substrate sample.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-8. (canceled)
9. A plasma doping method comprising the steps of:
placing a sample on a sample electrode in a vacuum chamber;
flowing a gas substantially isotropically toward the sample from a surface opposed to the sample while discharging the gas in the vacuum chamber;
generating a plasma in the vacuum chamber while controlling the vacuum chamber to be under a predetermined pressure; and
introducing impurity ions into a surface of the sample by allowing the impurity ions in the plasma to collide with the surface of the sample,
wherein a mass flow of gas flown toward a center portion of the sample and a mass flow of gas flown toward the outside of the sample in a surface on which the sample is placed are controlled by individual mass flow control systems, and
wherein a concentration of impurity material gas included in the gas flown toward the center portion of the sample is less than that of impurity material gas included in the gas flown toward the outside of the sample in the surface on which the sample is placed.
10. The plasma doping method according to claim 9, wherein the mass flow of impurity material gas included in the gas flown toward the center portion of the sample is a half or less than that of impurity material gas included in the gas flown toward the peripheral portion of the sample.
11. The plasma doping method according to claim 9, wherein plasmas are generated in the vacuum chamber by the supply of high-frequency power to a plasma source.
12. The plasma doping method according to claim 9, wherein the sample is a semiconductor substrate made of silicon.
13. The plasma doping method according to claim 9, wherein the impurity is arsenic, phosphorous, boron, or antimony.
14-24. (canceled)