Author: claimsbot

1. A method for forming an interconnect comprising:
selecting an insulative surface;
selecting a number of metallization stack layers having a critical thickness;
etching a trench on the insulative surface, the trench having a depth greater than the critical thickness and a width less than a sidewall thickness of a first metallization stack, and the trench coupling a first memory cell to a second memory cell;
etching a second trench on the insulative surface, the second trench having a depth greater than the critical thickness and a width greater than the sidewall thickness and less than a second sidewall thickness of a second metallization stack;
depositing the first metal layer;
depositing the second metal layer; and
planarizing the insulative surface.
2. The method of claim 1, wherein depositing a first metal comprises depositing copper.
3. The method of claim 1, wherein planarizing the insulative surface comprises planarizing by chemical mechanical polishing.
4. A method for dimensioning a trench comprising:
selecting a number of layers, the number of layers having a sidewall thickness;
selecting a second number of layers having a second sidewall thickness, wherein the second number of layers has one less metal layer than the number of layers;
identifying a critical depth; and
dimensioning the trench to have a depth greater than the critical depth and a width less than the sidewall thickness but greater than the second sidewall thickness.
5. The method of claim 4, wherein identifying a critical depth comprises:
calculating a total bottom thickness for one less layer than the number of layers, the total bottom thickness being the critical depth.
6. A method of forming a conductive structure comprising:
etching a trench having a depth greater than a critical depth in a substrate having a surface;
under filling the trench with a first conductive material;
overfilling the trench with a second conductive material suitable for high reliability wire-bonding; and
polishing the substrate until the first conductive material and the second conductive material are removed from the surface of the substrate.
7. The method of claim 6, wherein polishing the substrate until the first conductive material and the second conductive material are removed from the surface of the substrate comprises:
applying chemical mechanical polishing to remove the first conductive material and the second conductive material from the surface of the substrate.
8. A method of forming a conductive structure comprising:
etching a fine line trench to a depth greater than a critical depth in a substrate having a surface;
etching a wide line trench to the depth in the substrate such that the wide line trench intersects the fine line trench;
filling the fine line trench with a first conductive material;
under filling the wide line trench with the first conductive material;
filling the wide line trench with a second conductive material suitable for high reliability wire-bonding; and
polishing the substrate until the first conductive material and the second conductive material are removed from the surface of the substrate.
9. The method of claim 8, wherein filling the fine line trench with a first conductive material comprises:
overfilling the fine line trench with a first conductive material.
10. The method of claim 8, wherein filling the wide line trench with a second conductive material suitable for high reliability wire-bonding comprises:
under filling the wide line trench with a second conductive material suitable for high reliability wire-bonding.
11. A method of forming a conductive structure comprising:
etching a wide line trench having a depth greater than a critical depth in the substrate;
depositing a seed layer above the surface of the substrate;
depositing a layer of conductive material above the seed layer such that the conductive material under fills the wide line trench;
depositing a barrier layer above the layer of conductive material;
depositing a second layer of conductive material above the barrier layer, the second layer of conductive material is capable of reliably wire bonding to a gold wire; and
removing the seed layer, the layer of conductive material, the barrier layer, and the second layer of conductive material from the surface of the substrate.
12. The method of claim 11, wherein depositing a layer of conductive material above the seed layer such that the conductive material under fills the wide line trench comprises:
electroplating a layer of copper above the seed layer such that the copper under fills the wide line trench.
13. The method of claim 11, wherein depositing a second layer of conductive material above the barrier layer, the second layer of conductive material is capable of reliably wire bonding to a gold wire comprises:
depositing a layer of aluminum above the barrier layer, the aluminum layer is capable of reliably wire bonding to a gold wire.
14. A computer system comprising:
a processor;
a device coupled to the processor; and
a interconnect coupled to the device, the interconnect comprising:
a trench having a depth greater than a critical depth and a metal layer; and
a bond pad trench having a bond pad depth equal to the depth and a plurality of metal layers coupled to the metal layer.
15. The computer system of claim 14, further comprising:
a conductive wire eutectically bonded to at least one of the plurality of metal layers.
16. A computer system comprising:
a processor;
a device coupled to the processor; and
a connective structure coupled to the device, the connective structure comprising:
a trench having a depth greater than a critical depth, a barrier layer, and a copper layer above the barrier layer;
a bond pad trench having a barrier layer, the bond pad trench having a copper layer above the barrier layer, and the bond pad trench having a titanium layer above the copper layer, and an aluminum-copper layer above the titanium layer.
17. A computer system comprising:
a processor;
a device coupled to the processor; and
an interconnect coupled to the device, the interconnect comprising:
a fine line having a conductive layer; and
a wide line having a number of conductive layers, and at least one of the number of conductive layers of the wide line being coupled to the fine line.
18. The computer system of claim 17, wherein the wide line is capable of being reliably wire bonded to a conductive gold wire.
19. A computer system comprising:
a processor;
a device coupled to the processor; and
an interconnect coupled to the device, the interconnect comprising:
a fine line having a depth greater than a critical depth, a barrier layer and a layer of electroplated copper; and
a wide line having a wide line depth equal to the depth, a number of conductive layers, and at least one of the number of conductive layers coupled to the electroplated copper.
20. The computer system of claim 19, wherein at least one of the number of conductive layers is wire-bonded to a gold wire.
21. The computer system of claim 19, wherein a eutectic bond is used to wire-bond at least one of the number of conductive layers to a gold wire.
22. A computer system comprising:
a processor;
a device coupled to the processor; and
a conductive structure coupled to the device, the conductive structure comprising:
a fine line having a layer of electroplated copper; and
a wide line having a number of conductive layers, at least one of the number of conductive layers is capable of eutectic bonding to a gold wire, and the wide line is coupled to the fine line.
23. A computer system comprising:
a processor;
a device coupled to the processor; and
a connective structure coupled to the device, the connective structure comprising:
a fine line having a single layer of electroplated copper having a depth greater than a critical depth; and
a wide line having a stack of conductive layers capable of eutectic bonding to a gold wire, and the wide line coupled to the fine line and the wide line having a depth greater than a critical depth.
24. A computer system comprising:
a processor;
a device coupled to the processor; and
a conductive structure coupled to the device, the conductive structure comprising:
a fine line having a depth greater than a critical depth and a single layer of electroplated copper; and
a wide line having a wide line depth equal to the depth, and a stack comprising a barrier layer, a copper layer, and an aluminum layer capable of eutectic bonding to a conductive material, and the wide line coupled to the fine line.
25. The computer system of claim 24, wherein the barrier layer comprises a refractory metalrefractory metal nitride.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Apparatus for crushing frangible glass vials comprising:
(a) a housing having a top wall and four mutually perpendicular side walls and an open bottom;
(b) at least one vial input tube extending through the top wall to an interior of the housing; and
(c) a motor driven rotor journaled for rotation within the housing, the rotor having a pair of disks concentrically mounted thereon, each of the pair of disks including at least one inset defining a tooth edge on a peripheral surface of said disks, the inset adapted to capture a first portion of a glass vial dropped through the vial input tube with a remaining portion of the glass vial remaining residing in the vial input tube whereby the tooth edges fracture the glass vial as the rotor is driven and with the crushed glass exiting the housing through the open bottom.
2. The apparatus as in claim 1 and further including at least one motor disposed in the housing for driving the rotor.
3. The apparatus as in claim 1 and further including a pair of motors disposed in the housing for driving the rotor.
4. The apparatus in claim 3 wherein the housing further includes a pair of parallel, spaced-apart partition walls extending between front and rear ones of the four mutually perpendicular side walls, the parallel, spaced-apart partition walls supporting bearings for the journaling the rotor.
5. The apparatus as in claim 4 wherein a first of the pair of motors is disposed in the housing between one of the partition walls and a right end one of the four mutually-perpendicular side walls and the other of the pair of motors is disposed between the other of the partition walls and a left end one of the four mutually-perpendicular side walls.
6. The apparatus as in claim 2 and further including a control circuit responsive to an input signal for energizing the motor for a preset time interval.
7. The apparatus as in claim 6 wherein said input signal originates at a manually operated switch.
8. The apparatus as in claim 6 and further including a sensor disposed in the vial input tube for sensing the presence of a glass vial therein and producing the input signal.
9. The apparatus of claim 3 wherein the motor driven rotor comprises a solid, cylindrical core member contained within a tubular sleeve and the pair of disks are welded concentrically onto the tubular sleeve, with opposed ends of the cylindrical core member extending outward beyond opposed ends of the tubular sleeve and the opposed ends of the core member having a non-circular bore formed inward thereof adapted to receive a complimentary shaped drive shaft of the pair of motors.
10. Apparatus for crushing frangible glass vials, comprising:
(a) a housing having a top wall, four mutually perpendicular side walls and an open bottom;
(b) a plurality of vial input tubes extending through the top wall to an interior of the housing;
(c) a motor driven rotor journaled for rotation within the housing, the rotor having a pair of disks associated with each of vial input tubes, concentrically mounted thereon, each of the pairs of disks including at least one inset defining a tooth edge at a peripheral surface of said disks, the plurality of the pairs of disks being positioned relative to the vial input tubes such that the insets of the pairs of disks are adapted to capture a first portion of a glass vial dropped through an associated vial input tube with a remaining portion of the glass vial residing in the associated vial input tube, whereby the tooth edges fracture the glass vial as the rotor is driven and with the crushed glass exiting the housing through the open bottom.
11. The apparatus as in claim 10 and further including at least one motor disposed in the housing for driving the rotor.
12. The apparatus as in claim 10 and further including a pair of motors disposed in the housing for driving the rotor.
13. The apparatus in claim 12 wherein the housing further includes a pair of parallel, spaced-apart partition walls extending between front and rear ones of the four mutually perpendicular side walls, the parallel, spaced-apart partition walls supporting bearings for the journaling the rotor.
14. The apparatus as in claim 13 wherein a first of the pair of motors is disposed in the housing between one of the partition walls and a right end one of the four mutually-perpendicular side walls and the other of the pair of motors is disposed between the other of the partition walls and a left end one of the four mutually-perpendicular side walls.
15. (canceled)
16. The apparatus as in claim 12 and further including a control circuit responsive to an input signal for energizing the motor for a predetermined time interval.
17. The apparatus as in claim 15 wherein said input signal originates at a manually operated switch.
18. The apparatus as in claim 15 and further including a sensor disposed in the vial input tube for sensing the presence of a glass vial therein and producing the input signal.
19. The apparatus as in claim 10 wherein the plurality of vial input tubes are of a differing internal diameter.
20. The apparatus as in claim 19 and further including an elastomeric cap having a self-closing slit as a cover on an upper end of the vial input tubes.
21. The apparatus of claim 12 wherein the motor driven rotor comprises a solid, cylindrical core member contained within a tubular sleeve and the pair of disks are welded concentrically onto the tubular sleeve, with opposed ends of the cylindrical core member extending outward beyond opposed ends of the tubular sleeve and the opposed ends of the core member having a non-circular bore formed inward thereof adapted to receive a complimentary shaped drive shaft of the pair of motors.

1. A support coupled to a computer peripheral device, comprising:
a first frame:
a second frame having a first end and a second end, said second frame pivotally coupled to the first frame at said first end; and
a movable arm extending from the second frame at the second end, said movable arm being linearly movable relative to the second frame;
wherein the second frame has an extension at the second end for holding an object between the extension and the first frame; and the computer peripheral device is coupled to an end of the movable arm.
2. The support as claimed in claim 1, wherein the computer peripheral device is pivotally coupled to the movable arm.
3. The support as claimed in claim 2, wherein a retaining unit is located between the computer peripheral device and the movable arm for maintaining a relative angular position between the computer peripheral device and the movable arm.
4. The support as claimed in claim 3, wherein the retaining unit is a gasket.
5. The support as claimed in claim 1, wherein an axle and retaining unit are located between the first frame and second frame, the axle pivotally coupling the first frame to the second frame and the retaining unit maintaining a relative position between the first and second frames.
6. The support as claimed in claim 5, wherein the retaining unit is a gasket.
7. The support as claimed in claim 1, wherein a retaining unit is located between the movable arm and the second frame for maintaining the moving arm at a desired position relative to the second frame when not being move by a user.
8. The support as claimed in claim 7, wherein the retaining unit is a gasket.
9. The support as claimed in claim 1, wherein the movable arm has at least a protrusion which is captured within the second frame to movably retaining the moving arm within the second frame; and the second frame further has an opening for accommodating the movable arm.
10. The support as claimed in claim 9, wherein the protrusion is received within a recess of the second frame.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of comparing a first already-compiled programming file for a first programmable logic device to a second already-compiled programming file for a second programmable logic device different from said first programmable logic device, said method comprising:
identifying, in said first already-compiled programming file, a representation of one or more functional features of said first programmable logic device, and identifying, in said second already-compiled programming file, a representation of one or more functional features of said second programmable logic device, said second programmable logic device being different from said first programmable logic device;
establishing correspondence between one or more functional features of one programmable logic device selected from said first and second programmable logic devices, represented in one programming file selected from said first and second already-compiled programming files, and one or more functional features of another programmable logic device, selected from said first and second programmable logic devices, represented in another programming file selected from said first and second already-compiled programming files; and
comparing each of one or more of said functional features of said one programmable logic device, selected from said first and second programmable logic devices, represented in said one programming file selected from said first and second already-compiled programming files, to a corresponding functional feature of said another programmable logic device selected from said first and second programmable logic devices represented in said another programming file selected from said first and second already-compiled programming files, said comparing comprising constructing binary description diagrams for each combinational logic block in a pair of combinational logic blocks to be compared, and comparing said binary description diagrams.
2. The method of claim 1 wherein said establishing correspondence comprises comparing names of functional features.
3. The method of claim 1 wherein said establishing correspondence comprises comparing locations, in said first and second programmable logic devices, of functional features.
4. The method of claim 3 wherein said comparing locations comprises comparing on-chip locations.
5. The method of claim 3 wherein said comparing locations comprises comparing package locations.
6. The method of claim 1 wherein said establishing correspondence comprises comparing connectivity of an individual functional feature of one of said one programmable logic device and said another programmable logic device selected from said first and second programmable logic devices to at least one other functional feature of said one of said one programmable logic device and said another programmable logic device selected from said first and second programmable logic devices.
7. The method of claim 6 wherein, when said at least one other functional feature comprises a plurality of said other functional features of a given type, said comparing connectivity comprises distinguishing among said plurality of said other functional features of said given type based on names of said other functional features.
8. The method of claim 1 further comprising:
identifying, in said first and second already-compiled programming files, representations of functional blocks of said first and second programmable logic devices; and
further identifying, within said representations of functional blocks, said representations of functional features and representations of additional said functional blocks.
9. The method of claim 8 comprising repeating said further identifying with respect to said representations of additional functional blocks until no said representations of additional functional blocks are identified within any of said representations of additional functional blocks.
10. The method of claim 1 wherein:
said one programming file selected from said first and second programming files is for a first type of programmable logic device; and
said another programming file selected from said first and second programming files is for a second type of programmable logic device.
11. The method of claim 10 wherein:
said first type of programmable logic device is a field-programmable gate array; and
said second type of programmable logic device is a mask-programmable logic device.
12. The method of claim 1 wherein said comparing representations of functional features comprises comparing representations of elements selected from the group consisting of functional elements, programming bits, internal parameters, and combinations thereof.
13. The method of claim 1 further comprising displaying results of said comparing.
14. The method of claim 13 wherein said displaying comprises displaying only results indicating differences.
15. The method of claim 14 wherein said displaying results indicating differences comprises displaying only differences beyond a predetermined tolerance.
16. The method of claim 1 wherein said comparing comprises recognizing register packing.
17. The method of claim 1 wherein said constructing comprises: partitioning said combinational logic block into a plurality of combinational logic cones; and constructing one said binary description diagram for each said combinational logic cone.
18. The method of claim 17 wherein said partitioning comprises partitioning between sequential comparison points.
19. The method of claim 18 comprising assigning common names to said sequential comparison points in said different programmable logic devices.
20. A programmable logic device programmed by a programming file that has been compared to another programming file in accordance with the method of claim 1.
21. A digital processing system comprising:
processing circuitry;
a memory coupled to said processing circuitry; and
a programmable logic device as defined in claim 20 coupled to the processing circuitry and the memory.
22. A printed circuit board on which is mounted a programmable logic device as defined in claim 20.
23. The printed circuit board defined in claim 22 further comprising:
memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.
24. The printed circuit board defined in claim 23 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.
25. A machine-readable data storage medium encoded with machine-executable instructions for performing a method of comparing a first already-compiled programming file for a first programmable logic device to a second already-compiled programming file for a second programmable logic device different from said first programmable logic device, said instructions comprising:
instructions for identifying, in said first already-compiled programming file, a representation of one or more functional features of said first programmable logic device, and identifying, in said second already-compiled programming file, a representation of one or more functional features of said second programmable logic device, said second programmable logic device being different from said first programmable logic device;
instructions for establishing correspondence between one or more functional features of one programmable logic device, selected from said first and second programmable logic devices, represented in one programming file selected from said first and second already-compiled programming files, and one or more functional features of another programmable logic device, selected from said first and second programmable logic devices, represented in another programming file selected from said first and second already-compiled programming files; and
instructions for comparing each of one or more of said functional features of said one programmable logic device, selected from said first and second programmable logic devices, represented in said one programming file selected from said first and second already-compiled programming files, to a corresponding functional feature of said another programmable logic device, selected from said first and second programmable logic devices, represented in said another programming file selected from said first and second already-compiled programming files, said instructions for comparing comprising instructions for constructing binary description diagrams for each combinational logic block in a pair of combinational logic blocks to be compared, and instructions for comparing said binary description diagrams.
26. The machine-readable data storage medium of claim 25 wherein said instructions for establishing correspondence comprise instructions for comparing names of functional features.
27. The machine-readable data storage medium of claim 25 wherein said instructions for establishing correspondence comprise instructions for comparing locations of functional features.
28. The machine-readable data storage medium of claim 27 wherein said instructions for comparing locations comprise instructions for comparing on-chip locations.
29. The machine-readable data storage medium of claim 27 wherein said instructions for comparing locations comprise instructions for comparing package locations.
30. The machine-readable data storage medium of claim 25 wherein said instructions for establishing correspondence comprise instructions for comparing connectivity of an individual functional feature of one of said one programmable logic device and said another programmable logic device selected from said first and second programmable logic devices to at least one other functional feature of said one of said one programmable logic device and said another programmable logic device selected from said first and second programmable logic devices.
31. The machine-readable data storage medium of claim 30 wherein said instructions for comparing connectivity comprise instructions for, when said at least one other functional feature comprises a plurality of said other functional features of a given type, distinguishing among said plurality of said other functional features of said given type based on names of said other functional features.
32. The machine-readable data storage medium of claim 25 wherein said instructions further comprise:
instructions for identifying, in said first and second already-compiled programming files, representations of functional blocks of said first and second programmable logic devices; and
instructions for further identifying, within said representations of functional blocks, said representations of functional features and representations of additional said functional blocks.
33. The machine-readable data storage medium of claim 32 wherein said instructions comprise repeating said further identifying with respect to said representations of additional functional blocks until no said representations of additional functional blocks are identified within any of said representations of additional functional blocks.
34. The machine-readable data storage medium of claim 25 wherein, in said method:
said one programming file selected from said first and second programming files is for a first type of programmable logic device; and
said another programming file selected from said first and second programming files is for a second type of programmable logic device.
35. The machine-readable data storage medium of claim 34 wherein, in said method:
said first type of programmable logic device is a field-programmable gate array; and
said second type of programmable logic device is a mask-programmable logic device.
36. The machine-readable data storage medium of claim 25 wherein said instructions for comparing representations of functional features comprise instructions for comparing representations of elements selected from the group consisting of functional elements, programming bits, internal parameters, and combinations thereof.
37. The machine-readable data storage medium of claim 25 wherein said instructions further comprise instructions for displaying results of said comparing.
38. The machine-readable data storage medium of claim 37 wherein said instructions for displaying comprise instructions for displaying only results indicating differences.
39. The machine-readable data storage medium of claim 38 wherein said instructions for displaying results indicating differences comprise instructions for displaying only differences beyond a predetermined tolerance.
40. The machine-readable data storage medium of claim 25 wherein said instructions for comparing comprise instructions for recognizing register packing.
41. The machine-readable data storage medium of claim 25 wherein said instructions for constructing comprise: instructions for partitioning said combinational logic block into a plurality of combinational logic cones; and instructions for constructing one said binary description diagram for each said combinational logic cone.
42. The machine-readable data storage medium of claim 41 wherein said instructions for partitioning comprise instructions for partitioning between sequential comparison points.
43. The machine-readable data storage medium of claim 42 wherein said instructions comprise instructions for assigning common names to said sequential comparison points in said different programmable logic devices.