1. A positively buoyant wave-attenuating panel comprising a plurality of horizontally disposed pipe members fixedly coupled to each other such that the members share a common plane extending through the panel, wherein the panel is movably coupled to a seabed in a body of water with the common plane in a vertical orientation, the panel being configured to rise and fall along the common plane in response to changes in tide or water level elevation, and wherein the pipe members are pre-loaded in compression in a direction perpendicular to the length of the pipe members, wherein the pipe members having hollow interiors having respective central longitudinal axes extending lengthwise of the pipe members, the panel further comprising a plurality of tensioning rods extending through the interiors of the pipe members in the direction perpendicular to the length of the pipe members, the tensioning rods being placed in tension to place the pipe members in compression, wherein the tensioning rods intersect the central longitudinal axes of the interiors of the pipe members.
2. The panel of claim 1, wherein the panel defines a panel thickness and a draft, and wherein the draft is substantially greater than the panel thickness.
3. The panel of claim 1, wherein the pipe members are placed in compression against each other such that there are substantially no gaps between adjacent pipe members.
4. The panel of claim 1, wherein one or more of the hollow interiors are filled with an open-cell foam, a closed-cell foam, or both an open-cell foam and a closed-cell foam.
5. The panel of claim 1, wherein the panel defines two opposed outwardly facing faces and the tensioning rods extend through the pipe members at respective locations spaced inwardly from the outwardly facing faces.
6. A hybrid breakwater comprising:
a first wave-attenuating panel fixedly coupled to a seabed through a plurality of pilings such that a majority of the first panel remains underwater;
a second, positively buoyant wave-attenuating panel movably coupled to the seabed such that the buoyant panel floats adjacent a free surface regardless of tide, the second panel being spaced horizontally from the first panel, the second panel having opposed, outwardly facing faces separated by a panel thickness and a panel height perpendicular to the panel thickness, the panel height extending from a lower edge of the second panel to an upper edge of the second panel, the panel height being greater than the panel thickness, wherein a plane defined by at least one of the faces is oriented substantially vertically;
wherein the first wave-attenuating panel does not restrict vertical movement of the second wave-attenuating panel;
wherein the plurality of pilings form a row of pilings, the first panel is positioned on one side of the row of pilings, and the second panel is positioned on an opposite side of the row of pilings such that a face of the first panel that faces in a horizontal direction toward the second panel is horizontally spaced from a face of the second panel that faces in a horizontal direction toward the first panel.
7. The hybrid breakwater of claim 6, wherein the second panel comprises a plurality of horizontally oriented pipe members stacked one on top of each other.
8. The hybrid breakwater of claim 6, wherein an entirety of the second panel is spaced horizontally from the first panel.
9. The hybrid breakwater of claim 6, wherein the first panel comprises a plurality of horizontally oriented pipe members stacked one on top of each other.
10. A hybrid breakwater comprising:
a first wave-attenuating panel fixedly coupled to a seabed through a plurality of pilings such that a majority of the first panel remains underwater;
a second, positively buoyant wave-attenuating panel movably coupled to the seabed such that the buoyant panel floats adjacent a free surface regardless of tide, the second panel being spaced horizontally from the first panel, the second panel having opposed, outwardly facing faces separated by a panel thickness and a panel height perpendicular to the panel thickness, the panel height extending from a lower edge of the second panel to an upper edge of the second panel, the panel height being greater than the panel thickness, wherein a plane defined by at least one of the faces is oriented substantially vertically;
wherein the first wave-attenuating panel does not restrict vertical movement of the second wave-attenuating panel;
wherein the first panel comprises a plurality of horizontally oriented pipe members stacked one on top of each other, the second panel comprises a plurality of horizontally oriented pipe members stacked one on top of each other, the first panel having a central plane extending through the centers of the pipe members of the first panel, the second panel having a central plane extending through the centers of the pipe members of the second panel, the central plane of the first panel being spaced horizontally from the central plane of the second panel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of adjusting the duty cycle of a signal, the method comprising:
generating, by a clock signal source circuit, a clock input signal that includes true and complement clock signals;
receiving, by a duty cycle correction circuit, the clock input signal;
deriving from the clock input signal, by the duty cycle correction circuit, first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets; and
shifting, by the duty cycle correction circuit, the voltage offset of one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal to provide a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal.
2. The method of claim 1, further comprising detecting, by an error detection circuit, a duty cycle error in the clock output signal.
3. The method of claim 2, wherein the detecting step includes low pass filtering, by a low pass filter in the error detection circuit, the clock output signal to generate the duty cycle error signal.
4. The method of claim 3, further comprising generating, by the low pass filter, a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal.
5. The method of claim 2, wherein the detecting step includes determining, by the error detection circuit, times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal.
6. The method of claim 1, further comprising providing the first and second differential clock signals to first and second nodes, respectively, of the duty cycle correction circuit, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal.
7. A duty cycle adjustment circuit, comprising:
a clock input that receives a clock input signal that includes true and complement clock signals;
a duty cycle correction circuit, coupled to the clock input, that derives from the clock input signal first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets;
the duty cycle correction circuit including a voltage offset shift circuit that shifts the voltage offset exhibited by one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, the duty cycle correction circuit thus providing a duty cycle adjusted clock output signal, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal, thus providing a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal.
8. The duty cycle adjustment circuit of claim 7, further comprising an error detection circuit, coupled to the duty cycle correction circuit to receive the clock output signal and detect duty cycle error in the clock output signal.
9. The duty cycle adjustment circuit of claim 8, wherein the error detection circuit includes a low pass filter that filters the clock output signal to generate the duty cycle error signal.
10. The duty cycle adjustment circuit of claim 9, wherein the low pass filter generates a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal.
11. The duty cycle adjustment circuit of claim 8, wherein the error detection circuit determines times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal.
12. The duty cycle adjustment circuit of claim 7, wherein the duty cycle correction circuit includes first and second nodes to which the first and second differential clock signals are provided, respectively, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal.
13. An information handling system (IHS), comprising
a memory,
a processor coupled to the memory, the processor including a duty cycle adjustment circuit, the duty cycle adjustment circuit including:
a clock input that receives a clock input signal that includes true and complement clock signals;
a duty cycle correction circuit, coupled to the clock input, that derives from the clock input signal first and second differential clock signals corresponding to the true and complement clock signals, respectively, the first and second differential clock signals exhibiting respective voltage offsets;
the duty cycle correction circuit including a voltage offset shift circuit that shifts the voltage offset exhibited by one of the first and second differential clock signals in response to a duty cycle exhibited by a clock output signal derived from the first and second differential clock signals, the duty cycle correction circuit thus providing a duty cycle adjusted clock output signal, wherein the duty cycle correction circuit shifts the voltage offset of one of the first and second differential clock signals in response to a duty cycle error signal, thus providing a voltage offset shifted differential clock signal and a voltage offset un-shifted differential clock signal.
14. The IHS of claim 13, further comprising an error detection circuit, coupled to the duty cycle correction circuit to receive the clock output signal and detect duty cycle error in the clock output signal.
15. The IHS of claim 14, wherein the error detection circuit includes a low pass filter that filters the clock output signal to generate the duty cycle error signal.
16. The IHS of claim 15, wherein the low pass filter generates a DC voltage error signal that exhibits a voltage proportional to the duty cycle of the clock output signal.
17. The IHS of claim 14, wherein the error detection circuit determines times when the voltage offset shifted differential clock signal intersects with the voltage offset un-shifted differential clock signal.
18. The IHS of claim 13, wherein the duty cycle correction circuit includes first and second nodes to which the first and second differential clock signals are provided, respectively, the duty cycle correction circuit pulling one of the first and second nodes down to shift the voltage offset of one of the first and second differential clock signals to affect the duty cycle of the clock output signal.