Author: claimsbot

1. A method of forming an integrated circuit, comprising:
forming a conductive layer over a first region of a semiconductor;
forming a dielectric layer comprising carbon over said conductive layer;
forming a PMD dielectric layer over said dielectric layer and said conductive layer;
forming at least one opening in said PMD dielectric layer over said conductive layer thereby exposing a region of said dielectric layer;
removing said exposed region of said dielectric layer; and
forming a first conductive region in said opening of said PMD layer wherein said first conductive region contacts said conductive layer.
2. The method of claim 1 wherein said dielectric layer is formed from a material selected from the group consisting of silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and boron carbide.
3. The method of claim 1 wherein said removing said exposed region of said dielectric layer comprises using a RIE etch comprising chlorine.
4. The method of claim 1 further comprising forming a second dielectric layer between said conductive layer and said dielectric layer.
5. A method of forming an integrated circuit contact, comprising:
forming a conductive layer over a first region of a semiconductor;
forming a first dielectric layer over said conductive layer;
forming a second dielectric layer comprising carbon over said first conductive layer;
forming a PMD dielectric layer over said second dielectric layer and said conductive layer;
forming at least one opening in said PMD dielectric layer over said conductive layer thereby exposing a region of said second dielectric layer;
removing said exposed region of said second dielectric layer thereby exposing a region of said first dielectric layer;
removing said exposed region of said first dielectric layer; and
forming a first conductive region in said opening of said PMD layer wherein said first conductive region contacts said conductive layer.
6. The method of claim 5 wherein said second dielectric layer is formed from a material selected from the group consisting of silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and boron carbide.
7. The method of claim 6 wherein said removing said exposed region of said second dielectric layer comprises using a RIE etch comprising chlorine.
8-10. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power control circuit, comprising an electronic switch electrically coupled between a power unit and an electronic device, a driving circuit electrically coupled to the electronic switch, and a mechanical switch electrically coupled to the driving circuit, wherein:
the driving circuit receives a power-on signal from the mechanical switch, and signals the electronic switch to turn on and supply power to the electronic device in accordance with the power-on signal;
the electronic device controls the driving circuit to maintain the electronic switch to be on and continue the power supply to the electronic device; and
the electronic device receives a power-off signal from the mechanical switch, and signals the driving circuit to turn off the electronic switch and discontinues the power supply to the electronic device in accordance with the power-off signal.
2. The power control circuit as claimed in claim 1, wherein the mechanical switch is a dual-contact self-returning switch or a multi-contact self-returning switch, with a first contact connects with the driving circuit and a second contact connects with the electronic device.
3. The power control circuit as claimed in claim 2, wherein the mechanical switch includes a self-returning key which can move between the first contact and the second contact by control of an external force.
4. The power control circuit as claimed in claim 3, wherein the self-returning key reaches the first contact and produces a power-on signal to the driving circuit.
5. The power control circuit as claimed in claim 4, wherein the self-returning key reaches the second contact and produces a power-off signal to the electronic device.
6. The power control circuit as claimed in claim 5, wherein the electronic switch comprises a P-channel MOS having a gate, a source and a drain, the gate connecting with the driving circuit, the source connecting with the power unit and the drain connecting with the electronic device.
7. The power control circuit as claimed in claim 6, wherein the driving circuit comprises a resistance component electrically coupled between the source and the gate of the P-channel MOS and a N-channel MOS having a gate, a source and a drain, the gate of the N-channel MOS connecting with the electronic device, the source of the N-channel MOS being grounded and the drain of the N-channel MOS connecting with the gate of the P-channel MOS.
8. The power control circuit as claimed in claim 7, wherein the first contact of the mechanical switch connects with the drain of the N-channel MOS.
9. The power control circuit as claimed in claim 6, wherein the driving circuit comprising a resistance component electrically coupled between the source and the gate of the P-channel MOS and a diode having a cathode and an anode, the cathode connecting with the gate and the anode connecting with the electronic device.
10. The power control unit as claimed in claim 9, wherein the first contact of the mechanical switch connects with the cathode of the diode.
11. The power control circuit as claimed in claim 1, wherein the electronic device receives the power-on signal via the driving circuit and boots up in accordance with the power-on signal.
12. The power control circuit as claimed in claim 1, wherein the electronic device receives the power-off signal and prepares for a shut down in accordance with the power-off signal.

1. A structure fabrication method, comprising:
bonding an integrated circuit to a top side of an interposing shield, wherein the integrated circuit comprises N chip electric pads electrically connected to a plurality of devices on the integrated circuit, wherein the interposing shield comprises the N electric conductors, wherein N is an integer of at least 2, and wherein the interposing shield comprises a shield material that includes a first semiconductor material; and
polishing a bottom side of the interposing shield so as to expose the N electric conductors to a surrounding ambient at the bottom side of the interposing shield,
wherein said bonding comprises bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors,
wherein after said bonding and before said polishing, the shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient, and
wherein said polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.
2. The method of claim 1, further comprising:
forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.
3. The method of claim 2, further comprising, after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps.
4. The method of claim 2, wherein the N solder bumps are electrically connected to corresponding electric conductors of the N electric conductors via corresponding electrical chip pads, and wherein each electrical chip pad is disposed between and in direct physical contact with the corresponding solder bump and the corresponding electric conductor.
5. The method of claim 1, wherein the first semiconductor material is the only semiconductor material in the interposing shield.
6. The method of claim 5, wherein the interposing shield has a thickness of at least 50 \u03bcm after said polishing the bottom side is performed.
7. The method of claim 5, wherein the semiconductor material consists of silicon.
8. The method of claim 1, wherein said providing the interposing shield comprises:
providing a semiconductor layer;
creating N trenches in the semiconductor layer;
filling the N trenches with an electrically conducting material so as to form the N electric conductors, wherein the semiconductor layer, after said filling the N trenches is performed, comprises the interposing shield.
9. The method of claim 8, wherein said providing the interposing shield further comprises forming a dielectric layer on side walls of the N trenches before said filling the N trenches is performed.
10. The method of claim 9, wherein each trench of the N trenches has an annular shape.
11. A structure fabrication method, comprising:
bonding an integrated circuit to a top side of an interposing shield such that N chip electric pads are in electrical contact with N electric conductors, wherein N is an integer of at least 2, wherein the integrated circuit comprises N chip electric pads, wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit, wherein the interposing shield comprises the N electric conductors, and wherein the interposing shield comprises a first semiconductor;
polishing a bottom side of the interposing shield so as to expose the N electric conductors to a surrounding ambient at the bottom side of the interposing shield;
forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors;
after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps; and
forming M copper regions within the interposing shield, wherein M is at least 2, wherein each copper region comprises copper, wherein a first direction from the top side to the bottom side is perpendicular to both the bottom side and the top side, wherein each copper region has a length oriented in the first direction and a width oriented in a second direction perpendicular to the first direction, wherein the length exceeds the width of each copper region, wherein each electric conductor has a length oriented in the first direction and a width oriented in the second direction, wherein the length exceeds the width of each electric conductor.
12. The method of claim 11, wherein the length of each copper region is less than the length of each electric conductor.
13. The method of claim 11, wherein N exceeds M.
14. The method of claim 13, wherein N=M+1.
15. The method of claim 14, wherein M is at least 3, and wherein the N electric conductors and the M copper regions are distributed in the second direction in a spatial sequence of C1, E1, E2, C2, E3, E4, C3, . . . , wherein Cm denotes copper region m for m=1, 2, . . . , M, and wherein En denotes electric conductor n for n=1, 2, . . . , N.
16. A structure fabrication method, comprising:
providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom, wherein the interposing shield comprises a first semiconductor material;
bonding an integrated circuit to a top side of an interposing shield such that N chip electric pads are in electrical contact with N electric conductors side, wherein N is at least 2, wherein the integrated circuit comprises N chip electric pads, wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit, wherein the interposing shield comprises the N electric conductors, and wherein the interposing shield comprises a first semiconductor material;
polishing a bottom side of the interposing shield so as to expose the N electric conductors to a surrounding ambient at the bottom side of the interposing shield;
forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors;
after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps; and
forming a copper layer sandwiched between, and electrically insulated from, the N electric conductors and the N solder bumps.
17. The method of claim 16, wherein a first direction from the top side to the bottom side is perpendicular to both the bottom side and to top side, wherein the copper layer has a thickness in a range of 10 \u03bcm to 15 \u03bcm in the first direction, and wherein the interposing shield has a thickness less than 1 \u03bcm in the first direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A field effect transistor comprising:
a semiconductor substrate having a top surface and a bottom surface, wherein the semiconductor substrate includes a drain region therein;
a trench gate region extending into the semiconductor substrate for a first predetermined depth, wherein the trench gate region is insulated from the semiconductor substrate by a gate insulator region;
a pair of source regions in the semiconductor substrate and disposed on opposite sides of the trench gate region;
a pair of body regions extending into the semiconductor substrate for a second predetermined depth and disposed on opposite sides of the trench gate region, wherein each of the body regions separates a respective source region from the drain region and the second predetermined depth is less than the first predetermined depth;
a source metal contact disposed on the top surface of the semiconductor substrate, wherein the source metal contact is in physical contact with the pair of source regions, the pair of body regions, and a portion of the drain region, wherein the source metal contact is insulated from the trench gate region by the gate insulator region; and
a drain metal contact disposed on the bottom surface of the semiconductor substrate, wherein the drain metal contact is in physical contact with the drain region;
wherein each of the body regions further includes a lightly-doped body region below a respective source region and a heavily-doped body region above the lightly-doped body region such that the heavily-doped body region is in physical contact with the source metal contact and the lightly-doped body region is not in physical contact with the source metal contact.
2. The field effect transistor of claim 1, wherein:
the pair of source regions and the drain region are n-doped; and
the pair of body regions are p-doped.
3. The field effect transistor of claim 2, wherein said drain region comprises:
a heavily n-doped portion and a lightly n-doped portion;
wherein the heavily n-doped portion is in physical contact with the drain metal contact and the lightly n-doped portion is in physical contact with the pair of body regions and the source metal contact.
4. The field effect transistor of claim 2, wherein:
the lightly p-doped body region is disposed between the respective source region, the gate insulator region, and the drain region proximate the trench gate region; and
the heavily p-doped body region is disposed between the drain region, the lightly p-doped body region, the respective source region, and the source metal contact.
5. The field effect transistor of claim 1, wherein:
the pair of source regions and the drain region are p-doped; and
the pair of body regions are n-doped.
6. The field effect transistor of claim 5, wherein said drain region comprises:
a heavily p-doped portion and a lightly p-doped portion;
wherein the heavily p-doped portion is in physical contact with the drain metal contact and the lightly p-doped portion is in physical contact with the pair of body regions and the source metal contact.
7. The field effect transistor of claim 5, wherein:
the lightly n-doped body region is disposed between the respective source region, the gate insulator region, and the drain region proximate the trench gate region; and
the heavily n-doped body region is disposed between the drain region, the lightly n-doped body region, the respective source region, and the source metal contact.
8. The field effect transistor of claim 1, further comprising a Schottky junction disposed at the top surface where the source metal contact is physical contact with the portion of the drain region.
9. The field effect transistor of claim 1, wherein said pair of source regions are formed as substantially parallel elongated structures.
10. A field effect transistor comprising:
a first and second trench gate regions extending into a semiconductor substrate for a first predetermined depth;
a first source region disposed in the semiconductor substrate and proximate the first trench gate region;
a second source region disposed in the semiconductor substrate and proximate the second trench gate region;
a first lightly-doped body region disposed below said first source region proximate said first trench gate region and extending into the semiconductor substrate for a depth that is less than the first predetermined depth;
a second lightly-doped body region disposed below said second source region proximate said second trench gate region and extending into the semiconductor substrate for a depth that is less than the first predetermined depth;
a third heavily-doped body region disposed in the semiconductor substrate and adjacent said first source region and above said first lightly-doped body region;
a fourth heavily-doped body region disposed in the semiconductor substrate and adjacent said second source region and above said second lightly-doped body region;
a drain region disposed in the semiconductor substrate and between said first and second lightly-doped body regions and said third and fourth heavily-doped body regions and between said first and second gate regions, wherein said first lightly-doped body region and said third heavily-doped body region are disposed between said drain region and said first source region and wherein said second lightly-doped body region and said fourth heavily-doped body region are disposed between said drain region and said second source region;
a source contact disposed on a top surface of the semiconductor substrate and-in physical contact with said first and second source regions, said third and fourth heavily-doped body regions and a portion of said drain region disposed between said first and second trench gate regions;
a first gate insulator region insulating said first trench gate region from said first source region, said first lightly-doped body region, said drain region, and said source contact; and
a second gate insulator region insulating said second trench gate region and said second source region, said second lightly-doped body region, said drain region, and said source contact.
11. The field effect transistor of claim 10, wherein:
said first and second source regions comprise an n-doped semiconductor;
said drain region comprises an n-doped semiconductor; and
said first and second lightly-doped body regions comprise a p-doped semiconductor.
12. The field effect transistor of claim 11, wherein said drain region comprises: a heavily n-doped portion; and
a lightly n-doped portion disposed between said heavily n-doped portion and said first and second lightly-doped body regions, said third and fourth heavily-doped body regions, and said source contact.
13. The field effect transistor of claim 11, wherein:
said first lightly-doped body region comprises a lightly p-doped portion disposed between said first source region and said drain region proximate said gate region;
said third heavily-doped body region comprises a heavily p-doped portion disposed proximate said drain region and said source contact;
said second lightly-doped body region comprises a lightly p-doped portion disposed between said second source region and said drain region proximate said gate region; and
said fourth heavily-doped body region comprises a heavily p-doped portion disposed proximate said drain region and said source contact.
14. The field effect transistor of claim 11, wherein:
said first and second source regions comprise a p-doped semiconductor;
said drain region comprises a p-doped semiconductor; and
said first and second lightly-doped body regions comprise an n-doped semiconductor.
15. The field effect transistor of claim 14, wherein said drain region comprises:
a heavily p-doped portion; and
a lightly p-doped portion disposed between said heavily p-doped portion and said first and second lightly-doped body regions, said third and fourth heavily-doped body regions, and said source contact.
16. The field effect transistor of claim 14, wherein:
said first lightly-doped body region comprises a lightly n-doped portion disposed between said first source region and said drain region proximate said first gate region;
said third heavily-doped body region comprises a heavily n-doped portion disposed proximate said source contact;
said second lightly-doped body region comprises a lightly n-doped portion disposed between said second source region and said drain region proximate said second gate region; and
said fourth heavily-doped body region comprises a heavily n-doped portion disposed proximate said source contact.
17. The field effect transistor of claim 10, further comprising a Schottky junction disposed at an interface between said source contact and said portion of said drain region proximate said first and second lightly-doped body regions.
18. The field effect transistor of claim 10, wherein said first and said second gate regions are formed as substantially parallel elongated structures.