Author: claimsbot

1. A method to be executed at least in part in a computing device for performing concatenative speech synthesis, the method comprising:
determining feature vectors for speech segments based on a matrix of concatenation costs;
applying distance weighting to each speech segment pair based on the feature vectors;
clustering the speech segments into a predefined number of groups such that an average distance between speech segments within each group is minimized;
selecting a representative speech segment for each group; and
generating a compressed concatenation cost matrix based on the representative speech segments.
2. The method of claim 1, further comprising:
pre-saving the compressed concatenation cost matrix for real time computations in synthesizing speech.
3. The method of claim 1, wherein the distance weighting is applied employing one of: a Euclidean distance function and a city block distance function.
4. The method of claim 1, wherein the matrix of concatenation costs is constructed along a preceding speech segments axis and a following speech segments axis.
5. The method of claim 4, wherein a concatenation cost between a preceding speech segment and a following speech segment is different from a concatenation cost between the same speech segments with an order of the speech segments reversed.
6. The method of claim 1, wherein the representative speech segment for each group is selected such that an average distance between the representative speech segment and other speech segments within the same group is minimized.
7. The method of claim 1, wherein a number of the groups is determined based on at least one from a set of: a total number of speech segments, distances between the speech segments, and a desired reduction in concatenation cost data.
8. The method of claim 1, wherein the representative speech segment for each group is selected based on one of a median concatenation cost and a mean concatenation cost of each group.
9. The method of claim 1, wherein the speech segments include one of: individual phones, diphones, half-phones, and syllables.
10. A text to speech (TTS) synthesis system for generating speech employing compressed concatenation cost data, the system comprising:
a speech segment data store;
an analysis engine; and
a speech synthesis engine configured to:
determine a feature vector for each speech segment that comprises concatenation cost values of each speech segment with other speech segments;
apply distance weighting to each speech segment pair based on their respective feature vectors;
cluster the speech segments into a predefined number of groups such that an average distance between speech segments within each group is minimized;
select a representative speech segment for each group such that an average distance between the representative speech segment and other speech segments within the same group is minimized;
generate a compressed concatenation cost matrix based on the representative speech segments; and
pre-save the compressed concatenation cost matrix for real time computations in synthesizing speech.
11. The TTS system of claim 10, wherein the distance weighting is applied such that a sensitivity to compression errors is reduced.
12. The TTS system of claim 10, wherein the representative speech segment for each group is further selected based on center re-estimation.
13. The TTS system of claim 12, wherein the center re-estimation includes estimating a concatenation cost value based on a portion of whole samples such that a computation cost is reduced when speech segment numbers are relatively large.
14. The TTS system of claim 10, wherein the speech segment data store is configured to receive speech segments from at least one of: a user input and a set of pre-recorded speech patterns.
15. The TTS system of claim 10, wherein the analysis engine is configured to:
perform at least one from a set of: text analysis, prosody analysis, and phonetic analysis; and
provide input to the speech synthesis engine for segment selection based on the performed analyses.
16. A computer-readable storage medium with instructions stored thereon for generating speech employing compressed concatenation cost data, the instructions comprising:
determining feature vectors for speech segments based on a matrix of concatenation costs constructed along a preceding speech segments axis and a following speech segments axis;
applying distance weighting to each speech segment pair based on their respective feature vectors;
clustering the speech segments into M preceding segment and N following segment groups such that an average distance between speech segments within each group is minimized;
selecting a representative speech segment for each group;
generating a compressed concatenation cost matrix such that a concatenation cost between two speech segments is approximated by a concatenation cost between representative segments of respective preceding speech segment and following speech segment groups; and
pre-saving the compressed concatenation cost matrix for real time computations in synthesizing speech.
17. The computer-readable medium of claim 16, wherein the distance weighting is applied employing distance function:
\u03a3m=1n{abs(cci,m\u2212ccj,m)*K0\u2212(cci,m+ccj,m)}2, where cci,j are concatenation costs between speech segments i and j, and K0 is a predefined constant.
18. The computer-readable medium of claim 16, wherein the representative speech segment for each group is selected based on one of: minimization of an average distance between the representative speech segment and other speech segments within the same group, median concatenation cost of the group, and a mean concatenation cost of the group.
19. The computer-readable medium of claim 16, wherein the instructions further comprise:
determining M and N based on at least one from a set of: the total number of speech segments, distances between the speech segments, and a desired reduction in concatenation cost data
20. The computer-readable medium of claim 16, wherein a size of pre-saved concatenation data is reduced by n2(M\xd7N), where n is the total number of the speech segments.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An information recording medium having an information track formed spirally or in coaxial circles comprising:
a recordable area for information having a groove in a first depth being prerecorded with a frequency signal and a land pre-pit address signal from an inner circumference of said information track;
a first read only area having a pit in a second depth prerecorded with a frequency signal to be recorded with a reproduction signal as a pit; and
a second read only area having a pit in a first depth prerecorded with a frequency signal and a land pre-pit address signal to be recorded with a reproduction signal as a pit,
wherein a tracking error signal at a time of tracking off in a boundary between said first read only area and said second read only area is defined as a ratio of maximum amplitude in both directions from a center of maximum amplitude of said tracking error signal at the time of tracking off in said recordable area.
2. A reproducing method of information recording medium having an information track formed spirally or in coaxial circles comprising:
a recordable area for information having a groove in a first depth being prerecorded with a frequency signal and a land pre-pit address signal from an inner circumference of said information track;
a first read only area having a pit in a second depth prerecorded with a frequency signal to be recorded with a reproduction signal as a pit; and
a second read only area having a pit in a first depth prerecorded with a frequency signal and a land pre-pit address signal to be recorded with a reproduction signal as a pit,
wherein a tracking error signal at a time of tracking off in a boundary between said first read only area and said second read only area is defined as a ratio of maximum amplitude in both directions from a center of maximum amplitude of said tracking error signal at the time of tracking off in said recordable area,
said reproducing method comprising the steps of:
reproducing a land pre-pit address signal of said information track; and
tracking said boundary continuously on the basis of amplitude of a tracking error signal in said first read only area and said second read only area in accordance with reproduced said land pre-pit address signal.

1. A semiconductor memory device comprising:
a plurality of memory cells, arranged in rows and columns, each formed on an insulating film, each of the memory cells including (i) a first transistor for storing information by a voltage at a body region and having a first conduction node receiving a fixed voltage, and second and third conduction nodes isolated from said first conduction node by said body region, (ii) a second transistor having a fourth conduction node connected to said second conduction node of said first transistor, and (iii) a third transistor having a fifth conduction node connected to the third conduction node of said first transistor;
a plurality of first word lines, arranged corresponding to the memory cell rows, each connected to control electrodes of the second transistors of the memory cells in a corresponding row;
a plurality of second word lines, arranged corresponding to the memory cell rows, each connected to control electrodes of the third transistors of the memory cells in a corresponding row;
a plurality of charge lines, arranged corresponding to said memory cell rows, each connected to control electrodes of the first transistors of the memory cells in a corresponding row;
a plurality of first bit lines, arranged corresponding to said memory cell columns, respectively, each connected to sixth conduction nodes of the second transistors of the memory cells in a corresponding column; and
a plurality of second bit lines, arranged corresponding to said memory cell columns, respectively, each connected to seventh conduction nodes of the third transistors of the memory cells in a corresponding column.
2. The semiconductor memory device according to claim 1, wherein
each of said first transistors includes a first impurity region formed under the control electrode and forming said body region; a second impurity region adjacent to said first impurity region and forming said second conduction node connected to said second transistor; a third impurity region opposed to said second impurity region with respect to said first impurity region and forming the third conduction node connected to said third transistor; and a fourth impurity region arranged in a region of said first impurity region different from sides facing the second and third impurity regions, adjacent to said first impurity region and forming said first conduction node.
3. The semiconductor memory device according to claim 1, wherein
the second and third transistors of the memory cells aligned in a column direction are formed in an active region arranged extending linearly in the column direction, and the first and second bit lines in the corresponding column are arranged sandwiching the active region of the memory cells in the corresponding column, and
said first transistor has a region for forming said body region and said first conduction node formed in a projected region arranged in a portion between formation regions of the second and third transistors, said projected portion arranged projecting in a row direction from said active region beyond a corresponding first bit line, and regions for forming the second and third conduction nodes being shared by regions for forming the fourth and fifth conduction nodes of the second and third transistors, respectively.
4. The semiconductor memory device according to claim 1, wherein
the first and second word lines in each memory cell row are arranged sandwiching the charge line.
5. The semiconductor memory device according to claim 1, wherein
the memory cells are each formed in a rectangle-shaped active region, and
the first transistor of each memory cell has a control electrode of a T-shaped structure having a leg and a base, and the second and third transistors being arranged opposing to each other with respect to said leg, and
the second and third transistors of each memory cell have the control electrodes formed into L-shaped structures symmetrical with respect to said leg.
6. The semiconductor memory device according to claim 5, wherein
each first word line is connected to the control electrodes of the second transistors of the memory cells in two rows adjacent to each other in a column direction,
said second word line is connected to the control electrodes of the third transistors of the memory cells in the two rows adjacent to each other in said column direction,
the second and third transistors are arranged alternately to each other in the row direction, and
the memory cells arranged adjacent in the column direction in adjacent rows are connected to different bit lines.
7. The semiconductor memory device according to claim 5, wherein
each first word line has a portion extending under an adjacent second word line, and electrically coupled to the control electrode of a corresponding second transistor, and
each second word line has a portion extending under an adjacent first word line, and electrically coupled to the control electrode of the third transistor of the corresponding, adjacent memory cell.
8. A semiconductor memory device comprising:
a plurality of memory cells, arranged in rows and columns, each formed on an insulating film, each of the memory cells including (i) a first transistor for storing information by a voltage on a body region, and having a first conduction node receiving a fixed voltage, and a second conduction node isolated from said first conduction node by said body region, (ii) a second transistor having a third conduction node connected to said second conduction node of said first transistor, and (iii) a third transistor having a fourth conduction node connected to said body region of said first transistor and being different in conductivity type from the first and second transistors;
a plurality of first word lines, arranged corresponding to the memory cell rows, and each connected to control electrodes of the second transistors of the memory cells in a corresponding row;
a plurality of second word lines, arranged corresponding to said memory cell rows, each connected to control electrodes of the third transistors of the memory cells in a corresponding row;
a plurality of charge lines, arranged corresponding to said memory cell rows, each connected to control electrodes of the first transistors of the memory cells in a corresponding row;
a plurality of first bit lines, arranged corresponding to the memory cell columns, each connected to fifth conduction nodes of the second transistors of the memory cells in a corresponding column; and
a plurality of second bit lines, arranged corresponding to said memory cell columns, each connected to sixth conduction nodes of the third transistors of the memory cells in a corresponding column.
9. The semiconductor memory device according to claim 8, wherein
the memory cells aligned in the column direction are formed in an active region extending continuously in the column direction with convex and concave regions being arranged alternately in the column direction, and
the first and second transistors are formed in the convex regions, and the third transistors are formed in the concave regions.
10. The semiconductor memory device according to claim 8, wherein
in each memory cell row, the first and second word lines are arranged sandwiching the charge line.
11. The semiconductor memory device according to claim 8, wherein
in each memory cell row, the second word line and the charge line are arranged sandwiching a voltage line transmitting said fixed voltage.
12. The semiconductor memory device according to claim 8, wherein
the memory cell is formed in a rectangle-shaped active region, and
the first transistor of said memory cell has a control electrode of a T-shaped structure having a leg and a base, and the second and third transistors are arranged opposing to each other with respect to said leg,
the control electrodes of said second and third transistors have L-shaped structures arranged symmetrically with respect to said leg, and
a region forming said second transistor and a region forming said third transistor in each of the active regions are different in conductivity type from each other.
13. The semiconductor memory device according to claim 8, wherein
each of the first word line is connected to control electrodes of the second transistors of the memory cells in two rows adjacent to each other in a column direction,
each of the second word line is connected to control electrodes of the third transistors of the memory cells in two rows adjacent to each other in said column direction,
said second and third transistors are arranged alternately to each other in a row direction,
said second transistors are arranged in alignment in the column direction, and
said third transistors are arranged in alignment in the column direction, and
two second transistors located in the adjacent rows and aligned in the column direction are connected to different first bit lines, respectively, and two third transistors located in the adjacent rows and aligned in the column direction are connected to different second bit lines.
14. The semiconductor memory device according to claim 13, wherein
the first and second transistors are arranged alternately in the column direction, and the first and third transistors are arranged alternately in said column direction.
15. A semiconductor memory device comprising:
a plurality of memory cells formed on an insulating layer and arranged in rows and columns, each of the memory cells including a first transistor, a second transistor connected in series to said first transistor, and a third transistor having a control electrode connected to a body region of said first transistor and connected in series to said first transistor, and a connection node between the first and third transistors being coupled to a source line supplying a predetermined voltage;
a plurality of charge lines, arranged corresponding to the memory cell rows, each connected to control electrodes of the first transistors of the memory cells in a corresponding row;
a plurality of word lines, arranged corresponding to said memory cell rows, each connected to control electrodes of the second transistors of the memory cells in a corresponding row;
a plurality of first bit lines, arranged corresponding to said memory cell rows, each connected to the second transistors of the memory cells in a corresponding column; and
a plurality of second bit lines arranged corresponding to said memory cell columns, each connected to the third transistors of the memory cells in a corresponding column.
16. The semiconductor memory device according to claim 15, wherein
the memory cells arranged in alignment in the column direction are formed in an active region extending continuously in the column direction with convex and concave regions being alternately arranged in the column direction, and
the first and second transistors are formed in the convex regions, the third transistors are formed in the concave regions, the concave region having an impurity region coupled to the body region of said first transistor, and said impurity region being coupled to the control electrode of said third transistor.
17. A semiconductor memory device comprising:
a plurality of memory cells, arranged in rows and columns, each formed on an insulating film and including first and second transistors of different conductivity types, the first transistor having a first conduction node electrically connected to a body region of the second transistor, a second conduction node and a first control electrode, and said second transistor having a third conduction node receiving a reference voltage, a fourth conduction node and a second control electrode;
a plurality of first word lines, arranged corresponding to the memory cell rows, each connected to the first control electrodes of the first transistors of the memory cells in a corresponding row;
a plurality of second word lines arranged corresponding to said memory cell rows, respectively, and each connected to the second control electrodes of the second transistors of the memory cells in the corresponding row;
a plurality of first bit lines, arranged corresponding to the memory cell columns, each connected to the second conduction nodes of said first transistors in a corresponding column; and
a plurality of second bit lines, arranged corresponding to the memory cell columns, each connected to the fourth conduction nodes of said second transistors in a corresponding column.
18. The semiconductor memory device according to claim 17, wherein
in each of the memory cells,
the first transistor has said first control electrode formed of a first electrode interconnection arranged linearly and forming a part of a corresponding first word line, and the first and second conduction nodes formed of first and second impurity regions of a first conductivity type arranged opposing to each other with respect to said first electrode interconnection, and
said second transistor has said second control electrode formed of a second electrode interconnection having a first portion parallel to said first electrode interconnection and a second portion extending in a direction crossing said first portion, said body region formed of a third impurity region of the first conductivity type adjacent to the second impurity region and formed under said second electrode interconnection, and said third and fourth conduction nodes formed of impurity regions of a second conductivity type arranged opposing to each other with respect to said second portion.
19. The semiconductor memory device according to claim 18, wherein
said insulating film is formed on a semiconductor substrate receiving said reference voltage, and
the impurity region forming said third conduction node of said second transistor is electrically connected to said semiconductor substrate via a through-opening formed in said insulating film.
20. The semiconductor memory device according to claim 17, wherein
in each of said memory cells,
said first transistor has (i) said first control electrode formed of a first electrode interconnection arranged linearly and forming a part of a corresponding first word line, (ii) said first and second conduction nodes formed of first and second impurity regions of a first conductivity type arranged opposing to each other with respect to said first electrode interconnection, said first impurity region is formed at a surface of a third impurity region of a second conductivity type forming the body region of said first transistor, and (iii) said second impurity region being formed reaching said insulating film, and
said second transistor has (a) said second control electrode formed of a second electrode interconnection parallel to said first electrode interconnection, (b) the body region formed of a fourth impurity region of the first conductivity type electrically connected to said second impurity region, adjacent to a region for forming said first transistor and formed over an entire region for forming said second transistor, and (c) the third and fourth conduction nodes formed of fifth and sixth impurity regions of the second conductivity type formed, at a surface of said fourth impurity region, opposing to each other with respect to said second electrode interconnection.
21. The semiconductor memory device according to claim 20, further comprising:
a seventh impurity region of the second conductivity type formed opposing to said fifth impurity region with respect to said first electrode interconnection, adjacent to said first impurity region and at the surface of said fourth impurity region.
22. The semiconductor memory device according to claim 17, further comprising:
a plurality of sense amplifier circuits, arranged corresponding to the memory cell columns, each being activated in a data read operation to amplify differentially and latch potentials of the first and second bit lines in a corresponding column;
a second word line select circuit being activated in said data read operation to drive the second word line arranged corresponding to an addressed row to a selected state; and
a first word line select circuit for driving the first word line arranged corresponding to said addressed row when the sense amplifier circuits are active in said data read operation, and for driving the first word line corresponding to an addressed row according to an address signal in a data write operation.
23. A semiconductor memory device comprising:
a plurality of memory cells, arranged in rows and columns, each having a charge accumulation node, a first transistor of a first conductivity type transmitting charges corresponding to write data to said charge accumulation node in a data write operation, and a second transistor of a second conductivity type selectively transmitting a voltage on a reference potential node according to a potential of said charge accumulation node in a data read operation;
a plurality of first word lines, arranged corresponding to said memory cell rows, each connected to first control electrodes of said first transistors of the memory cells in a corresponding row;
a plurality of second word lines, arranged corresponding to the memory cell rows, each connected to second control electrodes of said second transistors of the memory cells in a corresponding row;
a plurality of first bit lines, arranged corresponding to the memory cell columns, each connected to first conduction nodes of said first transistors in a corresponding column;
a plurality of second bit lines, arranged corresponding to said memory cell columns each connected to second conduction nodes of the second transistors in a corresponding column;
a plurality of sense amplifier circuits arranged corresponding to said memory cell columns, and made active in a data read operation to amplify differentially voltages on the first and second bit lines in corresponding columns; and
a row select circuit for, in the data read operation, driving the second word line arranged corresponding to an addressed row to a selected state according to an address signal before the sense amplifier circuits are made active, and then driving the first word line arranged corresponding to the addressed row to the selected state after said sense amplifier circuits are made active.
24. The semiconductor memory device according to claim 23, wherein
said charge accumulation node is a body region of a third transistor of the second conductivity type connected in series to said second transistor between said reference potential node and a corresponding second bit line, and said body region is electrically coupled to a corresponding first bit line via said first transistor when said first transistor is made conductive.
25. The semiconductor memory device according to claim 23, wherein
said charge accumulation node is a body region of said second transistor, said second transistor is connected between said reference potential node and a corresponding second bit line, and said first transistor is connected between said body region and a corresponding first bit line.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for assigning a client to one of a plurality of real estate agents associated with a real estate service, the method comprising:
receiving a request from a client to get assigned to one of the plurality of real estate agents associated with the real estate service;
identifying the client’s current geographic position;
identifying a given real estate agent of the plurality of real estate agents that is proximate in distance to the client’s geographic position; and
assigning the given real estate agent to the client.
2. The method of claim 1, wherein identifying the client’s current geographic position further comprises identifying geographic coordinate information associated with the client’s mobile device.
3. The method of claim 1, wherein the step of identifying the given real estate agent further comprises:
identifying geographic coordinate information associated with at least a subset of the plurality of real estate agents;
calculating a distance between the geographic coordinate information associated with each of the plurality of real estate agents and a geographic coordinate information associated with the client the client;
identifying a particular real estate agent with the least calculated distance.
4. The method of claim 1, wherein the step of assigning the given real estate agent to the client further comprises:
transmitting the request from the client to one or more real estate agents determined to be proximate in distance to the client’s current geographic position;
receiving an indication of acceptance of request from a first real estate agent of the one or more proximate real estate agents;
transmitting the indication of acceptance to the client.
5. The method of claim 4, further comprising:
matching the client’s current location with a specific MLS-listed property located at or near the client’s current geographic position;
transmitting information associated with the specific MLS-listed property to the first real estate agent subsequent to receiving the indication of acceptance of request from the first real estate agent.
6. The method of claim 1, further comprising:
receiving, in addition to the request to get assigned to an agent, a tour-request for immediate showing of a property located at or near the client’s current geographic position;
matching the client’s current location with a specific MLS-listed property located at or near the client’s current geographic position;
transmitting information associated with the specific MLS-listed property to the given real estate agent.
7. The method of claim 6, further comprising:
computing, based on the given real estate agent’s current geographic position, an approximate time of travel between the given real agent’s current geographic position and the client’s geographic position;
transmitting, to the client, information associated with the approximate time of travel for the given real estate agent to arrive at the client’s geographic position.
8. The method of claim 7, further comprising:
periodically identifying an updated geographic position of the given real estate agent;
periodically transmitting, to the client, an updated approximate time of travel for the given real estate agent to arrive at the client’s geographic position.
9. A method for assigning a client to one of a plurality of real estate agents associated with a real estate service, the method comprising:
receiving a request from a client to tour a property associated with the client’s current geographic position by one of the plurality of real estate agents associated with the real estate service;
identifying the client’s current geographic position based on geographic coordinates associated with the client’s mobile device;
matching the client’s current location with a specific MLS-listed property located at or near the client’s current geographic position;
transmitting information associated with the client’s current location andor the specific MLS-property to a subset of the plurality of real estate agents that are determined to be located within a predetermined distance relative to the client’s current geographic position;
receiving an acceptance from a first real estate agent of the subset of the plurality of real estate agents;
assigning the first real estate agent to the client; and
transmitting a confirmation message and information associated with the first real estate agent to the client.
10. The method of claim 9, further comprising:
computing, based on the first real estate agent’s current geographic position, an approximate time of travel between the first real agent’s current geographic position and the client’s geographic position;
transmitting, to the client, information associated with the approximate time of travel for the first real estate agent to arrive at the client’s geographic position.
11. A system for tracking a real estate agent’s property visits, the system comprising:
a processor;
a memory configured to store a set of instructions, which when executed by the processor cause the system to perform a method, the method including:
receiving a request from a client to get assigned to one of the plurality of real estate agents associated with the real estate service;
identifying the client’s current geographic position;
identifying a given real estate agent of the plurality of real estate agents that is proximate in distance to the client’s geographic position; and
assigning the given real estate agent to the client.
12. The system of claim 11, wherein identifying the client’s current geographic position further comprises identifying geographic coordinate information associated with the client’s mobile device.
13. The system of claim 11, wherein the step of identifying the given real estate agent further comprises:
identifying geographic coordinate information associated with at least a subset of the plurality of real estate agents;
calculating a distance between the geographic coordinate information associated with each of the plurality of real estate agents and a geographic coordinate information associated with the client the client;
identifying a particular real estate agent with the least calculated distance.
14. The system of claim 11, wherein the step of assigning the given real estate agent to the client further comprises:
transmitting the request from the client to one or more real estate agents determined to be proximate in distance to the client’s current geographic position;
receiving an indication of acceptance of request from a first real estate agent of the one or more proximate real estate agents;
transmitting the indication of acceptance to the client.
15. The system of claim 14, wherein the method further comprises:
matching the client’s current location with a specific MLS-listed property located at or near the client’s current geographic position;
transmitting information associated with the specific MLS-listed property to the first real estate agent subsequent to receiving the indication of acceptance of request from the first real estate agent.
16. The system of claim 11, wherein the method further comprises:
receiving, in addition to the request to get assigned to an agent, a tour-request for immediate showing of a property located at or near the client’s current geographic position;
matching the client’s current location with a specific MLS-listed property located at or near the client’s current geographic position;
transmitting information associated with the specific MLS-listed property to the given real estate agent.
17. The system of claim 16, wherein the method further comprises:
computing, based on the given real estate agent’s current geographic position, an approximate time of travel between the given real agent’s current geographic position and the client’s geographic position;
transmitting, to the client, information associated with the approximate time of travel for the given real estate agent to arrive at the client’s geographic position.