1460743669-3bc8daf3-f2cc-46d1-9978-c1419820829d

1. A multilayered semiconductor device, comprising:
a first semiconductor package, comprising:
a first semiconductor element; and
a first wiring board having the first semiconductor element mounted on one surface thereof and having a plurality of connection pads for electric connection to an outside formed on another surface thereof;

a second semiconductor package, comprising:
a second semiconductor element;
a second wiring board having the second semiconductor element mounted on one surface thereof; and
a first encapsulating resin for encapsulating the second semiconductor element therein; and

a plate member disposed between the first semiconductor package and the second semiconductor package,
wherein:
the first semiconductor package, the plate member, and the second semiconductor package are stacked in this order;
the first wiring board and the second wiring board are electrically connected to each other via a metal wire through one of a notch and an opening formed in the plate member; and
the first semiconductor element, the second semiconductor package, and the metal wire are encapsulated in a second encapsulating resin.
2. The multilayered semiconductor device according to claim 1, wherein a linear expansion coefficient of the plate member is larger than linear expansion coefficients of the first encapsulating resin and the second encapsulating resin.
3. The multilayered semiconductor device according to claim 2, wherein an area of the plate member is smaller than an area of the first wiring board seen from a direction perpendicular to a surface of the first wiring board, and the notch is formed by a plate body disposed within a region of the first wiring board and a protruding piece which protrudes from the plate body to a location of a connection pad disposed in a corner of the first wiring board among the plurality of connection pads.
4. The multilayered semiconductor device according to claim 3, wherein an area of the second wiring board is smaller than the area of the first wiring board and the second wiring board is disposed within the region of the first wiring board seen from the direction perpendicular to the surface of the first wiring board, and an area of the plate body is equal to or smaller than the area of the second wiring board and the plate body is disposed within a region of the second wiring board seen from the direction perpendicular to the surface of the first wiring board.
5. The multilayered semiconductor device according to claim 3, wherein the protruding piece includes a tip portion and a coupling portion, the tip portion being formed so as to cover a contour of a corner pad seen from the direction perpendicular to the surface of the first wiring board, the coupling portion coupling the plate body and tip portion and having a width smaller than a width of the tip portion.
6. The multilayered semiconductor device according to claim 3, wherein the protruding piece is formed so as to be thicker than the plate body.
7. The multilayered semiconductor device according to claim 1, wherein one surface of the plate member is bonded to the first semiconductor element by a bonding member, and another surface of the plate member is bonded to the first encapsulating resin of the second semiconductor package.
8. A printed circuit board, comprising:
a printed wiring board; and
the multilayered semiconductor device according to claim 1 mounted on the printed wiring board.
9. A method of manufacturing a multilayered semiconductor device, the multilayered semiconductor device comprising:
a first semiconductor package, the first semiconductor package comprising:
a first semiconductor element; and
a first wiring board having the first semiconductor element mounted on one surface thereof and having a plurality of connection pads formed on another surface thereof, the plurality of connection pads being formed of a conductor electrically connected to a printed wiring board; and

a second semiconductor package, the second semiconductor package comprising:
a second semiconductor element;
a second wiring board having the second semiconductor element mounted on one surface thereof; and
a first encapsulating resin for encapsulating the second semiconductor element therein,

the method comprising:
a step of arranging a plurality of first semiconductor packages;
a step of disposing a plurality of plate members on the plurality of first semiconductor packages, each plate member having a linear expansion coefficient that is larger than a linear expansion coefficient of the first encapsulating resin and having one of a notch and an opening formed therein;
a first fixing step of fixing the plurality of plate members to the plurality of first semiconductor packages, respectively;
a step of supplying a plurality of second semiconductor packages onto the plurality of plate members;
a second fixing step of fixing the plurality of second semiconductor packages to the plurality of plate members, respectively;
a step of electrically connecting each of a plurality of first wiring boards and each of a plurality of second wiring boards via the notch or the opening by using metal wires;
a step of collectively encapsulating a plurality of first semiconductor elements, the metal wires, and the plurality of second semiconductor packages in a second encapsulating resin, the second encapsulating resin having a linear expansion coefficient smaller than the linear expansion coefficient of the plurality of plate members; and
a step of dividing a plurality of multilayered semiconductor devices by cutting the second encapsulating resin.
10. The method of manufacturing a multilayered semiconductor device according to claim 9, wherein:
an area of each plate member is smaller than an area of the first wiring board seen from a direction perpendicular to a surface of the first wiring board;
each notch is formed by a plate body disposed within a region of the first wiring board and a protruding piece that protrudes from the plate body to a location of a connection pad disposed in a corner of the first wiring board among the plurality of connection pads;
the first fixing step includes fixing the plurality of first semiconductor packages to the plurality of plate bodies of the plurality of plate members, respectively; and
the second fixing step includes fixing the plurality of second semiconductor packages to the plurality of plate bodies of the plurality of plate members, respectively.
11. The method of manufacturing a multilayered semiconductor device according to claim 9, wherein, for each plane member, one surface of the plate member is bonded to the first semiconductor element by a bonding member, and another surface of the plate member is bonded to the first encapsulating resin of the second semiconductor package.
12. The method of manufacturing a multilayered semiconductor device according to claim 9, wherein:
the first fixing step includes supplying a sheet-like plate material in which the plurality of plate members are coupled onto the plurality of first semiconductor packages that have undergone a test; and
the step of dividing includes cutting the sheet-like plate material together with the second encapsulating resin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for producing a \u03c9-alkyl halide nitrile or \u03c9-halogen carboxylic acid, comprising:
a) reacting a malonic acid diester or cyanoacetic acid ester with a \u03b1,\u03c9-dihalogen alkane, wherein:
i) the two halogen atoms in said \u03b1,\u03c9-dihalogen alkane are separated by a chain of at least 3 carbon atoms;
ii) the reaction is carried out in the presence of one or more alkali carbonates or alkaline earth carbonates and a phase transfer catalyst with the constant removal of water formed during the reaction; and
iii) said one or more alkali carbonates or alkaline earth carbonates are, when added together, present in a molar ratio to the malonic acid diesters or cyanoacetic acid esters of greater than 0.6:1; and

b) saponifying and decarboxylating reaction products produced in step a).
2. The process of claim 1, wherein the saponification and decarboxylation are performed by adding a catalyst acid without the addition of a solvent.
3. The process of claim 1, wherein the reaction between said malonic acid diester or cyanoacetic acid ester and said \u03b1,\u03c9-dihalogen alkane takes place in a polar aprotic solvent and wherein said one or more alkali carbonates or alkaline earth carbonates are present in a molar ratio to the malonic acid diesters or cyanoacetic acid esters of greater than 1:1.
4. The process of claim 3, wherein said polar aprotic solvent is selected from the group consisting of: DMF, DMSO, dimethylacetamide or N-methylpyrrolidone.
5. The process of any one of claims 1\u20134, wherein said the malonic acid diesters or cyanoacetic acid esters, said \u03b1,\u03c9-dihalogen alkane, and said one or more alkali carbonates or alkaline earth carbonates are added in a ratio of 1:2.0\u20135.0:1.0\u20132.0.
6. The process of any one of claims 1\u20134, wherein a cyclic hydrocarbon or an aromatic hydrocarbon is used as an entrainer to remove reaction water.
7. The process of any one of claims 1\u20134, wherein a quaternary ammonium salt is used as said phase transfer catalyst.

1460743661-8df6aa97-4a47-49cf-a654-a5f0a39683ba

1. A laser drive circuit comprising:
a plurality of input channels configured to receive digital input channel signals;
at least one digital-to-analog converter, each input channel being assigned to at least one digital-to-analog converter, each digital-to-analog converter having a current input, a current output, and a digital data input, the digital-to-analog converter being configured to output an output current at the current output to amplify an input current at the current input by a current amplification as analog amplification, the digital-to-analog converter configured to convert a digital input value at the digital data input in the current amplification; and
a switching amplifier device, each input channel being connected to a switch input of the switching amplifier device,
wherein the current output of each digital-to-analog converter is connected to a current input of the switching amplifier device, and
wherein the switching amplifier device is configured to switch each output current of each digital-to-analog converter according to the input channel signal of the associated input channel, to sum it, and to output it amplified at least to one output of the switching amplifier device.
2. The laser drive circuit according to claim 1, further comprising at least one analog switch, wherein a current input of the at least one digital-to-analog converter is connected to the at least one analog switch.
3. The laser drive circuit according to claim 1, wherein a current output of at least one digital-to-analog converter is connectable to a current input of at least one additional digital-to-analog converter via a switch.
4. The laser drive circuit according to claim 2, wherein the current output of the at least one digital-to-analog converter is connectable to the current input of the additional digital-to-analog converter by the analog switch.
5. The laser drive circuit according to claim 2, wherein the at least one analog switch is connected to a first reference source to provide a first reference current andor to a second reference source to provide a second reference current, so that the first reference current or the second reference current is switchable to the analog input of the digital-to-analog converter by the analog switch.
6. The laser drive circuit according to claim 1, further comprising a master channel and a number of slave channels, in which one of the digital-to-analog converters is assigned to the master channel, wherein the current output of the digital-to-analog converter assigned to the master channel is connectable to the current inputs of the digital-to-analog converters assigned to the slave channels via a switch.
7. The laser drive circuit according to claim 1, further comprising a master channel and a number of slave channels, wherein each slave channel has a configurable logic, wherein the input channel signals of the slave channels are logically linkable by the configurable logic, particularly by an AND or OR or EXCLUSIVE operation, to the input signal of the master channel for switching by the switching amplifier device.
8. The laser drive circuit according to claim 1, wherein the switching amplifier device has a component for setting the amplification of the switching amplifier device, the component including switchable amplifier units connected parallel to one another.
9. The laser drive circuit according to claim 1, further comprising:
an oscillator whose output is connected to a switch input of the switching amplifier device to output a digital oscillator signal; and
an additional digital-to-analog converter, whose current output to output an additional output current is connected to a current input of the switching amplifier device,
wherein the switching amplifier device is formed to switch the additional output current in the oscillator signal clock, and also to sum it and to output it amplified at the at least one output.
10. The laser drive circuit according to claim 9, further comprising:
an additional analog switch, which is connected to an additional current input of the additional digital-to-analog converter and to the first reference source andor to the second reference source andor to one or more of the current outputs of the digital-to-analog converter.
11. The laser drive circuit according to claim 9, further comprising:
an additional configurable logic, whose output is connected to an input of the oscillator andor to the additional digital-to-analog converter,
wherein the additional configurable logic andor the oscillator is configured to change a gating of the oscillation of the oscillator andor an oscillator frequency of the oscillator andor an amplitude of the oscillator signal andor a phase of the oscillator signal by a logical linking of one or more input channel signals of the channels andor by control signals.
12. The laser drive circuit comprising digital-to-analog converters, each having a current input and a current output to set current values of partial currents that are switchable by digital channel signals, to provide a laser current pulse at least on the basis of a sum of the partial currents, wherein at least one current output of one of the digital-to-analog converters is connected to at least one current input of an additional digital-to-analog converter via an analog switch.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power supply apparatus comprising:
a first capacitor that is connected to a power supply line which supplies power to a fuel injection system and that suppresses fluctuations in voltage of the power supply line;
DC loads except the fuel injection system; and
a second capacitor that is parallel-connected to the DC loads to exclusively supply the power to the DC loads.
2. The power supply apparatus according to claim 1, wherein the second capacitor is charged by first switch means for passing a current through the power supply line and the second capacitor, after a predetermined time has elapsed since an engine is started.
3. The power supply apparatus according to claim 1, wherein the second capacitor is charged by charging control means for controlling charging of the second capacitor when or after an engine is started.
4. The power supply apparatus according to claim 3, wherein the charging control means has power supply suppressing means for suppressing a power supply amount per unit time to the second capacitor.
5. The power supply apparatus according to claim 4, wherein the power supply suppressing means uses a resistance.
6. The power supply apparatus according to claim 4, wherein the power supply suppressing means has second switch means, and the second switch means repeats charging of the second capacitor intermittently, and thereby reduces an average of the power supply amount per unit time.
7. The power supply apparatus according to claim 1, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
8. The power supply apparatus according to claim 1, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
9. The power supply apparatus according to claim 2, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
10. The power supply apparatus according to claim 3, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
11. The power supply apparatus according to claim 4, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
12. The power supply apparatus according to claim 5, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
13. The power supply apparatus according to claim 6, further comprising:
first check means for preventing the power from being supplied from the first capacitor to the second capacitor and the DC loads.
14. The power supply apparatus according to claim 2, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
15. The power supply apparatus according to claim 3, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
16. The power supply apparatus according to claim 4, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
17. The power supply apparatus according to claim 5, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
18. The power supply apparatus according to claim 6, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
19. The power supply apparatus according to claim 7, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.
20. The power supply apparatus according to claim 9, further comprising:
second check means for preventing the power from being supplied from the second capacitor to the power supply line.