Author: claimsbot

1. A semiconductor device comprising:
a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area; and
an insulation layer covering the first and second areas and having at least one void removing part formed at the insulation layer, the void removing part extending from the first area to the second area to prevent a void from being formed, wherein the void removing part has a groove shape or an opening that exposes the semiconductor chip when viewed from above the device.
2. The semiconductor device according to claim 1, further comprising: an adhesive film covering the first area.
3. The semiconductor device according to claim 1, wherein the void removing part has a cross shape or a straight line shape when viewed from above the device.
4. The semiconductor device according to claim 1, wherein the void removing part has a lattice shape when viewed from the above the device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for maintaining routes, applied in a communications network comprising multiple point of presence (PoP) groups, wherein each of the PoP groups comprises one or more PoP nodes, the method comprising:
issuing, by PoP nodes within the same PoP group, routing information of a same super prefix;
issuing, by PoP nodes within different PoP groups, routing information of different super prefixes;
acquiring, by each PoP node, routing information of a detailed prefix covered by a super prefix issued by the PoP node itself from an edge network of the PoP node, wherein the acquired routing information of the detailed prefix covered by the super prefix is preset in the PoP node that issues the routing information of the super prefix or registered by a border router in the communications network dynamically, and wherein dynamically registering, by the border router in the communications network, the routing information of the detailed prefix covered by the super prefix comprises: receiving, by the border router, the routing information of the super prefix issued by the PoP node, generating a routing table, recording an address of the PoP node that issues the routing information of the super prefix in the routing table, and registering, by the border router, the routing information of the detailed prefix within the connected edge network with a proximate PoP node that issues the routing information of the super prefix covering the detailed prefix; and
synchronizing, by each PoP node, the acquired routing information of the detailed prefix with the other PoP nodes within the same PoP group to make each PoP node to get routing information of all detailed prefixes covered by the super prefix.
2. The method according to claim 1, wherein the routing information of the super prefix issued by the PoP node is preset.
3. The method according to claim 1, wherein the routing information of the detailed prefix comprises the detailed prefix and a routable address, priority, and overhead information of the border router.
4. The method according to claim 1, further comprising forwarding a data packet, wherein the method comprises: hop-by-hop forwarding the data packet to the proximate PoP node that issues the routing information of the super prefix according to matching routing information of the super prefix, searching, by the proximate PoP node, a route optimally matching a destination IP address of the data packet in the routing table, determining an address of the border router corresponding to the optimal route, and sending the data packet to the border router in a tunnel mode.
5. The method according to claim 1 further comprising:
when the routing information of the detailed prefix within the edge network connected to a border router changes, performing registration update, by the border router, to a proximate PoP node that issues the routing information of the super prefix covering the detailed prefix; and
after the proximate PoP node receives the registration update, updating the routing information of the detailed prefix maintained by the proximate PoP node, and spreading the routing information update to other PoP nodes within the PoP group corresponding to the super prefix.
6. The method according to claim 1 further comprising:
when the routing information of the detailed prefix within the edge network connected to the border router changes, performing registration update, by the border router, to the proximate PoP node that issues the routing information of the super prefix covering the detailed prefix; and
after the proximate PoP node receives the registration update, updating the routing information of the detailed prefix maintained by the proximate PoP node, and spreading the routing information update to other PoP nodes within the PoP group corresponding to the super prefix.
7. The method according to claim 1, wherein the PoP nodes within the same PoP group synchronize routing information by using the Border Gateway Protocol (BGP).
8. A point of presence (PoP) node for maintaining routes, comprising:
a route maintenance module that stores routing information of a super prefix;
an issue module that issues routing information of a super prefix stored in the route maintenance module, wherein the routing information of a same super prefix is issued within the same PoP group, and the routing information of different super prefixes is issued within different PoP groups;
a receiver implemented in hardware that receives routing information of a detailed prefix covered by a super prefix issued by the PoP node itself from an edge network of the PoP node, and stores the received routing information of the detailed prefix in the route maintenance module; and
a synchronization module that synchronizes the routing information of the detailed prefix stored in the route maintenance module with other PoP nodes within the same PoP group to make each PoP node to get routing information of all detailed prefixes covered by the super prefix,
wherein the received routing information of the detailed prefix covered by the super prefix is preset in the PoP node that issues the routing information of the super prefix or registered by a border router in the communications network dynamically, and
wherein dynamically registering, by the border router in the communications network, the routing information of the detailed prefix covered by the super prefix comprises: receiving, by the border router, the routing information of the super prefix issued by the PoP node, generating a routing table, recording an address of the PoP node that issues the routing information of the super prefix in the routing table, and registering, by the border router, the routing information of the detailed prefix within the connected edge network with a proximate PoP node that issues the routing information of the super prefix covering the detailed prefix.

1. A method for reducing serum glucose levels in a human diabetic patient in need thereof, comprising administering to said patient a therapeutically effective amount of colesevelam or a pharmaceutically acceptable salt thereof.
2. A method for reducing serum glucose levels in a human diabetic patient in need thereof, comprising administering to said patient a therapeutically effective amount of colesevelam or a pharmaceutically acceptable salt thereof, wherein said colesevelam or pharmaceutically acceptable salt thereof is the only active ingredient administered to the patient.
3. The method of claim 1, wherein a pharmaceutically acceptable salt of colesevelam is administered to the patient.
4. The method of claim 2, wherein a pharmaceutically acceptable salt of colesevelam is administered to the patient.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a GaAs-based substrate; and
a quantum well structure formed on the GaAs-based substrate and including a quantum well layer, a pair of first barrier layers facing each other with the quantum well layer therebetween, and a pair of second barrier layers adjacent to the respective first barrier layers.
2. The semiconductor device according to claim 1, wherein the wavelength of light generated in the quantum well structure is adjusted by varying the thicknesses and compositions of the first barrier layers and the second barrier layers.
3. The semiconductor device according to claim 1, wherein each of the first barrier layers has a thickness ranging from 0.1 nm to 50 nm.
4. The semiconductor device according to claim 1, wherein each of the second barrier layers has a thickness ranging from 0.1 nm to 50 nm.
5. The semiconductor device according to claim 1, wherein the quantum well layer contains GaxIn1-xNyAs1-y where x and y are greater than 0 and smaller than 1.
6. The semiconductor device according to claim 1, wherein the first barrier layers contain InxGa1-xAs where x is greater than 0 and smaller than 1.
7. The semiconductor device according to claim 1, wherein the second barrier layers contain GaNxAs1-x where x is greater than 0 and smaller than 1.
8. The semiconductor device according to claim 1, wherein the quantum well layer is a multi-quantum well layer comprising a plurality of well layers composed of GaInNAs and a plurality of barrier layers alternating with the well layers.
9. The semiconductor device according to claim 8, wherein each of the well layers has a thickness ranging from 2 nm to 10 nm.
10. The semiconductor device according to claim 8, wherein the plurality of barrier layers contain GaAs.
11. The semiconductor device according to claim 10, wherein the plurality of barrier layers contain GaNAs.
12. The semiconductor device according to claim 1, wherein compressive strain is induced in the quantum well layer by the first barrier layers.
13. The semiconductor device according to claim 1, wherein tensile strain is induced in the quantum well layer by the second barrier layers.
14. The semiconductor device according to claim 1, wherein the quantum well layer contains GaxIn1-xNyAs1-y where x and y are greater than 0 and smaller than 1, the compressive strain of the quantum well layer is controlled by adjusting the amount of In in the first barrier layers, and the tensile strain of the quantum well layer is controlled by adjusting the amount of N in the second barrier layers.
15. An edge-emitting semiconductor laser comprising:
a GaAs-based substrate;
a quantum well structure formed on the GaAs-based substrate;
a cladding layer surrounding the quantum well structure; and
a pair of electrodes electrically connected to the cladding layer,
wherein the quantum well structure comprises a quantum well layer, a pair of first barrier layers facing each other with the quantum well layer therebetween, and a pair of second barrier layers adjacent to the respective first barrier layers.
16. A vertical cavity surface emitting laser comprising:
a GaAs-based substrate;
a first distributed Bragg reflection region formed on the GaAs-based substrate;
a quantum well structure formed on the first DBR (distributed Bragg reflection) region;
a second DBR region formed on the quantum well structure; and
a pair of electrodes electrically connected to the first and second DBR regions,
wherein the quantum well structure comprises a quantum well layer, a pair of first barrier layers facing each other with the quantum well layer therebetween, and a pair of second barrier layers adjacent to the respective first barrier layers.
17. The vertical cavity surface emitting laser according to claim 16, wherein the quantum well layer contains GaxIn1-xNyAs1-y where x and y are greater than 0 and smaller than 1.
18. The vertical cavity surface emitting laser according to claim 16, wherein the first barrier layers contain InxGa1-xAs where x is greater than 0 and smaller than 1.
19. The vertical cavity surface emitting laser according to claim 16, wherein the second barrier layers contain GaNxAs1-x where x is greater than 0 and smaller than 1.
20. The vertical cavity surface emitting laser according to claim 16, wherein the quantum well layer is a multi-quantum well layer comprising a plurality of well layers composed of GaInNAs and a plurality of barrier layers alternating with the well layers.
21. The vertical cavity surface emitting laser according to claim 20, wherein each of the well layers has a thickness ranging from 2 nm to 10 nm.
22. The vertical cavity surface emitting laser according to claim 16, wherein compressive strain is induced in the quantum well layer by the first barrier layers.
23. The vertical cavity surface emitting laser according to claim 16, wherein tensile strain is induced in the quantum well layer by the second barrier layers.
24. The vertical cavity surface emitting laser according to claim 16, wherein each of the first barrier layers has a thickness ranging from 0.1 nm to 50 nm.
25. The vertical cavity surface emitting laser according to claim 16, wherein each of the second barrier layers has a thickness ranging from 5 nm to 50 nm.
26. A method of manufacturing a semiconductor device, the method comprising:
preparing a GaAs-based substrate;
forming a second lower barrier layer on the GaAs-based substrate;
forming a first lower barrier layer on the second lower barrier layer;
forming a quantum well layer on the first lower barrier layer;
forming a first upper barrier layer on the quantum well structure; and
forming a second upper barrier layer on the first upper barrier layer.
27. The method according to claim 26, wherein the quantum well layer contains GaxIn1-xNyAs1-y where x and y are greater than 0 and smaller than 1.
28. The method according to claim 26, wherein the first lower and upper barrier layers contain InxGa1-xAs where x is greater than 0 and smaller than 1.
29. The method according to claim 26, wherein the second lower and upper barrier layers contain GaNxAs1-x where x is greater than 0 and smaller than 1.
30. The method according to claim 26, wherein the quantum well layer has a thickness ranging from 2 nm to 10 nm.
31. The method according to claim 26, wherein compressive strain is induced in the quantum well layer by the first lower and upper barrier layers.
32. The method according to claim 26, wherein tensile strain is induced in the quantum well layer by the second lower and upper barrier layers.
33. The method according to claim 26, wherein each of the first lower and upper barrier layers has a thickness ranging from 0.1 nm to 50 nm.
34. The method according to claim 26, wherein each of the second lower and upper barrier layers has a thickness ranging from 0.1 nm to 50 nm.