1. A loop-back extender card comprising:
a substrate containing wiring traces for conducting signals;
first contact pads along a first edge of the substrate, the first contact pads for mating with a memory module socket on a motherboard;
a test socket, mounted to the substrate, for receiving a memory module during testing;
wherein the memory module contains memory chips and a buffer chip; wherein the buffer chip buffers data from the memory chips to the test socket and the memory chips do not directly drive data to the test socket;
northbound-lane module inputs, on the test socket, for connecting to northbound-lane inputs of the buffer chip on the memory module, the northbound-lane module inputs being differential inputs for carrying data buffered from memory chips of downstream memory modules;
northbound-lane module outputs, on the test socket, for connecting to northbound-lane outputs of the buffer chip on the memory module, the northbound-lane module outputs being differential outputs for carrying data buffered from the memory chips;
a northbound loopback, in the wiring traces, that connects the northbound-lane module outputs on the test socket to corresponding northbound-lane module inputs on the test socket,
northbound-lane motherboard inputs, on the first contact pads, that are disconnected from the test socket; and
northbound-lane motherboard outputs, on the first contact pads, that are disconnected from the test socket,
whereby northbound lanes from the test socket are looped back and disconnected from northbound lanes on the motherboard.
2. The loop-back extender card of claim 1 further comprising:
southbound-lane module inputs, on the test socket, for connecting to southbound-lane inputs of the buffer chip on the memory module, the southbound-lane module inputs being differential inputs for carrying data from a processor on the motherboard to the memory chips or to the memory chips of downstream memory modules;
southbound-lane module outputs, on the test socket, for connecting to southbound-lane outputs of the buffer chip on the memory module, the southbound-lane module outputs being differential outputs for carrying data from the processor to the memory chips of downstream memory modules;
a southbound loopback, in the wiring traces, that connects the southbound-lane module outputs on the test socket to corresponding southbound-lane module inputs on the test socket,
southbound-lane motherboard inputs, on the first contact pads, that are disconnected from the test socket;
southbound-lane motherboard outputs, on the first contact pads, that are disconnected from the test socket,
whereby northbound lanes and southbound lanes are separately looped back to the test socket by the loop-back extender card.
3. The loop-back extender card of claim 2 further comprising:
pass-through control signal traces in the wiring traces, the pass-through control signal traces connecting control signals on the first contact pads to control signals in the test socket,
whereby pass-through control signals are passed through to the memory module.
4. The loop-back extender card of claim 3 wherein the control signals include a differential clock, a reset signal, and a control signal for activating a test mode of the buffer chip, the test mode for generating test signals on the northbound-lane module outputs.
5. The loop-back extender card of claim 4 wherein the control signals further comprise serial-presence-detect (SPD) signals that control a serial-presence-detect (SPD) electrically-erasable programmable read-only memory (EEPROM) on the memory module.
6. The loop-back extender card of claim 3 wherein the northbound loopback comprises:
a plurality of serpentine traces, in the wiring traces, the plurality of serpentine traces having lengths substantially longer than lengths of the pass-through control signal traces,
whereby serpentine traces form the northbound loopback.
7. The loop-back extender card of claim 6 wherein the serpentine traces are each more than double an average length of the pass-through control signal traces.
8. The loop-back extender card of claim 6 wherein the southbound loopback comprises:
a second plurality of serpentine traces, in the wiring traces, the second plurality of serpentine traces having lengths substantially longer than lengths of the pass-through control signal traces,
whereby serpentine traces form the southbound loopback.
9. The loop-back extender card of claim 3 wherein the northbound loopback further comprises:
a plurality of series resistors, having a series resistor inserted into each of the plurality of wiring traces in the northbound loopback,
wherein the southbound loopback further comprises:
a plurality of series resistors, having a series resistor inserted into each of the plurality of wiring traces in the southbound loopback,
whereby loopback series resistance is increased by the plurality of series resistors.
10. The loop-back extender card of claim 3 wherein the buffer chip is an Advanced Memory Buffer (AMB).
11. The loop-back extender card of claim 3 wherein the memory module is a fully-buffered memory module wherein memory chips on the memory module have data outputs that connect to the buffer chip and do not connect to an edge connector of the memory module that fits into the test socket.
12. The loop-back extender card of claim 3 wherein the northbound-lane module inputs are for receiving frames being sent toward a processor on the motherboard in a daisy chain of memory modules;
wherein the southbound-lane module inputs are for receiving frames being sent from the processor on the motherboard in the daisy chain of memory modules.
13. The loop-back extender card of claim 3 wherein the northbound loopback comprises 14 differential pairs of wiring traces that carry 14 bits in parallel on 28 wiring traces and wherein the southbound loopback comprises 10 differential pairs of wiring traces that carry 10 bits in parallel on 20 wiring traces.
14. The loop-back extender card of claim 3 wherein the southbound loopback and the northbound loopback comprise differential pairs of wiring traces that carry multiple bits in parallel on wiring traces, further comprising:
a first plurality of shunt resistors, having a shunt resistor inserted across each differential pair of wires in the plurality of wiring traces in the northbound loopback,
wherein the southbound loopback further comprises:
a second plurality of shunt resistors, having a shunt resistor inserted across each differential pair of wires in the plurality of wiring traces in the southbound loopback, whereby loopback shunt resistance is provided.
15. The loop-back extender card of claim 3 wherein the test socket is a zero-insertion-force (ZIF) test socket.
16. A motherboard-based memory-module tester comprising:
a personal computer motherboard having a microprocessor for executing programs;
a memory controller on the personal computer motherboard for generating frames for reading and writing user data to a memory module under test;
a plurality of memory module sockets on the personal computer motherboard for receiving memory modules;
wherein the memory modules each contain memory chips and a buffer chip;
wherein the buffer chip buffers data from the memory chips into frames to the memory controller and the memory chips do not directly drive data to the memory controller unless packaged into a frame by the buffer chip;
an extender card having lower contact pads for fitting into one of the plurality of memory module sockets;
wherein the lower contact pads comprise differential lane contacts for connecting to the memory controller or to other memory module sockets in a daisy chain of memory module sockets, the differential lane contacts for passing frames to and from the buffer chip;
a test socket on the extender card for receiving the memory module under test, the test socket comprising differential data input lines for connecting to data inputs of the buffer chip, and differential data output lines for connecting to data outputs of the buffer chip;
wiring traces on the extender card for passing control signals through from the lower contact pads to the test socket, the control signals being generated by the personal computer motherboard;
loopback wiring traces that connect the differential data output lines in the test socket to the differential data input lines of the test socket;
wherein the differential lane contacts of the lower contact pads do not connect to the test socket,
whereby the differential data output lines are looped back to the differential data output lines by the loopback wiring traces on the extender card.
17. The motherboard-based memory-module tester of claim 16 wherein the differential data output lines comprise northbound lanes for passing frames toward the memory controller in the daisy chain and southbound lanes for passing frames generated by the memory controller.
18. The motherboard-based memory-module tester of claim 16 wherein the memory chips are dynamic-random-access memory (DRAM) chips.
19. A test extender card for loopback testing of fully-buffered memory modules, the test extender card comprising:
substrate means for supporting wiring trace means for conducting signals;
first contact pads means, along a first edge of the substrate means, for mating with a memory module socket on a motherboard;
test socket means, mounted to the substrate means, for receiving a memory module during testing;
wherein the memory module comprises memory chips and buffer chip means for buffering data from the memory chips to the test socket means;
wherein the memory chips do not directly drive data to the test socket means;
northbound-lane module input means, on the test socket means, for connecting to northbound-lane inputs of the buffer chip means on the memory module, the northbound-lane input means having differential input means for carrying data buffered from memory chips of downstream memory modules;
northbound-lane module output means, on the test socket means, for connecting to northbound-lane outputs of the buffer chip means on the memory module, the northbound-lane output means having differential outputs for carrying data buffered from the memory chips;
northbound loopback means, in the wiring trace means, for connecting the northbound-lane module output means on the test socket means to corresponding northbound-lane module input means on the test socket means,
northbound-lane motherboard inputs, on the first contact pads means, that are disconnected from the test socket means; and
northbound-lane motherboard outputs, on the first contact pads means, that are disconnected from the test socket means,
whereby northbound lanes from the test socket means are looped back and disconnected from northbound lanes on the motherboard.
20. The test extender card of claim 19 further comprising:
southbound-lane module input means, on the test socket means, for connecting to southbound-lane inputs of the buffer chip means on the memory module, the southbound-lane inputs being differential inputs for carrying data from a processor to the memory chips or to the memory chips of downstream memory modules;
southbound-lane module output means, on the test socket means, for connecting to southbound-lane outputs of the buffer chip means on the memory module, the southbound-lane outputs being differential outputs for carrying data from the processor to the memory chips of downstream memory modules;
southbound loopback means, in the wiring trace means, for connecting the southbound-lane module output means on the test socket means to corresponding southbound-lane module input means on the test socket means,
southbound-lane motherboard inputs, on the first contact pads means, that are disconnected from the test socket means;
southbound-lane motherboard outputs, on the first contact pads means, that are disconnected from the test socket means,
whereby northbound lanes and southbound lanes are separately looped back to the test socket means by the extender card.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A heterocyclically substituted benzoylguanidine of the formula I
4
in which:
R(1) is (CF2)cCF3;
c is zero, 1, 2 or 3;
R(2) is (C1-C9)-heteroaryl, linked via C or N, which is unsubstituted or substituted by 1-3 substituents selected from the group consisting of F, Cl, CF3, CH3, methoxy, hydroxyl, amino, methylamino and dimethylamino;
R(3) is H, F, Cl, Br, I, CN, NO2 or (C1-C8)-alkyl;
R(4) is H, (C1-C4)-alkyl, (C1-C4)-alkoxy, F, Cl, Br, I, CN or (CF2)oCF3;
o is zero, 1 or2;
or a pharmaceutically tolerable salt thereof.
2. A compound of claim 1, wherein:
R(1) is trifluoromethyl;
R(2) is imidazolyl or benzimidazolyl, linked via C or N, each of which is unsubstituted or substituted by 1-3 substituents selected from the group consisting of F, Cl, CF3, CH3, methoxy, hydroxyl, amino, methylamino and dimethylamino;
R(3) is H, F, Cl or (C1-C4)-alkyl;
R(4) is H, (C1-C4)-alkyl, (C1-C4)-alkoxy, F, Cl or CF3.
3. A compound of claim 1, wherein:
R(1) is trifluoromethyl;
R(2) is imidazolyl or benzimidazolyl, linked via N, each of which is unsubstituted or substituted by 1-3 substituents selected from the group consisting of F, Cl, CF3, CH3 and methoxy;
R(3) is H;
R(4) is H, methyl, methoxy, Cl or CF3.
4. A process for preparing a compound I of claim 1, which comprises reacting a compound of the formula II
5
in which R(1) to R(4) have the meaning indicated and L is an easily nucleophilically substitutable leaving group, with guanidine.
5. A method of treating or preventing an illness caused by an ischemic condition, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment or prevention.
6. A method of treating or preventing cardiac infarct, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment or prevention.
7. A method of treating or preventing angina pectoris, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment or prevention.
8. A method for the treatment or prevention of an ischemic condition of the heart, comprising administering an effective amount of a compound of claim 1 to a host in need of each treatment or prevention.
9. A method for the treatment or prevention of stroke or of an ischemic condition of the peripheral or central nervous system, which comprises administering an effective amount of a compound of claim 1 to a host in need of such treatment or prevention.
10. A method for the treatment or prevention of an ischemic condition of the peripheral organs or limbs, comprising administering an effective amount of a compound of claim 1 to a host need of such treatment or prevention.
11. A method of treating or preventing a state of shock, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment or prevention.
12. A method of protecting a transplant organ during surgical operation or organ transplantations, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment.
13. A method of preserving or protecting organ transplants for surgical measures, comprising bringing an effective amount of a compound of claim 1 into contact with the organ transplant.
14. A method of treating an illness in which cell proliferation is a primary or secondary cause, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment.
15. A method of treating or protecting a disorder of fat metabolism, comprising administering an effective amount of a compound of claim 1 to a host in need of such treatment or protection.
16. A pharmaceutical composition, comprising a compound of claim 1 and a pharmaceutically acceptable carrier.