Author: claimsbot

1. A wiring board comprising:
an insulating board including a land conductor layer on a surface thereof;
an insulating layer formed on the insulating board;
a via hole reaching the land conductor layer from an upper surface of the insulating layer;
a via conductor formed in the via hole and formed of a plated metal layer; and
a wiring conductor formed on the via conductor and electrically connected to the via conductor,
wherein the via hole is provided with a protruding portion formed of copper foil and protruding from a periphery of an opening of the via hole toward a center of the opening.
2. The wiring board according to claim 1,
wherein the protruding portion protrudes from the periphery of the opening of the via hole toward the center of the opening by an amount of 3 to 15 \u03bcm.
3. The wiring board according to claim 1,
wherein the via conductor and the wiring conductor are formed integrally with the plated metal layer.
4. A method for manufacturing a wiring board, the method comprising the steps of:
sequentially laminating an insulating layer and copper foil on an insulating board including a land conductor layer on a surface thereof;
forming a via hole reaching the land conductor layer from an upper surface of the copper foil such that the via hole is provided with a protruding portion formed of the copper foil and protruding from a periphery of an opening of the via hole toward a center of the opening;
forming, on the copper foil, a plating resist layer including an opening portion for exposing the via hole and a periphery thereof;
forming a via conductor formed of a plated metal layer in the via hole and forming a wiring conductor in the opening portion of the plating resist layer; and
removing the plating resist layer and the copper foil in a portion covered with the plating resist layer.
5. The method for manufacturing a wiring board according to claim 4 further comprising a step of etching a surface of the copper foil after the step of forming the via hole.
6. The manufacturing method according to claim 4,
wherein the protruding portion protrudes from the periphery of the opening of the via hole toward the center of the opening by an amount of 3 to 15 \u03bcm.
7. The manufacturing method according to claim 4,
wherein the via conductor and the wiring conductor are formed integrally with the plated metal layer.
8. The manufacturing method according to claim 4,
wherein the copper foil is roughened.
9. The manufacturing method according to claim 4,
wherein the via hole provided with the protruding portion is formed by laser irradiation.
10. The manufacturing method according to claim 9, wherein
the laser irradiation is divided into two steps, and energy of laser irradiation in a second step is set weaker than that in a first step.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A timing control method for operating a synchronous memory, wherein the synchronous memory has a local data bus, a signal amplification bus, and a global data bus, the timing control method comprising the steps of:
providing a synchronous timing such that following operations are carried out in a (n+1)th clock cycle of the synchronous timing;
reading and decoding the (a+1)th address;
pre-charging the local data bus that stores the ath bath of local data into an initial value in a local data bus pre-charging period;
amplifying and transferring the ath batch of global data from the signal amplification bus to the global data bus in a global data transmission period;
transferring the (a+1)th batch of local data to the local data bus in a non-local data bus pre-charging period;
pre-charging the signal amplification bus and the global data bus that stores the ath batch of global data into an initial value in a signal amplification bus pre-charging period after temporarily storing the ath batch of global data to a register; and
transferring the (a+1)th batch of local data from the local data bus to the signal amplification bus.
2. The method of claim 1, wherein the following operations are carried out in the nth clock cycle of the synchronous timing:
reading out an address value;
decoding the address value; and
retrieving local bus data from a location corresponding to the address provided by the decoding operation.
3. The method of claim 2, wherein the ath batch of local data is put on the local data bus in the non-local data bus pre-charging period after the address value is decoded, a column select is within the address value decoding termination cycle and other signals corresponding to the column select is within the address value decoding termination cycle.
4. The method of claim 1, wherein after the transfer of the ath batch of global data from the signal amplification bus to the global data bus, further includes storing the ath batch of global data in a register within the synchronous memory.
5. The method of claim 4, wherein after the transfer of the ath batch of global data into the register, further includes outputting the ath batch of global data from the register in the (n+2)th cycle of the synchronous timing.
6. The method of claim 1, wherein the step of putting the (a+1)th batch of local data on the local data bus requires a signal developing time for transforming the (a+1)th batch of local data into the (a+1)th batch of local data pair.
7. The method of claim 6, wherein length of the signal developing time is the period between the transition of the local data bus pre-charging period into the non-local data bus pre-charging period and the transition from the non-global data transmission period into the global data transmission period.

1. An apparatus, comprising:
a plurality of modules, at least some of the plurality of modules including a plurality of stacked dice, each of the plurality of stacked dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the plurality of modules; and
a Package-on-Package (PoP) structure coupling the plurality of modules to one another such that an individual access to each CE signal connection associated with the PoP structure is provided from the surface of the corresponding module.
2. The apparatus of claim 1, wherein the plurality of stacked dice comprises memory dice.
3. The apparatus of claim 2, wherein the plurality of memory dice includes at least one type of memory device selected from devices including a Phase Change Memory (PCM) device, a Magnetic Random Access Memory (MRAM) device, and a Ferroelectric Random Access Memory (FRAM) device.
4. The apparatus of claim 1, wherein each of the plurality of stacked dice is individually accessible via a unique CE signal, the unique being defined as a CE signal provided to at least one of the CE signal connections to access specific ones of each of the plurality of stacked dice individually.
5. The apparatus of claim 4, wherein the unique CE signal is configured to control a specific one of the plurality of stacked dice.
6. The apparatus of claim 1, wherein the PoP structure includes individual access contacts to each of the separate CE signal connections of the corresponding module.
7. The apparatus of claim 1, wherein at least some of the plurality of modules include a mold having at least one filled via extending from a first surface of the mold to a second opposing surface of the mold.
8. The apparatus of claim 1, wherein at least some of the plurality of modules include a mold having at least one laminate board with electrical traces thereon and extending from a first surface of the mold to a second opposing surface of the mold.
9. The apparatus of claim 1, wherein each of the plurality of stacked dice is arranged in a staggered configuration relative to an adjacent one of the dice to allow physical access to a corresponding one of the CE signal connections.
10. The apparatus of claim 9, wherein the CE signal connections of the adjacent ones of the dice are located on opposing edges of each subsequent die in the stack.
11. The apparatus of claim 1, wherein each of the plurality of stacked dice is rotated approximately 90 degrees relative to an adjacent one of the dice to allow physical access to a corresponding one of the CE signal connections.
12. An apparatus, comprising:
a plurality of stacked memory dice encapsulated in a mold, at least some of the plurality of stacked memory dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the stacked memory dice, each of the plurality of stacked memory dice having the CE signal connection being configured to be controlled individually by a unique CE signal applied to the CE signal connection, the unique CE signal being defined as a CE signal provided to at least one of the CE signal connections to access specific ones of the at least some of the plurality of stacked dice individually; and
a single CE signal connection located on a surface of the mold and coupled to each of the CE signal connections on the surfaces of corresponding ones of the plurality of memory dice.
13. An apparatus, comprising a plurality of modules attached to each other to form a Package-on-Package (PoP) structure, at least one module of the plurality of modules including a plurality of memory dice stacked over one another, each of the plurality of memory dice including a Chip Enable (CE) signal connection, each of the plurality of memory dice being controllable individually by a unique CE signal, the unique CE signal being defined as a CE signal provided to at least one of the CE signal connections to access specific ones of each of the plurality of stacked dice individually, each of the CE signal connections being coupled to a different connection at a bottom surface of the at least one module via an electrical trace in a package substrate arranged to support the plurality of memory dice.
14. The apparatus of claim 13, wherein each of the plurality of modules is interchangeable in the PoP structure with another one of the plurality of modules, with respect to providing individual access to each CE signal connection in the PoP structure.
15. The apparatus of claim 13, wherein the at least one module includes a mold having at least one filled, electrically-conductive via extending from a first surface of the mold to a second, opposing surface of the mold and electrically coupled to a first surface of the PoP structure.
16. The apparatus of claim 13, wherein the first surface of the PoP structure includes a plurality of solder balls, at least some of the solder balls being configured to couple each of the CE signal connections on the plurality of memory dice to a host controller.
17. An apparatus, comprising:
a plurality of modules, at least some of the plurality of modules including a plurality of stacked dice, at least some of the plurality of stacked dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the plurality of modules, at least some of the plurality of modules including a mold having at least one filled via extending from a first surface of the mold to a second opposing surface of the mold; and
a Package-on-Package (PoP) structure coupling the plurality of modules to one another such that an individual access to each CE signal connection associated with the PoP structure is provided from the surface of the corresponding module.
18. An apparatus, comprising:
a plurality of modules, at least some of the plurality of modules including a plurality of stacked dice, at least some of the plurality of stacked dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the plurality of modules, at least some of the plurality of modules including a mold having at least one laminate board with electrical traces thereon and extending from a first surface of the mold to a second opposing surface of the mold; and
a Package-on-Package (PoP) structure coupling the plurality of modules to one another such that an individual access to each CE signal connection associated with the PoP structure is provided from the surface of the corresponding module.
19. An apparatus, comprising:
a plurality of modules, at least some of the plurality of modules including a plurality of stacked dice, at least some of the plurality of stacked dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the plurality of modules, each of the plurality of stacked dice being arranged in a staggered configuration relative to an adjacent one of the dice to allow physical access to a corresponding one of the CE signal connections; and
a Package-on-Package (PoP) structure coupling the plurality of modules to one another such that an individual access to each CE signal connection associated with the PoP structure is provided from the surface of the corresponding module.
20. An apparatus, comprising:
a plurality of modules, at least some of the plurality of modules including a plurality of stacked dice, at least some of the plurality of stacked dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the plurality of modules, each of the plurality of stacked dice being rotated approximately 90 degrees relative to an adjacent one of the dice to allow physical access to a corresponding one of the CE signal connections; and
a Package-on-Package (PoP) structure coupling the plurality of modules to one another such that an individual access to each CE signal connection associated with the PoP structure is provided from the surface of the corresponding module.
21. An apparatus, comprising:
a plurality of stacked memory dice encapsulated in a mold, at least some of the plurality of stacked memory dice including a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the stacked memory dice, each of the plurality of stacked memory dice having the CE signal connection being configured to be controlled individually by a unique CE signal applied to the CE signal connection, the unique CE signal being defined as a CE signal provided to at least one of the CE signal connection to access specific ones of each of the plurality of stacked dice individually; and
separate CE signal connections located on a surface of the mold and individually coupled to corresponding ones of each of the CE signal connections on the surfaces of the plurality of memory dice.
22. An apparatus, comprising a plurality of modules attached to each other to form a Package-on-Package (PoP) structure, at least one module of the plurality of modules including a plurality of memory dice stacked over one another, each of the plurality of memory dice including a Chip Enable (CE) signal connection, each of the plurality of modules being interchangeable in the PoP structure with another one of the plurality of modules, with respect to providing individual access to each CE signal connection in the PoP structure, each of the plurality of memory dice being controllable individually by a unique CE signal, the unique CE signal being defined as a CE signal provided to at least one of the CE signal connection to access specific ones of each of the plurality of stacked dice individually.
23. An apparatus, comprising a plurality of modules attached to each other to form a Package-on-Package (PoP) structure, at least one module of the plurality of modules including a plurality of memory dice stacked over one another, the at least one module including a mold having at least one filled, electrically-conductive via extending from a first surface of the mold to a second, opposing surface of the mold and electrically coupled to a first surface of the PoP structure, each of the plurality of memory dice including a Chip Enable (CE) signal connection, each of the plurality of memory dice being controllable individually by a unique CE signal, the unique CE signal being defined as a CE signal provided to at least one of the CE signal connection to access specific ones of each of the plurality of stacked dice individually.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device, comprising:
a backing layer with an exterior side and an interior side;
one or more light sources;
a flexible circuit strip or board affixed to the interior side of the backing layer, wherein the light sources are mounted on said flexible circuit strip or board;
a power source providing electrical power to said light sources; and
an adhesive layer applied to the interior side of said backing layer.
2. The device of claim 1, wherein said light sources are LEDs.
3. The device of claim 1, wherein said light sources are pico-LEDs.
4. The device of claim 1, wherein said power source is a thin film battery.
5. The device of claim 1, wherein said power source is a solar cell.
6. The device of claim 1, wherein there is a single light source.
7. The device of claim 1, wherein the light sources are arranged in one or more lines.
8. The device of claim 1, wherein the adhesive layer is hydrogel.
9. The device of claim 1, wherein the adhesive layer is not applied over the light sources.
10. The device of claim 1, wherein the device is adapted to be placed on the human epidermis.
11. The device of claim 10, wherein the light sources are no more than 1 mm distant from the epidermis when the device is placed on the human epidermis.
12. The device of claim 1, wherein the light sources are identical in color and intensity.
13. The device of claim 1, wherein the light sources vary in color and intensity.
14. The device of claim 1, wherein one or more light sources are strobing.
15. The device of claim 1, further comprising a microchip processor or controller mounted or embedded in said flexible circuit strip or board.
16. The device of claim 15, wherein said microchip processor or controller is programmed to control the color and intensity of the light sources.
17. The device of claim 1, further comprising a switch to turn the light sources on or off.