Author: claimsbot

1-12. (canceled)
13. A testing arrangement for testing the electrical circuits of a terminal block assembly (3), comprising at least one testing unit (200) including:
(a) a generally rectangular testing unit housing (23) formed of insulating material, said housing including vertical pairs of side and end walls, and horizontal top and bottom walls, said walls defining a chamber contained within said housing;
(b) at least one connection device (42) mounted in said housing chamber, said connection device including:
(1) an elongated connector body formed of insulating material and having center and end portions, said connector body including:
(a) an integral measuring tab portion (24) extending downwardly from said connector body center portion, and outwardly from said testing unit housing via an opening contained in said housing bottom wall, said tab portion being adapted for insertion into a testing opening contained in the terminal block assembly;
(b) a pair of coplanar measurement portions (29) extending upwardly from said connector body end portions, respectively, via corresponding openings contained in said testing unit housing; and

(2) a testing circuit at least partially mounted on said connection device, said testing circuit including:
(a) an electrical testing component (33) having a pair of end terminals;
(b) a pair of input conductive contact plates (24c, 24d) mounted on opposite sides of said measuring tab portion for connection with the terminals of an electrical circuit of said terminal block assembly that is to be tested; and
(c) a pair of conductive connecting paths connecting said contact plates with said testing component end terminals, respectively, each of said conductive arrangements including a bus bar section arranged within said elongated connector body, and a contact carried by an associated one of said measurement portions;
(c) said measurement portions terminating in upper tip portions (291) that are at different elevations relative to each other, thereby to afford a compact assembly of said testing arrangement.
14. A testing arrangement as defined in claim 13, wherein said connector body measurement portions comprise hollow sockets adapted for connection with probe heads (37), respectively.
15. A testing arrangement as defined in claim 14, wherein said connector body is vertically displaceable to different height levels (47, 48, 49) relative to said housing.
16. A testing arrangement as defined in claim 15, and further including a fixed pin (35) and detent slot (34) arrangement for determining the vertical position of said connector body relative to said housing.
17. A testing arrangement as defined in claim 13, wherein said connector body measurement portions are arranged at an acute angle (44) relative to each other.
18. A testing arrangement as defined in claim 17, wherein a first one of said connector body measurement portions is vertical.
19. A testing arrangement as defined in claim 18, wherein said a second one of said body portions (30) is horizontal and extends through a vertical slot contained in an associated side wall of said housing.
20. A testing arrangement as defined in claim 13, wherein a plurality of said connection devices are arranged in side-by-side relation within said housing chamber.
21. A testing arrangement as defined in claim 13, wherein a plurality of said testing units are arranged in side-by-side relation.
22. A testing arrangement as defined in claim 21, wherein said testing units are arranged in vertically-offset relation.
23. A testing arrangement as defined in claim 21, wherein at least some of said testing units are arranged in successive mirror image vertical-axis 180-degree-rotated relation, thereby to achieve compact assembly of said testing units when measuring probes heads (37) are attached thereto.
24. A testing arrangement as defined in claim 23, wherein said contact plates (24d) are arranged on opposite sides of a vertical transverse plane extending through said measuring tab; and further wherein the connector measurement portions of each testing unit area are angularly arranged opposite ends of the associated connection device elongated body to define an angle (44).
25. A testing arrangement as defined in claim 24, wherein the connector portions of each test unit have the same angular relationship.
26. A testing arrangement as defined in claim 25, wherein corresponding connector portions of the test units have the same length.
27. A testing arrangement as defined in claim 23, wherein said measuring tab is adapted for insertion between the leaf spring contacts of an associated terminal block assembly.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for forming a multi-bit memory cell using a semiconductor substrate, comprising:
forming a first insulating layer over the semiconductor substrate;
forming a second insulating layer over the first insulating layer;
forming a layer of gate material over the second insulating layer;
patterning the gate material to leave a gate portion of the layer of gate material;
etching the second insulating layer to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion; and
forming nanocrystals on the first insulating layer wherein a first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer, whereby the first portion of the nanocrystals are for storing a logic state of a first bit and the second portion is for storing a logic state of a second bit.
2. The method of claim 1, further comprising forming a sidewall spacer adjacent to the gate portion, the sidewall spacer covering a third portion of the nanocrystals adjacent to the first portion of the nanocrystals and covering a fourth portion of the nanocrystals adjacent to the second portion of nanocrystals.
3. The method of claim 2, further comprising applying an etchant useful in removing the nanocrystals using the gate portion and the sidewall spacer as a mask.
4. The method of claim 3 further comprising growing an insulating layer on the gate portion prior to forming the nanocrystals.
5. The method of claim 4, further comprising implanting sourcedrain dopants into the semiconductor substrate using the gate portion and the sidewall spacer as a mask.
6. The method of claim 5, further comprising:
forming a second sidewall spacer after the implanting; and
implanting sourcedrain dopants into the semiconductor substrate using the second sidewall spacer as a mask.
7. The method of claim 6, wherein the forming of the first insulating layer is further characterized by the first insulating layer comprising hafnium oxide.
8. The method of claim 6, wherein the forming of a first insulating layer is further characterized by having a top surface that has an etch characteristic selective to oxide.
9. The method of claim 1, wherein the forming of the first insulating layer comprises:
forming an oxide layer on the semiconductor substrate; and
performing a decoupled plasma nitridation on the oxide layer.
10. The method of claim 1, wherein forming a first insulating layer is further characterized by having a top surface that has an etch characteristic selective to oxide.
11. A method for forming a multi-bit memory cell using a semiconductor substrate, comprising:
forming a first insulating layer over the semiconductor substrate, the first insulating layer having a nitrided top surface;
forming a second insulating layer over the first insulating layer, wherein the second insulating layer is selectively etchable with respect to the nitrided top surface of the first insulating layer;
forming a polysilicon layer over the second insulating layer;
patterning the polysilicon layer to leave a gate portion of the polysilicon layer;
applying hydrofluoric acid to the second insulating layer to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion; and
forming nanocrystals over the first insulating layer wherein a first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer, whereby the first portion of the nanocrystals are for storing a logic state of a first bit and the second portion of the nanocrystals is for storing a logic state of a second bit.
12. The method of claim 11, wherein forming the first insulating layer comprises performing decoupled plasma nitridation to achieve the nitrided top surface.
13. The method of claim 11, wherein forming the second insulating layer comprises performing a high temperature oxide deposition, wherein the second insulating layer is thicker than the first insulating layer.
14. The method of claim 11, further comprising:
forming a sidewall spacer adjacent to the gate portion that covers a third portion of the nanocrystals adjacent to the first portion of the nanocrystals and covers a fourth portion of the nanocrystals adjacent to the second portion of nanocrystals; and
implanting sourcedrain dopants into the substrate using the gate portion and the sidewall spacer as a mask.
15. The method of claim 14, further comprising growing an oxide layer on the gate portion prior to forming the nanocrystals.
16. A method for forming a multi-bit memory cell using a semiconductor substrate, comprising:
growing a first oxide layer on the semiconductor substrate;
performing a decoupled plasma nitridation on the first oxide layer;
depositing a second oxide layer overlying the first oxide layer;
forming a layer of gate material overlying the second oxide layer;
patterning the gate material to leave a gate portion of the layer of gate material;
applying hydrofluoric acid to the second oxide layer for a duration sufficiently long to undercut the gate portion at least 150 Angstroms and expose portions of the first oxide layer; and
forming nanocrystals on the first oxide layer.
17. The method of claim 16, wherein forming the nanocrystals further comprises forming a first portion of the nanocrystals under a first side of the gate portion and forming a second portion of the nanocrystals under a second side of the gate portion.
18. The method of claim 17, further comprising forming a sidewall spacer adjacent to the gate portion, the sidewall spacer covering a third portion of the nanocrystals adjacent to the first portion of the nanocrystals and covering a fourth portion of the nanocrystals adjacent to the second portion of nanocrystals.
19. The method of claim 18, further comprising implanting sourcedrain dopants into the semiconductor substrate using the gate portion and the sidewall spacer as a mask.
20. The method of claim 19, further comprising:
forming a second sidewall spacer after the implanting; and
implanting sourcedrain dopants into the semiconductor substrate using the second sidewall spacer as a mask.

1. A capacitive touch sensing device comprising:
a flexible touch sensing circuit with a first surface and a second surface opposite to the first surface, the flexible touch sensing circuit including a flexible dielectric film and an array of capacitance sensing nodes, the array including a plurality of conductive lines, the flexible dielectric film and the array of capacitance sensing nodes being disposed between the first surface and the second surface, the flexible touch sensing circuit being deformable into a plurality of different three-dimensional shapes such that the second surface is conformable to each of the plurality of different three-dimensional shapes while the flexible touch sensing circuit senses multiple touch events occurring at different locations on the first surface.
2. The capacitive touch sensing device of claim 1 wherein the flexible touch sensing circuit includes an electrically isolated electrode at each capacitance sensing node, each electrode electrically connected to an individual one of the conductive lines for operatively coupling to capacitive monitoring circuitry.
3. The capacitive touch sensing device of claim 2, further comprising:
the capacitive monitoring circuitry, wherein the capacitive monitoring circuitry includes one or more integrated circuits for monitoring the capacitance at each of the electrodes.
4. The capacitive touch sensing device of claim 3, further comprising:
a processing device that detects the multiple touch events occurring on the first surface of the flexible touch sensing circuit, the multiple touch events being detected based on capacitance information received from the capacitive monitoring circuitry.
5. The capacitive touch sensing device of claim 1 wherein the capacitance sensing nodes are arranged in an orthogonal grid.
6. The capacitive touch sensing device of claim 1 wherein the flexible touch sensing circuit is opaque.
7. The capacitive touch sensing device of claim 1, further comprising:
an object including a processing device, wherein the second surface of the flexible touch sensing circuit is attached to one or more surfaces of the object, and the processing device detects the multiple touch events occurring on the first surface.
8. The capacitive touch sensing device of claim 7 wherein the object is a handheld electronics device, and the processing device further generates input commands of the handheld electronics device, the input commands being generated based on the detected touch events.
9. The capacitive touch sensing device of claim 8 wherein the handheld electronics device is a remote control, a computer, a mobile telephone or a digital media player.
10. The capacitive touch sensing device of claim 7 wherein the object is a musical instrument.
11. The capacitive touch sensing device of claim 7 wherein the object is a handle of a sporting device.
12. The capacitive touch sensing device of claim 1, wherein a distance between the first and second surfaces is 0.1 mm or less.
13. The capacitive touch sensing device of claim 1, wherein the flexible touch sensing circuit is substantially transparent.
14. The capacitive touch sensing device of claim 13, wherein the conductive lines include indium tin oxide (ITO).
15. The capacitive touch sensing device of claim 1, wherein the conductive lines include a first set of conductive lines disposed a first layer and a second set of conductive lines disposed in a second layer, the first and second layers being spatially separated from each other, the first set of conductive lines arranged along a first direction and the second set of conductive lines arranged along a second direction different than the first direction, such that first and second sets of conductive lines overlap at a plurality of locations, wherein each overlap is one of the capacitance sensing nodes.
16. The capacitive touch sensing device of claim 15, wherein the first direction is orthogonal to the second direction.
17. The capacitive touch sensing device of claim 7, wherein the one or more surfaces of the object includes a planar surface.
18. The capacitive touch sensing device of claim 7, wherein the processing device further determines an arrangement of the detected multiple touch events, compares the determined arrangement to a predetermined arrangement, and generates feedback information based on the comparison.
19. The capacitive touch sensing device of claim 18, wherein the object is a sporting device, the predetermined arrangement is a predetermined grip arrangement of the sporting device, and the feedback information indicates whether or not the determined arrangement matches the predetermined grip arrangement.
20. The capacitive touch sensing device of claim 8, further comprising:
a display screen that displays graphical user interface (GUI) objects, wherein the input commands generated by the processing device are further based on the GUI objects.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for an attribute identification framework comprising:
a processing unit;
an attribute identification algorithm module;
an offline training portion comprising:
a preprocessing module to tokenize a first sentence input to the offline training portion into ngrams to define a first tokenized sentence;
a feature selection module employing information gain to determine a presence or absence of a plurality of attributes in the first tokenized sentence;
a model training module to generate the attribute identification algorithm module for each of the plurality of attributes within the first tokenized sentence, with each term having a relationship with another term of the first tokenized sentence;

an online prediction portion comprising:
a preprocessing module to tokenize a second sentence input to the online prediction portion into ngrams to define a second tokenized sentence;
an attribute prediction module to determine attributes of the second tokenized sentence employing the attribute identification algorithm module; and
an attribute number prediction module to determine a number of attributes to be associated with the second tokenized sentence.
2. The system as recited in claim 1, wherein the first sentence comprises a plurality of attributes.
3. The system as recited in claim 1, wherein the second sentence comprises a plurality of attributes.
4. The system as recited in claim 1, wherein the second sentence is an online review for a product.
5. The system as recited in claim 1, wherein the attribute identification algorithm comprises a plurality of binary classifiers.
6. The system as recited in claim 1, wherein the ngrams are less than or equal to 3.
7. The system as recited in claim 1, wherein the information gain of the feature selection module is defined as:
G
\u2061

(
t
)
=
–
\u2211

i
=
1

m

\u2062
P
r

\u2061

(

c
i

)
\u2062
log
\u2062
\u2062
P
r

\u2061

(

c
i

)
+
P
r

\u2061

(
t
)
\u2062
\u2211

i
=
1

m

\u2062
P
r

\u2061

(
c
i

\u2758
t

)
\u2062
log
\u2062
\u2062
P
r

\u2061

(
c
i

\u2758
t

)
+
P
r

\u2061

(
t
)
\u2062
\u2211

i
=
1

m

\u2062
P
r

\u2061

(
c
i

\u2758
t

)
\u2062
log
\u2062
\u2062
P
r

\u2061

(
c
i

\u2758
t

)
wherein ci denotes a category of the attribute in the sentence.