Author: claimsbot

What is claimed is:

1. A method for controlling storage of data on a removable external recording medium which can be installed on a storage system, comprising the steps of:
halting of data storage on said external recording medium when judgment is made not to store data on said external recording medium and, beginning storage of data which follows data stored on said external recording medium in an internal storage means.
2. A method for controlling storage of data according to claim 1, comprising the steps of:
comparing an amount of free space on said external recording medium with an amount of data to be stored next;
storing data on said external recording medium if the amount of free space is larger than the amount of data; and
storing data in said internal storage means if the amount of free space is insufficient.
3. A method for controlling storage of data according to claim 1, comprising the steps of:
judging whether capacity of said external recording medium is sufficient for data to be stored next;
storing data on said external recording medium if the capacity of said external recording medium is sufficient; and
storing data in said internal storage means if the capacity of said external recording medium is not sufficient.
4. A method for controlling storage of data according to claim 1, wherein data in said internal storage means is updated by sequentially-entered data and wherein, when the amount of data stored on said external recording medium has reached a predetermined amount, data which follows data stored on said external recording medium is held in said internal storage means.
5. A method for controlling storage of data according to claim 1, wherein, when said external recording medium is exchanged from a first external recording medium to a second external recording medium, data held in said internal storage means is stored on said second external recording medium.
6. A method for controlling storage of data according to claim 5, wherein, on said second external recording medium, data stored in said internal storage means is stored first and then data entered after said second external recording medium is installed is stored.
7. A method for controlling storage of data according to claim 5, wherein data entered after said second external recording medium is installed is stored first on said second external recording medium and wherein data held in said internal storage means is stored on said second external recording medium when data supply after said medium installation is stopped.
8. A method for controlling storage of data on a removable external recording medium which can be installed on a storage system wherein, when said external recording medium is removed, data which follows data stored on said external recording medium is held in an internal storage means.
9. A method for controlling storage of data according to claim 8 wherein, when a second external recording medium is installed, data which is held in said internal storage means and which is entered after a first external recording medium is removed is stored in said second external recording medium.
10. A method for controlling storage of data according to claim 9, wherein, on said second external recording medium, data stored in said internal storage means is stored before data entered after said second external recording medium is installed is stored.
11. A method for controlling storage of data according to claim 9, wherein data entered after said second external recording medium is installed is stored first on said second external recording medium and wherein data held in said internal storage means is stored on said second external recording medium when data supply after medium installation is stopped.
12. A data storage control system comprising:
an external storage controller which stores data on a removable external recording medium which can be installed on a storage system;
an internal storage controller which stores data in internal storage means on an auxiliary basis; and
a main controller which controls said external storage controller and said internal storage controller, said main controller is stopping writing data on said external recording medium and holding data, which follows data stored on said external recording medium, in said internal storage means when judgment is made not to store data on said external recording medium.
13. A data storage system comprising:
an encoder for coding entered data into variable length data;
an external storage controller which stores data on a removable external recording medium which can be installed on said storage system;
an internal storage controller which stores data in internal storage means on an auxiliary basis; and
a main controller which controls said external storage controller and said internal storage controller, said main controller is stopping writing data on said external recording medium and holding data, which follows data stored on said external recording medium, in said internal storage means when judgment is made not to store data on said external recording medium.
14. A data storage system according to claim 13, wherein said main controller has a comparator which compares an amount of free space on said external recording medium with an amount of data to be stored next;
wherein said main controller stores data on said external recording medium if the amount of free space is larger than the amount of data; and
wherein said main controller stores data in said internal storage means if the mount of free space is insufficient.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A torsional vibration measuring instrument comprising:
a plurality of reflecting means arranged with stipulated intervals therebetween along surface of a rotator of which torsional vibration is to be measured;
a pulse light irradiating means for irradiating a repetitive pulse light beam to the plurality of reflecting means;
an outgoing-transmitting means for transmitting the irradiated pulse light beam;
a plurality of transmitting-receiving means for irradiating the transmitted pulse light beam to the plurality of reflecting means, and for receiving plurality of reflected pulse light beams which have been reflected by the plurality of reflecting means;
an incoming-transmitting means for transmitting the plurality of reflected pulse light beams which have been received;
a plurality of detecting means for detecting the plurality of reflected pulse light beams which have been transmitted by the incoming-transmitting means; and
a signal processing means for processing a plurality of pulse output signals which have been outputted from the plurality of detecting means and for calculating torsional vibration frequency of the rotator to be measured.
2. The torsional vibration measuring instrument of claim 1 characterized that the pulse light beam irradiating means can irradiate pulse light beam with variable pulse repetitive frequency and with variable pulse time width.
3. The torsional vibration measuring instrument of claim 1 characterized that the pulse light beam irradiating means includes a plurality of separated units each corresponding to one of the plurality of transmitting-receiving means.
4. The torsional vibration measuring instrument of claim 1 characterized that the ongoing-transmitting means includes a beam splitter for splitting the pulse light irradiated from the pulse light irradiating means and for transmitting the pulse light.
5. The torsional vibration measuring instrument of claim 1 characterized that the plurality of reflecting means and the plurality of transmitting-receiving means are aligned in radial direction of the rotator to be measured, and that the pulse light beams are directed so that the pulse light beam is irradiated substantially perpendicular to the plurality of reflector means.
6. The torsional vibration measuring instrument of claim 1 characterized that the outgoing-transmission means and the incoming transmission means have at least one light dividing means, and that the outgoing-transmission means and the incoming transmission means utilize at least partly a common light guide.
7. The torsional vibration measuring instrument of claim 1 characterized that the signal processing means calculate torsional vibration frequency of the rotator based upon difference of rotational periods obtained by the corresponding pulse output signals.
8. The torsional vibration measuring instrument of claim 1 characterized that the transmitting-receiving means are arranged in peripheral direction of the rotator to be measured.
9. The torsional vibration measuring instrument of claim 1 characterized that at least three transmitting-receiving means and at least three reflecting means are arranged along axial direction of the rotator.
10. The torsional vibration measuring instrument of claim 1 characterized that the reflecting means has a high reflection region where the light beam is reflected with a high reflection coefficient, and a low reflection region where the light beam is reflected with a reflection coefficient lower than the high reflection coefficient, and that the high reflection region and the low reflection region are distributed along peripheral direction of the rotator to be measured.
11. The torsional vibration measuring instrument of claim 1 characterized that the plurality of reflecting means each includes a plurality of units of reflecting means attached on the rotator to be measured.
12. The torsional vibration measuring instrument of claim 1 characterized that the signal processing means calculates the torsional vibration frequency of the rotator to be measured, by differentiating the plurality of pulse output signals which are outputted from the plurality of detecting means.
13. The torsional vibration measuring instrument of claim 1 characterized that the signal processing means calculates the torsional vibration frequency of the rotator to be measured, by digital counting of the plurality of pulse output signal which are outputted from the plurality of detecting means.
14. The torsional vibration measuring instrument of claim 1 characterized that the signal processing means calculates the torsional vibration frequency of the rotator to be measured, using lengths of the plurality of reflecting means in peripheral direction.
15. The torsional vibration measuring instrument of claim 1 characterized that wavelength of pulse light of the pulse irradiating means can be changed.
16. The torsional vibration measuring instrument of claim 1 characterized that the detecting means include wavelength selecting means for selecting the reflected pulse light beam using the wavelength and for detecting the selected pulse light beam.
17. The torsional vibration measuring instrument of claim 1 characterized that size of the pulse light beam which is irradiated to the reflecting means is much smaller than lengths of the reflecting means in axial and peripheral directions of the rotator to be measured.

1. A pneumatic radial medium truck tire comprising at least one pair of annular beads, at least one carcass ply wrapped around said beads, five to twelve belts disposed over said at least one carcass ply in a crown area of said tire, a tread disposed over said five to twelve belts and, sidewalls disposed between said tread and said beads, wherein the majority of said five to twelve belts are reinforced with steel filaments or cords, and the remaining belts including the top two belts of the five to twelve belts are reinforced with organic polymer filaments or cords, wherein the organic polymer filaments or cords are inclined at angles of 5\xb0 to 35\xb0 with respect to an equatorial plane of the tire and the organic polymer filaments or cords are obround cross section monofilaments.
2. The tire of claim 1 wherein the axial edges of the top two belts extend axially beyond the axial edges of the steel belts.
3. The tire of claim 1 wherein the organic polymer monofilaments in said top two belts are at a concentration of 8 to 16 ends per inch and the steel filaments or cords in said steel belts are at a concentration of 9 to 16 ends per inch.
4. The tire of claim 1 wherein said organic polymer monofilament have at least 2000 denier (2200 dTex), a tenacity of at least 3.5 gdenier (31 cNTex), an initial modulus of at least 30 gdenier (265 cNTex), an elongation at break of at least 17%, and a shrinkage of at most 6%.
5. The tire of claim 4 wherein said organic polymer monofilements are nylon 66.
6. The tire of claim 4 wherein the organic polymer monofilaments are coated with a resorcinol formaldehyde latex (RFL) adhesive.
7. The tire of claim 4 wherein the organic polymer monofilaments are coated with an epoxy subcoat and a resorcinol formaldehyde latex (RFL) adhesive top coat.
8. The tire of claim 4 wherein the top two belts are reinforced with 6,000 denier (6,700 dtex) obround nylon monofilaments.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data strobe signal generator, comprising:
a control unit for generating a column address strobe (CAS) latency signal and a preamble signal in response to a mode register set signal, an extended mode register set signal and address signals;
a pulse delay unit for delaying a pulse signal for a predetermined time and outputting a delayed pulse signal in response to the CAS latency signal and the preamble signal;
a clock generator for outputting a control clock signal in response to the CAS latency signal and the preamble signal; and
a data strobe output unit for outputting a data strobe signal in response to the delayed pulse signal and the control clock signal.
2. The data strobe signal generator as set forth in claim 1, wherein:
the CAS latency signal represents information about a data output time;
the preamble signal represents information about a initial toggle time;
the data output time is the time taken from the time at which a read command is input to a semiconductor memory device including the data strobe signal generator, to a time at which the semiconductor memory device outputs output data, and the initial toggle time is the time for which the data strobe signal is stabilized; and
the data output time includes the initial toggle time.
3. The data strobe signal generator as set forth in claim 1, wherein:
the address signals include a first address signal and a second address signal; and
the control unit comprises:
a first latch unit for outputting a first latch signal, in response to the mode register set signal and the first address signal;
a second latch unit for outputting a second latch signal, in response to the extended mode register set signal and the second address signal;
a subtractor for subtracting a bit value of the second latch signal from a bit value of the first latch signal and outputting a subtraction signal based on the result of the subtraction;
a first decoder for decoding the subtraction signal and outputting the CAS latency signal based on the result of the decoding; and
a second decoder for decoding the second latch signal and outputting the preamble signal based on the result of the decoding.
4. The data strobe signal generator as set forth in claim 3, wherein:
the address signals further include a third address signal; and
the control unit further generates a burst length signal in response to the mode register set signal and the third address signal.
5. The data strobe signal generator as set forth in claim 4, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles, determined by the preamble signal and the burst length signal, as the control clock signal.
6. The data strobe signal generator as set forth in claim 4, wherein the control unit further comprises a third latch unit for latching the third address signal and outputting the latched signal as the burst length signal, in response to the mode register set signal.
7. The data strobe signal generator as set forth in claim 6, wherein:
the mode register set signal is enabled when a mode register set command is generated, and the extended mode register set signal is enabled when an extended register set command is generated;
the first latch unit latches the first address signal when the mode register set signal is enabled;
the second latch unit latches the second address signal when the extended mode register set signal is enabled; and
the third latch unit latches the third address signal when the mode register set signal is enabled.
8. The data strobe signal generator as set forth in claim 4, wherein the first to third address signals and the subtraction signal respectively include a plurality of bits, and the number of bits in the first address signal is larger than the number of bits in the second address signal.
9. The data strobe signal generator as set forth in claim 1, wherein:
the address signals include a first address signal and a second address signal; and
the control unit comprises:
a first latch unit for outputting a first latch signal, in response to the mode register set signal and the first address signal;
a second latch unit for outputting a second latch signal, in response to the extended mode register set signal and the second address signal;
a counter for performing a counting operation in response to the first and second latch signals and outputting a counting signal;
a first decoder for decoding the counting signal and outputting the CAS latency signal based on the result of the decoding; and
a second decoder for decoding the second latch signal and outputting the preamble signal based on the result of the decoding.
10. The data strobe signal generator as set forth in claim 9, wherein:
the address signals further include a third address signal; and
the control unit further generates a burst length signal in response to the mode register set signal and the third address signal.
11. The data strobe signal generator as set forth in claim 10, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles, determined by the preamble signal and the burst length signal, as the control clock signal.
12. The data strobe signal generator as set forth in claim 10, wherein the control unit further comprises a third latch unit for latching the third address signal and outputting the latched signal as the burst length signal, in response to the mode register set signal.
13. The data strobe signal generator as set forth in claim 12, wherein:
the mode register set signal is enabled when a mode register set command is generated, and the extended mode register set signal is enabled when an extended register set command is generated;
the first latch unit latches the first address signal when the mode register set signal is enabled;
the second latch unit latches the second address signal when the extended mode register set signal is enabled; and
the third latch unit latches the third address signal when the mode register set signal is enabled.
14. The data strobe signal generator as set forth in claim 12, wherein:
the counting signal includes first to Nth (N is integer) bits; and the counter comprises:
a counter control unit for outputting a counting control signal based on the first latch signal and outputting a counting clock signal based on the second latch signal; and
first to N-th flip flops connected in series to each other, and configured to respectively output the first to N-th bits in response to the counting clock signal;
wherein the first flip flop receives the counting control signal and outputs the received counting control signal as the first bit, in response to the counting clock signal;
the second to N-th flop flops respectively receive the first to N\u22121-th bits and respectively output the received first to N\u22121-th bits as the second to N-th bits, in response to the counting clock signal.
15. The data strobe signal generator as set forth in claim 14, wherein:
the counting control unit toggles the counting control signal by a number determined by first latch signal’s bit value and toggles the counting clock signal by a number determined by a bit value of the second latch signal; and
when the toggle numbers of the counting control signal and the counting clock signal are changed, the bit value of the counting signal is altered.
16. The data strobe signal generator as set forth in claim 1, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles which is determined by the preamble signal as the control clock signal.
17. A synchronous semiconductor memory device, comprising:
an internal core circuit having a memory cell array;
at least one data output circuit for outputting output data received from the internal core circuit to an external device via at least one data inputoutput pin; and
a data strobe signal generator for generating a data strobe signal in response to a mode register set signal, an extended mode register set signal, address signals and an internal clock signal,
wherein the data strobe signal generator comprises:
a control unit for generating a column address strobe (CAS) latency signal and a preamble signal in response to the mode register set signal, the extended mode register set signal and address signals;
a pulse delay unit for delaying a pulse signal for predetermined time and outputting a delayed pulse signal, in response to the CAS latency signal and the preamble signal;
a clock generator for outputting a control clock signal in response to the CAS latency signal and the preamble signal; and
a data strobe output unit for outputting a data strobe signal in response to the delayed pulse signal and the control clock signal.
18. The synchronous semiconductor memory device as set forth in claim 17, wherein:
the CAS latency signal represents information about a data output time;
the preamble signal represents information about a initial toggle time;
the data output time is the time taken from the time at which a read command is input to a semiconductor memory device including the data strobe signal generator, to a time at which the semiconductor memory device outputs output data, and the initial toggle time is the time for which the data strobe signal is stabilized; and
the data output time includes the initial toggle time.
19. The synchronous semiconductor memory device as set forth in claim 17, wherein:
the address signals include a first address signal and a second address signal; and
the control unit comprises:
a first latch unit for outputting a first latch signal, in response to the mode register set signal and the first address signal;
a second latch unit for outputting a second latch signal, in response to the extended mode register set signal and the second address signal;
a subtractor for subtracting a bit value of the second latch signal from a bit value of the first latch signal and outputting a subtraction signal based on the result of the subtraction;
a first decoder for decoding the subtraction signal and outputting the CAS latency signal based on the result of the decoding; and
a second decoder for decoding the second latch signal and outputting the preamble signal based on the result of the decoding.
20. The synchronous semiconductor memory device as set forth in claim 19, wherein:
the address signals further include a third address signal; and
the control unit further generates a burst length signal in response to the mode register set signal and the third address signal.
21. The synchronous semiconductor memory device as set forth in claim 20, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles, determined by the preamble signal and the burst length signal, as the control clock signal.
22. The synchronous semiconductor memory device as set forth in claim 20, wherein the control unit further comprises a third latch unit for latching the third address signal and outputting the lathed signal as the burst length signal, in response to the mode register set signal.
23. The synchronous semiconductor memory device as set forth in claim 17, wherein:
the address signals include a first address signal and a second address signal; and
the control unit comprises:
a first latch unit for outputting a first latch signal, in response to the mode register set signal and the first address signal;
a second latch unit for outputting a second latch signal, in response to the extended mode register set signal and the second address signal;
a counter for performing a counting operation in response to the first and second latch signals and outputting a counting signal;
a first decoder for decoding the counting signal and outputting the CAS latency signal based on the result of the decoding; and
a second decoder for decoding the second latch signal and outputting the preamble signal based on the result of the decoding.
24. The synchronous semiconductor memory device as set forth in claim 23, wherein:
the address signals further include a third address signal; and
the control unit further generates a burst length signal in response to the mode register set signal and the third address signal.
25. The synchronous semiconductor memory device as set forth in claim 24, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles, which is determined by the preamble signal and the burst length signal, as the control clock signal.
26. The synchronous semiconductor memory device as set forth in claim 24, wherein the control unit further comprises a third latch unit for latching the third address signal and outputting the lathed signal as the burst length signal, in response to the mode register set signal.
27. The synchronous semiconductor memory device as set forth in claim 23, wherein:
the counting signal includes first to Nth (N is integer) bits; and the counter comprises:
a counter control unit for outputting a counting control signal based on the first latch signal and outputting a counting clock signal based on the second latch signal; and
first to N-th flip flops connected in series to each other, and configured to respectively output the first to N-th bits in response to the counting clock signal;
wherein the first flip flop receives the counting control signal and outputs the received counting control signal as the first bit, in response to the counting clock signal;
the second to N-th flop flops respectively receive the first to N\u22121-th bits and respectively output the received first to N\u22121-th bits as the second to N-th bits, in response to the counting clock signal.
28. The synchronous semiconductor memory device as set forth in claim 27, wherein:
the counting control unit toggles the counting control signal by a number determined by a bit value of the first latch signal and toggles the counting clock signal by a number determined by a bit value of the second latch signal; and
when the toggle numbers of the counting control signal and the counting clock signal are changed, a bit value of the counting signal is altered.
29. The synchronous semiconductor memory device as set forth in claim 17, wherein the clock generator outputs the internal clock signal corresponding to a number of clock cycles which is determined by the preamble signal as the control clock signal.
30. The synchronous semiconductor memory device as set forth in claim 17, further comprising at lease one data input circuit for outputting input data received from the external device to the internal corn circuit via the at least one data inputoutput pin in response to an additional data strobe signal.