Author: claimsbot

It is claimed:

1. A method of operating a memory device, the method comprising:
connecting a first potential to source lines of memory cells of a first block of memory cells during an access operation; and
disconnecting a supply voltage from source lines of memory cells of a second block of memory cells during the access operation.
2. The method of claim 1, wherein connecting a first potential to source lines includes connecting the source lines to ground.
3. The method of claim 2, wherein the access operation is one of read operation and program operation.
4. The method of claim 1, wherein connecting a first potential to source lines includes connecting the source lines to a positive voltage.
5. The method of claim 4, wherein the access operation is an erase operation.
6. A method of operating a memory device, the method comprising:
setting source lines of memory cells of a first block of memory cells to a first state during an access operation; and
setting source lines of memory cells of a second block of memory cells to a second state during the access operation.
7. The method of claim 6, wherein setting source lines of memory cells of a first block of memory cells includes applying a non-zero voltage to the source lines of memory cells of the first block of memory cells.
8. The method of claim 7, wherein setting source lines of memory cells of a second block of memory cells includes applying ground to the source lines of memory cells of the second block of memory cells.
9. The method of claim 6, wherein setting source lines of memory cells of a first block of memory cells includes applying a voltage to the source lines of memory cells of the first block of memory cells.
10. The method of claim 9, wherein setting source lines of memory cells of a second block of memory cells includes setting the source lines of memory cells of the second block of memory cells to a high impedance state.
11. The method of claim 6, wherein setting source lines of memory cells of a first block of memory cells and setting source lines of memory cells of a second block of memory cells includes:
applying a first potential to the source lines of memory cells of the first block of memory cells.
applying a second potential to the source lines of memory cells of the second block of memory cells, wherein the first potential is unequal to the second potential.
12. A method of operating a memory device, the method comprising:
setting source lines of memory cells of a first block of memory cells to a first state during an erase operation; and
setting source lines of memory cells of a second block of memory cells to a second state during the erase operation, wherein the first state is unequal to the second state.
13. The method of claim 12, wherein setting source lines of memory cells of a first block of memory cells includes applying a positive voltage to the source lines of memory cells of the first block of memory cells.
14. The method of claim 13, wherein setting source lines of memory cells of a second block of memory cells includes applying ground to the source lines of memory cells of the second block of memory cells.
15. The method of claim 12, wherein setting source lines of memory cells of a first block of memory cells includes applying a voltage to the source lines of memory cells of the first block of memory cells.
16. The method of claim 15, wherein setting source lines of memory cells of a second block of memory cells includes setting the source lines of memory cells of the second block of memory cells to a high impedance state.
17. The method of claim 12, wherein setting source lines of memory cells of a first block of memory cells and setting source lines of memory cells of a second block of memory cells includes:
applying a first potential to the source lines of memory cells of the first block of memory cells.
applying a second potential to the source lines of memory cells of the second block of memory cells, wherein the first potential is unequal to the second potential.
18. A method comprising:
fabricating a plurality of horizontal source lines, each of the horizontal source lines having a resistance per unit length;
connecting the horizontal source lines together using a vertical source line;
connecting the horizontal source lines together at a plurality of horizontal locations using a plurality of vertical line straps; and
connecting the vertical source line to a global source line through a first plurality of switches.
19. The method of claim 18 further comprising: connecting the vertical source line to a source bus through a second plurality of switches.
20. The method of claim 18, wherein fabricating a plurality of the horizontal source lines includes fabricating the horizontal source lines with semiconductor material.
21. The method of claim 20, wherein connecting the horizontal source lines together using a vertical source line includes using metal for the vertical source line.
22. The method of claim 18, wherein fabricating a plurality of the horizontal source lines includes fabricating the horizontal source lines with doped polysilicon.
23. The method of claim 18, wherein connecting the horizontal source lines together using a vertical source line includes using material for the vertical source line different from material of the horizontal source lines.
24. A memory device comprising:
a first block having a first plurality of memory cells;
a first plurality of source lines connected to the first plurality memory cells;
a second block having a second plurality of memory cells;
a second plurality of source lines connected to the second plurality memory cells; and
a source line decoder circuit connected to the first plurality of source lines and the second plurality of vertical source lines for applying a first potential to the first plurality of source lines during an access operation, and for disconnecting a supply voltage from the second plurality of source lines during the access operation.
25. The memory device of claim 24, wherein the source line decoder circuit includes a first plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a global source line.
26. The memory device of claim 25, wherein the source line decoder circuit further includes a second plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a source bus.
27. A memory device comprising:
a first block having a first plurality of memory cells;
a first plurality of source lines connected to the memory cells of the first block;
a second block having a second plurality of memory cells;
a second plurality of source lines connected to the memory cells of the second block; and
a source line decoder circuit connected to the first plurality of source lines and the second plurality of source lines for setting the first plurality of source lines to a first state during an access operation, and for setting the second plurality of source lines to a second state during the access operation.
28. The memory device of claim 27, wherein the source line decoder circuit includes a first plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a global source line.
29. The memory device of claim 28, wherein the source line decoder circuit further includes a second plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a source bus.
30. The memory device of claim 27, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a first potential during the access operation, and for connecting the second group of vertical source lines to a source bus having a second potential unequal to the first potential during the access operation.
31. The memory device of claim 27, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a potential during the access operation, and for setting the second group of vertical source lines to a high impedance state during the access operation.
32. A memory device comprising:
a first block having a first plurality of memory cells;
a first plurality of source lines connected to the memory cells of the first block;
a second block having a second plurality of memory cells;
a second plurality of source lines connected to the memory cells of the second block; and
a source line decoder circuit connected to the first plurality of source lines and the second plurality of source lines for setting the first plurality of source lines to a first state during an erase operation, and for setting the second plurality of source lines to a second state unequal to the second state during the erase operation.
33. The memory device of claim 32, wherein the source line decoder circuit includes a first plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a global source line.
34. The memory device of claim 33, wherein the source line decoder circuit further includes a second plurality of switches for connecting the first plurality of source lines and the second plurality of source lines to a source bus.
35. The memory device of claim 32, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a first voltage during the erase operation, and for connecting the second group of vertical source lines to a source bus having a second voltage unequal to the first voltage during the erase operation.
36. The memory device of claim 32, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a positive voltage during the erase operation, and for connecting the second group of vertical source lines to a source bus having zero voltage during the erase operation.
37. The memory device of claim 32, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a voltage during the erase operation, and for setting the second group of vertical source lines to a high impedance state during the erase operation.
38. A memory device comprising:
a plurality of horizontal source lines, each of the horizontal source lines having a resistance per unit length;
a plurality of vertical source lines connected to the horizontal source lines;
a plurality of vertical line straps connects the horizontal source lines together at a plurality of horizontal locations; and
a source line decoder circuit connected to the plurality of vertical source lines for applying a first potential to a first group of vertical source lines in the plurality of vertical source lines during an access operation, and for disconnecting a supply voltage from a second group of vertical source lines in the plurality of vertical source lines during the access operation.
39. The memory device of claim 38, wherein the source line decoder circuit includes a first plurality of switches connected between the plurality of vertical source lines and a global source line.
40. The memory device of claim 39, wherein the source line decoder circuit further includes a second plurality of switches connected between the plurality of vertical source lines and a source bus.
41. A memory device comprising:
a plurality of horizontal source lines, each of the horizontal source lines having a resistance per unit length;
a plurality of vertical source lines connected to the horizontal source lines;
a plurality of vertical line straps connects the horizontal source lines together at a plurality of horizontal locations; and
a source line decoder circuit connected to the plurality of vertical source lines for setting a first group of vertical source lines in the plurality of vertical source lines to a first state during an access operation, and for setting a second group of vertical source lines in the plurality of vertical source lines to a second state the access operation.
42. The memory device of claim 41, wherein the source line decoder circuit includes a first plurality of switches connected between the plurality of vertical source lines and a global source line.
43. The memory device of claim 42, wherein the source line decoder circuit further includes a second plurality of switches connected between the plurality of vertical source lines and a source bus.
44. The memory device of claim 41, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a first potential during the access operation, and for connecting the second group of vertical source lines to a source bus having a second potential unequal to the first potential during the access operation.
45. The memory device of claim 41, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a potential during the access operation, and for setting the second group of vertical source lines to a high impedance state during the access operation.
46. A memory device comprising:
a plurality of horizontal source lines, each of the horizontal source lines having a resistance per unit length;
a plurality of vertical source lines connected to the horizontal source lines;
a plurality of vertical line straps connects the horizontal source lines together at a plurality of horizontal locations; and
a source line decoder circuit connected to the plurality of vertical source lines for setting a first group of vertical source lines in the plurality of vertical source lines to a first state during an erase operation, and for setting a second group of vertical source lines in the plurality of vertical source lines to a second state the erase operation.
47. The memory device of claim 46, wherein the source line decoder circuit includes a first plurality of switches connected between the plurality of vertical source lines and a global source line.
48. The memory device of claim 47, wherein the source line decoder circuit further includes a second plurality of switches connected between the plurality of vertical source lines and a source bus.
49. The memory device of claim 46, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a first voltage during the erase operation, and for connecting the second group of vertical source lines to a source bus having a second voltage unequal to the first voltage during the erase operation.
50. The memory device of claim 46, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a non-zero voltage during the erase operation, and for connecting the second group of vertical source lines to a source bus having zero voltage during the erase operation.
51. The memory device of claim 46, wherein the source line decoder circuit includes a first plurality of switches for connecting the first group of vertical source lines to a global source line having a voltage during the erase operation, and for setting the second group of vertical source lines to a high impedance state during the erase operation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of treating a patient comprising:
implanting a cardioverter-defibrillator in the patient;
capturing far-field cardiac signals from electrodes disposed beneath the skin and outside of a patient’s ribcage;
identifying the patient’s P-wave in the far-field cardiac signals;
monitoring the patient’s P-wave to determine whether the patient’s P-wave abruptly changes; and
if the patient’s P-wave abruptly changes, determining that the patient is experiencing atrial fibrillation and withholding cardiac stimulus that would otherwise be delivered to the patient.
2. The method of claim 1, wherein the cardioverter-defibrillator comprises a lead assembly coupled to a canister that houses operational circuitry for the cardioverter-defibrillator, and the step of implanting comprises placing the canister and the lead assembly in the patient beneath the skin and outside of the patient’s ribcage without accessing the vasculature or heart of the patient.
3. The method of claim 1, further comprising withholding cardiac stimulus that would otherwise be delivered to the patient if it is determined that the patient is experiencing atrial fibrillation.
4. The method of claim 1, wherein the step of monitoring the patient’s P-wave includes determining whether the patient’s P-wave disappears and, if so, concluding that the P-wave has abruptly changed.
5. The method of claim 1, further comprising identifying at least one characteristic of the patient’s P-wave during normal sinus rhythm.
6. The method of claim 5, wherein the at least one characteristics of the patient’s P-wave includes the morphology of the patient’s P-wave during normal sinus rhythm, and further wherein an abrupt change is determined by observation of whether a change occurs in the morphology of the patient’s P-wave.
7. The method of claim 5, wherein the at least one characteristic of the patient’s P-wave includes the amplitude and timing relationship of the patient’s P-wave to the patient’s QRS during normal sinus rhythm, and further wherein an abrupt change is determined by observation of whether a change occurs in the amplitude and timing relationship of the patient’s P-wave to the patient’s QRS during an unknown rhythm.
8. The method of claim 5, wherein the at least one characteristic of the patient’s P-wave includes the frequency content of the patient’s P-wave during normal sinus rhythm, and further wherein an abrupt change is determined by observation of whether a change occurs in the frequency content of the patient’s P-wave.
9. The method of claim 5, wherein the at least one characteristic of the patient’s P-wave includes the timing of the patient’s P-wave in relation to the patient’s QRS during normal sinus rhythm, and further wherein an abrupt change is determined by observation of whether a change occurs in the timing of the patient’s P-wave in relation to the patient’s QRS.
10. The method of claim 5, wherein the at least one characteristic of the patient’s P-wave includes polarity of the patient’s P-wave in relation to the patient’s QRS during normal sinus rhythm, and further wherein an abrupt change is determined by observation of whether a change occurs in the polarity of the patient’s P-wave in relation to the patient’s QRS.
11. An implantable cardioverter defibrillator (ICD) comprising a housing containing operational circuitry that is coupled to a plurality of electrodes for implantation in a patient, wherein the operational circuitry is configured to perform the following method of cardiac signal analysis while implanted in a patient:
capturing far-field cardiac signals from electrodes disposed beneath the skin and outside of a patient’s ribcage;
identifying the patient’s P-wave in the far-field cardiac signals;
monitoring the patient’s P-wave to determine whether the patient’s P-wave abruptly changes; and
if the patient’s P-wave abruptly changes, determining that the patient is experiencing atrial fibrillation and withholding cardiac stimulus that would otherwise be delivered to the patient.
12. The ICD of claim 11, wherein the operational circuitry is further configured to withhold cardiac stimulus that would otherwise be delivered to the patient if it is determined that the patient is experiencing atrial fibrillation.
13. The ICD of claim 11, wherein the operational circuitry is further configured such that the step of monitoring the patient’s P-wave includes determining whether the patient’s P-wave disappears and, if so, concluding that the P-wave has abruptly changed.
14. The ICD of claim 11, wherein the operational circuitry is further configured such that the method also includes identifying at least one characteristic of the patient’s P-wave during normal sinus rhythm.
15. The ICD of claim 14, wherein the operational circuitry is further configured such that:
the at least one characteristic of the patient’s P-wave includes the morphology of the patient’s P-wave during normal sinus rhythm; and
an abrupt change is determined by observation of whether a change occurs in the morphology of the patient’s P-wave.
16. The ICD of claim 14, wherein the operational circuitry is further configured such that:
the at least one characteristic of the patient’s P-wave includes the amplitude and timing relationship of the patient’s P-wave to the patient’s QRS during normal sinus rhythm; and
wherein an abrupt change is determined by observation of whether a change occurs in the amplitude and timing relationship of the patient’s P-wave to the patient’s QRS.
17. The ICD of claim 14, wherein the operational circuitry is further configured such that:
the at least one characteristic of the patient’s P-wave includes the frequency content of the patient’s P-wave during normal sinus rhythm; and
an abrupt change is determined by observation of whether a change occurs in the frequency content of the patient’s P-wave.
18. The ICD of claim 14, wherein the operational circuitry is further configured such that:
the at least one characteristic of the patient’s P-wave includes the timing of the patient’s P-wave in relation to the patient’s QRS during normal sinus rhythm; and
an abrupt change is determined by observation of whether a change occurs in the timing of the patient’s P-wave in relation to the patient’s QRS.
19. The ICD of claim 14, wherein the operational circuitry is further configured such that:
the at least one characteristic of the patient’s P-wave includes polarity of the patient’s P-wave in relation to the patient’s QRS during normal sinus rhythm; and
an abrupt change is determined by observation of whether a change occurs in the polarity of the patient’s P-wave in relation to the patient’s QRS.
20. A method of identifying atrial fibrillation in an implantable cardiac stimulus device comprising:
capturing cardiac signals from electrodes disposed beneath the skin and outside of a patient’s ribcage;
identifying R-waves in the cardiac signals and observing whether intervals between R-waves are stable or irregular;
if the R-wave intervals are irregular, observing whether QRS morphology is similar on a beat-to-beat basis; and
if R-wave intervals are irregular and QRS morphology is similar on a beat-to-beat basis, determining that the patient is experiencing atrial fibrillation.

1. A syringe disposal device for a single syringe, the syringe having an elongate body with a needle at one end and a finger engageable flange at its other end, said device comprising:
an elongate enclosed sheath having a closed tip at one end and a syringe body receiving opening at the other end; and
a syringe retaining means located adjacent said syringe body receiving opening; wherein said sheath has a wall thickness, said wall thickness increasing from said syringe body receiving opening towards said closed tip.
2. The device as defined in claim 1 wherein the interior of said sheath is smooth and unstepped.
3. The device as defined in claim 2 wherein the tip of said sheath interior is substantially hemispherical.
4. A method of disposing of an individual syringe having a needle tip, said method comprising the steps of:
(i) inserting the needle tip of said syringe into an opening of a syringe disposal device for a single syringe, the syringe also having a finger engageable flange at its other end opposing the needle tip, the syringe disposal device also having an elongate enclosed sheath having a closed tip at the end opposing the opening and a syringe retaining means located adjacent said opening, wherein said elongate enclosed sheath has a wall thickness, said wall thickness increasing from said opening towards said closed tip;
(ii) continuing said insertion until said needle tip engages said sheath closed tip and is permanently deflected thereby; and
(iii) continuing said insertion until said finger engageable flange is engaged with said syringe retaining means.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for delivering one or more pulses of pressure to the larynx of a subject to elicit a laryngeal adductor reflex (LAR) in the subject, the subject having a larynx comprising left and right vocal folds (VFs), said system comprising:
a pressure pulsing component configured to provide a stable and adjustable pulse of pressure to the larynx,
a control system component in functional communication with the pressure pulsing component configured to control or regulate one or more of timing, magnitude and number of pulses of pressure delivered by the pressure pulsing component in one or more respiratory cycles, and,
a respiratory sensor component configured to detect or determine one or more physiological characteristics of the subject’s LAR response to the one or more pulses of pressure delivered.
2. The system of claim 1 wherein the control system component is in functional communication with the respiratory sensor unit and controls or regulates the detection or determination of the one or more physiological characteristics of the subject’s LAR response.
3. The system of claim 1 wherein the system is configured to provide the respiratory sensor unit the capacity to detect closing and opening activities of the VFs during the complete respiratory cycle.
4. The system of claim 1 wherein one or more of the pressure pulsing, control system and respiratory sensor components is automated.
5. The system of claim 1 further comprising an air catheter unit in communication with the pressure pulsing component configured to assist in delivering pressure pulses to the larynx of the subject.
6. The system of claim 1 wherein the control system component is configured to adjust for temporal variation in the subject’s LAR response.
7. The system of claim 4 wherein the control system component is configured to provide for automated delivery of pressure pulses in synchrony with one or more phases of the subject’s respiratory cycle.
8. The system of claim 1 wherein the pressure pulsing component comprises an air pressure source in the form of an air cylinder, air cartridge, or mini air cartridge.
9. A method for performing an LAR test on a subject, wherein the subject has a larynx comprising left and right vocal folds which undergo closure along the medial edge of the vocal folds or incomplete medialization along the edge (adduction), and re-opening of the vocals folds (abduction), the method comprising evoking an LAR response in the subject and determining one or more physiological measurements of duration, velocity, and angles of motion of the subject’s VFs during the LAR.
10. The method of claim 9 wherein the method further comprises determining the pressure threshold to evoke VF medialization (adduction).
11. The method of claim 9 wherein the method comprises determining one or more of adduction phase duration, glottic closure duration, VF abduction duration, total LAR duration, and LAR onset latency.
12. The method of claim 11 wherein the method comprises determining the subject’s VF adduction phase duration by establishing the time interval between the subject’s rest frame immediately preceding VF adduction through an end frame defined by either the vocal folds approximating along the entire medial edge or in case of incomplete VF medialization, the moment wherein maximal medialization occurs.
13. The method of claim 11 wherein the method comprises determining the subject’s complete glottic closure duration by determining the time interval that the VFs remain approximated along the entire medial edge during a LAR response or, in case of incomplete VF medialization, the time interval of the smallest glottal gap.
14. The method of claim 11 wherein the method comprises determining the subject’s VF abduction duration by determining the time interval between one frame preceding the emergence of a glottal gap between the medial edges of the VFs and a frame wherein the VFs reach maximum abduction prior to resuming a next rest breathing cycle, or in cases of VF abduction phase hesitation, in which a predetermined number of consecutive frames defining a hesitation is followed by additional abduction, the time interval through a predetermined frame of the VF abduction hesitation.
15. The method of claim 11 wherein the method comprises determining the subject’s LAR onset latency by determining the time interval from pressure pulse delivery to the start of the LAR response.
16. The method of claim 11 wherein the method comprises determining the subject’s total LAR duration by determining the duration of time between the VF adduction phase start frame and VF abduction phase end frame.
17. The method of claim 9 wherein the method further comprises eliciting a laryngeal adductor reflex (LAR) response in the subject by providing the subject with one or more stable and adjustable pulses of pressure from a pressure system component in functional communication with a control system component, detecting the subject’s LAR response using a respiratory sensor unit, and determining the one or more physiological characteristics of the subject’s LAR response to the pressure delivered.
18. The method of claim 9 wherein one or more of the pressure pulsing component, respiratory sensor component, and the control component is automated.
19. The method of claim 9 wherein the subject’s larynx comprises an arytenoid mucosa, aryepiglottic fold, or other mucosal target at the entrance of the larynx, and the method comprises:
delivering a series of air pulses by an air pulse system to the arytenoid mucosa, aryepiglottic fold, or other mucosal target at the laryngeal entrance of the subject through a working channel of an endoscope having a tip,
adjusting the tip of the endoscope to ensure an adequate viewing field, and
determining one or more LAR metrics selected from the group consisting of VF adduction phase duration, glottic closure duration, VF abduction duration, total LAR duration, and LAR onset latency.
20. The method of claim 9 wherein the method comprises determining the velocity or angles of motion of the subject’s VFs during the LAR.