Author: claimsbot

1. A first wireless device comprising:
a wireless local area network (WLAN) module configured to selectively operate in a power save mode, wherein while not operating in the power save mode, the WLAN module is configured to communicate with a second wireless device;
a mobile phone radio module configured to receive, in accordance with a mobile phone protocol, base station time reference information from a base station;
a time module configured to maintain, at least while the WLAN module is operating in the power save mode, a base station time reference based on the base station time reference information received in accordance with the mobile phone protocol; and
a sleep module configured to control, based on the base station time reference maintained by the time module, when the WLAN module exits the power save mode to permit the WLAN module to communicate with the second wireless device.
2. The first wireless device of claim 1, further comprising an association module configured to receive and store settings common to a group including the first wireless device and the second wireless device.
3. The first wireless device of claim 2, wherein the association module is configured to request participation of the first wireless device in the group.
4. The first wireless device of claim 3, wherein the association module is configured to communicate with a coordination manager to request participation of the first wireless device in the group.
5. The first wireless device of claim 4, wherein the coordination manager specifies the base station from which the mobile phone radio module is to receive the base station time reference information.
6. The first wireless device of claim 4, wherein the coordination manager specifies a wireless channel for the WLAN module to use in communicating with the second wireless device.
7. The first wireless device of claim 4, wherein the coordination manager specifies an offset between the base station time reference information and base station time reference information from an alternative base station.
8. The first wireless device of claim 4, wherein the association module is configured to communicate with the coordination manager via the WLAN module.
9. The first wireless device of claim 1, wherein the sleep module is configured to (i) monitor, using the base station time reference, a length of time the WLAN module is in the power save mode, and (ii) control the WLAN module to exit the power save mode in response to the length of time reaching a predetermined value.
10. The first wireless device of claim 9, wherein the predetermined value is determined in agreement with the second wireless device.
11. A method of operating a first wireless device, the method comprising:
selectively operating a wireless local area network (WLAN) module of the first wireless device in a power save mode;
while not operating the WLAN module in the power save mode, communicating wirelessly with a second wireless device using the WLAN module;
receiving, in accordance with a mobile phone protocol, base station time reference information from a base station;
maintaining, at least while operating the WLAN module in the power save mode, a base station time reference based on the base station time reference information received in accordance with the mobile phone protocol; and
controlling, based on the maintained base station time reference, when the WLAN module exits the power save mode to permit the WLAN module to communicate with the second wireless device.
12. The method of claim 11, further comprising receiving and storing settings common to a group including the first wireless device and the second wireless device.
13. The method of claim 12, further comprising requesting participation of the first wireless device in the group.
14. The method of claim 13, further comprising communicating with a coordination manager to request participation of the first wireless device in the group.
15. The method of claim 14, further comprising, in response to the coordination manager, determining the base station from which to receive the base station time reference information.
16. The method of claim 14, further comprising, in response to the coordination manager, determining a wireless channel to use in communicating with the second wireless device.
17. The method of claim 14, further comprising, in response to the coordination manager, determining an offset between the base station time reference information and base station time reference information from an alternative base station.
18. The method of claim 14, further comprising communicating with the coordination manager via the WLAN module.
19. The method of claim 11, further comprising:
monitoring, using the base station time reference, a length of time the WLAN module is in the power save mode; and
controlling the WLAN module to exit the power save mode in response to the length of time reaching a predetermined value.
20. The method of claim 19, further comprising determining the predetermined value in agreement with the second wireless device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A test circuit formed on a surface of a semiconductor wafer having a plurality of chip areas for placing semiconductor product chips and scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested;
a selection circuit that sequentially selects at least one of the elements at a time; and
a plurality of pads used for testing the elements,
wherein the test circuit and the pads are placed within one of the scribe lines.
2. The test circuit according to claim 1, wherein a number of the elements included in the test circuit is at least 100.
3. The test circuit according to claim 1, wherein:
the plurality of pads comprise at least one input pad to input an input signal to the selected one of the elements and at least one output pad to output an output signal from the selected one of the elements.
4. The test circuit according to claim 3, wherein the test circuit further comprises:
at least one switch to supply the input signal from the input pad to the selected one of the elements or to supply the output signal of the selected one of the elements to the output pad.
5. The test circuit according to claim 3, wherein the plurality of pads further comprises at least one power supply pad to supply an electric power to the selection circuit and at least one control pad to supply a control signal to the selection circuit.
6. The test circuit according to claim 1, wherein:
the plurality of pads comprise at least three pads arranged along a longitudinal direction of one of the scribe lines; and
the plurality of elements are divided into at least two groups, each including at least two elements, at least two of the groups of elements are separately arranged in respective spaces between adjacent ones of the at least three pads.
7. The test circuit according to claim 6, wherein:
the selection circuit comprises a shift register having a plurality of shift stages, each for selecting at least one of the elements; and
the shift stages of the shift register that select the elements included in at least two of the groups are arranged together with corresponding elements in the respective spaces.
8. A test circuit formed on a surface of a semiconductor wafer having a plurality of chip areas for placing semiconductor product chips and scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested; and
a shift register comprising a plurality of shift stages, each for selecting a predetermined number of the elements, wherein:
each of the shift stages of the shift register and the predetermined number of the elements that can be selected by each of the shift stages are arranged along a direction generally perpendicular to a longitudinal direction of one of the scribe lines to form a unit having a dimension that can be placed within one of the scribe lines; and
the test circuit includes at least one block, each comprising a plurality of the units arranged along the longitudinal direction of one of the scribe lines.
9. The test circuit according to claim 8, wherein a number of the elements included in the test circuit is at least 100.
10. The test circuit according to claim 8, wherein:
the test circuit further comprises at least three pads used for testing the elements and arranged along the longitudinal direction of one of the scribe lines; and
the at least one block comprises at least two blocks separately arranged in respective spaces between adjacent ones of the at least three pads.
11. A semiconductor product wafer comprising:
a plurality of product chips placed within respective chip areas arranged on a surface of the semiconductor product wafer and a test circuit, the test circuit comprising:
a plurality of elements to be tested;
a selection circuit that sequentially selects at least one of the elements at a time; and
a plurality of pads used for testing the elements,
wherein the test circuit and the pads are placed within one of scribe lines that separate the chip areas.
12. The semiconductor product wafer according to claim 11, wherein a number of the elements included in the test circuit is at least 100.
13. The semiconductor product wafer according to claim 11, wherein:
the plurality of pads comprise at least three pads arranged along a longitudinal direction of one of the scribe lines; and
the plurality of elements are divided into at least two groups, each comprising at least two of the elements,
wherein at least two of the groups of elements are separately arranged in respective spaces between adjacent ones of the at least three pads.
14. The semiconductor product wafer according to claim 13, wherein:
the selection circuit comprises a shift register comprising a plurality of shift stages, each for selecting at least one of the elements; and
the shift stages of the shift register that select the elements included in at least two of the groups are arranged together with the corresponding elements in the respective spaces.
15. A semiconductor product wafer comprising:
a plurality of product chips placed within respective chip areas arranged on a surface of the semiconductor product wafer and a test circuit placed within one of scribe lines between the chip areas, the test circuit comprising:
a plurality of elements to be tested; and
a shift register comprising a plurality of shift stages, each for selecting a predetermined number of the elements, wherein:
each of the shift stages of the shift register and the predetermined number of the elements that can be selected by the each of the shift stages are arranged along a direction generally perpendicular to a longitudinal direction of one of the scribe lines to form a unit having a dimension that can be placed within one of the scribe lines; and
the test circuit comprises at least one block, each comprising a plurality of the units arranged along the longitudinal direction of one of the scribe lines.
16. The semiconductor product wafer according to claim 15, wherein a number of the elements included in the test circuit is at least 100.
17. The semiconductor product wafer according to claim 15, wherein:
the test circuit further comprises at least three pads used for testing the elements and arranged along the longitudinal direction of one of the scribe lines; and
the at least one block comprises at least two blocks separately arranged in respective spaces between adjacent ones of the at least three pads.
18. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers by the manufacturing process, each of the product wafers comprising:
a plurality semiconductor product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and
a test circuit placed within one of scribe lines between the chip areas, the test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time;

testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers; and
evaluating results of the testing to monitor the manufacturing process.
19. The method according to claim 18, wherein a number of the elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before a decrease of a yield of the semiconductor product chips occurs.
20. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers including different types of semiconductor product wafers at an arbitrary ratio in an arbitrary order by the manufacturing process, each of the different types of semiconductor product wafers comprising:
a plurality of one of different types of product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and
a common test circuit placed within one of scribe lines between the chip areas, the common test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time;

selecting a plurality of the manufactured semiconductor product wafers comprising at least two of the different types of the semiconductor product wafers;
testing each of the elements in the test circuit in the selected semiconductor product wafers; and
evaluating results of the testing to monitor the manufacturing process.
21. The method according to claim 20, wherein a number of elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before a decrease in a yield of the different types of product chips occurs.
22. The method according to claim 20, wherein the evaluating step is performed when a decrease in a yield of at least one of the different types of product chips occurs.
23. The method according to claim 20, further comprising:
adjusting the manufacturing process according to a result of the evaluating to prevent occurrence of a decrease in a yield of at least one of the different types of product chips.
24. The method according to claim 20, wherein the plurality of manufactured semiconductor product wafers are selected such that the selected semiconductor product wafers are manufactured with approximately a fixed interval.
25. The method according to claim 20, wherein different customers provide mask patterns used to manufacture the different types of product chips.
26. A method of monitoring a manufacturing process for manufacturing semiconductor product wafers, comprising:
manufacturing semiconductor product wafers, each including a plurality of product chips and a test circuit comprising a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the plurality of elements at a time;
testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers;
evaluating results of the testing; and
adjusting the manufacturing process according to the results of the evaluating to prevent occurrence of a decrease in a yield of the product chips.
27. The method according to claim 26, wherein a number of the elements included in the test circuit are sufficiently large to detect a change of a state of the manufacturing process before the decrease in the yield of the product chips occurs.

1. A printed circuit board, comprising:
a printed wiring board;
a semiconductor which is mounted on the printed wiring board and includes a semiconductor chip, the semiconductor having a first power supply terminal, a second power supply terminal, a first ground terminal, and a second ground terminal;
a first circuit for supplying power to the semiconductor chip, the first circuit comprising:
a source power supply,
a first power supply wiring for connecting the first power supply terminal of the semiconductor with the source power supply,
a first ground wiring for connecting the first ground terminal of the semiconductor with the source power supply, and
a first bypass capacitor which connects the first power supply wiring and the first ground wiring; and

a second circuit comprising:
a second power supply wiring connected to the second power supply terminal of the semiconductor,
a second ground wiring connected to the second ground terminal of the semiconductor, and
a second bypass capacitor which connects the second power supply wiring and the second ground wiring, wherein:

the first power supply terminal and the second power supply terminal are at the same potential;
the first power supply terminal is electrically connected to the second power supply terminal only within the semiconductor; and
the first ground wiring is electrically connected to the second ground wiring only within the semiconductor.
2. A printed circuit board according to claim 1, wherein:
the printed circuit board has a multilayer structure including a power supply layer and a ground layer;
the first power supply wiring is comprised of a power supply wiring provided in the power supply layer and a first through hole;
the first ground wiring is comprised of a ground wiring provided in the ground layer and a second through hole;
the first bypass capacitor is connected to the semiconductor through the first through hole and the second through hole;
the second power supply wiring is comprised of a third through hole;
the second ground wiring is comprised of a fourth through hole; and
the second bypass capacitor is connected to the semiconductor through the third through hole and the fourth through hole.
3. A printed circuit board according to claim 1, wherein:
the first power supply wiring and the second power supply wiring each are connected to the IC chip through a power supply pattern and a bonding wire within the semiconductor and are connected to each other in the IC chip; and
the first ground wiring and the second ground wiring each are connected to the IC chip through a ground pattern and a bonding wire within the semiconductor and are connected to each other in the IC chip.
4. A printed circuit board according to claim 1, wherein:
the first bypass capacitor has a resonance frequency in a first frequency band; and
the second bypass capacitor has a resonance frequency in a second frequency band higher than the first frequency band.
5. A printed circuit board according to claim 4, wherein:
the first bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the first frequency band; and
the second bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the second frequency band and reduces propagation of the power ground noise in the second frequency band to a side of the source power supply.
6. A printed circuit board according to claim 5, wherein an S21 characteristic (transmission characteristic) from the semiconductor chip to the source power supply in the second frequency band is free from a resonance frequency at which the transmission characteristic has a peak.
7. A printed circuit board, comprising:
a printed wiring board;
a semiconductor which is mounted on the printed wiring board and includes a semiconductor chip, the semiconductor having a first power supply terminal, a second power supply terminal, a first ground terminal, and a second ground terminal;
a first circuit for supplying power to the semiconductor chip, the first circuit comprising:
a source power supply,
a first power supply wiring for connecting the first power supply terminal of the semiconductor with the source power supply,
a first ground wiring for connecting the first ground terminal of the semiconductor with the source power supply, and
a first bypass capacitor which connects the first power supply wiring and the first ground wiring; and

a second circuit comprising:
a second power supply wiring connected to the second power supply terminal of the semiconductor;
a second ground wiring for connecting the second ground terminal of the semiconductor with the source power supply; and
a second bypass capacitor which connects the second power supply wiring and the second ground wiring, wherein:

the first power supply terminal and the second power supply terminal are at the same potential; and
the first power supply terminal is electrically connected to the second power supply terminal only within the semiconductor.
8. A printed circuit board according to claim 7, wherein:
the printed circuit board has a multilayer structure including a power supply layer and a ground layer;
the first power supply wiring is comprised of a power supply wiring provided in the power supply layer and a first through hole;
the first ground wiring is comprised of a ground wiring provided in the ground layer and a second through hole;
the first bypass capacitor is connected to the semiconductor through the first through hole and the second through hole;
the second power supply wiring is comprised of a power supply wiring provided in the power supply layer and a third through hole;
the second ground wiring is comprised of a fourth through hole; and
the second bypass capacitor is connected to the semiconductor through the third through hole and the fourth through hole.
9. A printed circuit board according to claim 7, wherein:
the first power supply wiring and the second power supply wiring each are connected to the IC chip through a power supply pattern and a bonding wire within the semiconductor and are connected to each other in the IC chip; and
the first ground wiring and the second ground wiring each are connected to the IC chip through a ground pattern and a bonding wire within the semiconductor and are connected to each other in the IC chip.
10. A printed circuit board according to claim 7, wherein:
the first bypass capacitor has a resonance frequency in a first frequency band; and
the second bypass capacitor has a resonance frequency in a second frequency band higher than the first frequency band.
11. A printed circuit board according to claim 10, wherein:
the first bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the first frequency band; and
the second bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the second frequency band and reduces propagation of the power ground noise in the second frequency band to a side of the source power supply.
12. A printed circuit board according to claim 11, wherein an S21 characteristic (transmission characteristic) from the semiconductor chip to the source power supply in the second frequency band is free from a resonance frequency at which the transmission characteristic has a peak.
13. A circuit structure for power supply, comprising:
a semiconductor chip;
a source power supply;
a first circuit for supplying power to the semiconductor chip, the first circuit comprising:
the semiconductor chip,
the source power supply,
a first power supply path for connecting the semiconductor chip with the source power supply,
a first ground path for connecting the semiconductor chip with the source power supply, and
a first bypass capacitor which connects the first power supply path and the first ground path; and

a second circuit comprising:
the semiconductor chip,
a second bypass capacitor,
a second power supply path for connecting the semiconductor chip with the second bypass capacitor, and
a second ground path for connecting the semiconductor chip with the second bypass capacitor, wherein:

the first power supply path and the second power supply path are at the same potential and are electrically connected to each other only within the semiconductor chip.
14. A circuit structure for power supply according to claim 13, wherein:
the first bypass capacitor has a resonance frequency in a first frequency band; and
the second bypass capacitor has a resonance frequency in a second frequency band higher than the first frequency band.
15. A circuit structure for power supply according to claim 14, wherein:
the first bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the first frequency band; and
the second bypass capacitor reduces a power ground noise of the IC chip at an operating frequency within the second frequency band and reduces propagation of the power ground noise in the second frequency band to a side of the source power supply.
16. A circuit structure for power supply according to claim 14, wherein an S21 characteristic (transmission characteristic) from the semiconductor chip to the source power supply in the second frequency band is free from a resonance frequency at which the transmission characteristic has a peak.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
passing data from a producer processor to an inter-processor ring structure, and setting a bit in a self-destruct register;
reading the self-destruct register by a consumer processor to determine the number of bytes of data to read from the inter-processor ring, while clearing the self-destruct register; and
removing from the ring, data passed to the ring from the producer processor, with the amount of data removed from the ring corresponding to a number of bits set in the self-destruct register.
2. The method of claim 1 wherein the inter-processor ring structure resides in memory.
3. The method of claim 1 wherein the producer processor data are messages that it places on the inter-processor ring.
4. The method of claim 1 wherein the bit location in the register is determined by using a counter on the producer processor.
5. The method of claim 1 wherein the counter that the producer uses to select the next bit to set in the self-destruct register is global to all threads on the producer processor that place data on the inter-processor ring.
6. The method of claim 1 wherein the self-destruct register enables synchronization between the producer and consumer processors for data passing through the inter-processor ring.
7. The method of claim 1 wherein the self-destruct register during a write operation of a bit in the bit register is logically \u201cOred\u201d with existing bits in the self-destruct register in an atomic operation.
8. The method of claim 1 wherein a read operation from the register returns the current state of the register and atomically clears the register.
9. The method of claim 8 wherein the current state of the register is all bits set following the last read operation to the register or after a reset.
10. The method of claim 1 wherein the consumer processor uses a Find First bit Set (FFS) microinstruction with the self-destruct register to immediately determine if the ring needs processing.
11. The method of claim 1 further comprising:
signaling by a producer thread in the producer microengine to a consumer microengine when the producer microengine places data on the inter-processor ring.
12. The method of claim 11 further comprising:
checking the inter-processor ring by the consumer processor if the consumer processor receives a signal that indicates that at least one message is waiting in the ring; and
checking the self-destruct register once the signal is received by the consumer processor to determine the number of messages waiting on the ring.
13. The method of claim 1 wherein the producer processor and the consumer processor are micro-engines on a network processor device.
14. A method to read data off of an inter-processor ring comprises:
waking up a thread when a signal sent from a producer is set;
reading a self-destruct register;
setting a value in a local register;
checking the value in the local register and if the local register value indicates that data are available,
processing data off of the inter-processor ring; and
removing one of the set bits from the local register.
15. The method of claim 14 wherein if the value indicates that data are not available the process exits.
16. The method of claim 14 wherein the counter that the producer uses to select the next bit to set in the self-destruct register is global to all threads on the producer processor that place data on the inter-processor ring.
17. The method of claim 14 wherein self-destruct register enables synchronization between the producer and consumer processors for data passing through the inter-processor ring.
18. A system, comprising:
an inter-processor ring;
a producer processor that passes data to the inter-processor ring, while setting a bit in a self-destruct register;
a consumer processor to read the self-destruct register to determine the number of bytes of the data to read from the inter-processor ring and clearing the self-destruct register to remove from the ring, data passed to the ring from the producer processor, with the amount of data removed from the ring corresponding to a number of bits set in the self-destruct register.
19. The system of claim 18 wherein the inter-processor ring structure is memory ring.
20. The system of claim 18 wherein the producer processor data are messages that it places on the inter-processor ring.
21. The system of claim 18 wherein the bit location in the register determined by using a counter on the producer processor.
22. The system of claim 18 wherein the counter that the producer uses to select the next bit to set in the self-destruct register is global to all threads on the producer processor that place data on the inter-processor ring.
23. The system of claim 18 wherein the self-destruct register enables synchronization between the producer and consumer processors for data passing through the inter-processor ring.
24. The system of claim 18 wherein the self-destruct register during a write operation of a bit in the bit register is logically \u201cOred\u201d with existing bits in the self-destruct register in an atomic operation.
25. The system of claim 24 wherein a read operation from the register returns the current state of the register and atomically clears the register.
26. The system of claim 18 wherein the consumer processor uses a Find First bit Set (FFS) microinstruction with the self-destruct register to immediately determine if the ring needs processing.
27. The system of claim 18 wherein the producer thread in the producer microengine signals a consumer microengine when the producer microengine places data on the inter-processor ring.
28. A system comprising:
an inter-processor ring;
a global_cnt register;
a producer processor passing data to the inter-processor ring structure to populate the ring with bytes in a message, while setting a bit in the global_cnt register;
a self-destruct register having a bit position that is set corresponding to the bit in the global_cnt register; and
a consumer processing microengine that is signaled by a thread in the producer microengine that a message is available to be read, the consumer processing microengine reading the self-destruct register by a consumer processor to determine and remove the number of bytes of data to read from the inter-processor ring while clearing the self-destruct register.
29. The system of claim 28 wherein the global_cnt is checked to determine if the value in the register exceeds a maximum number of bits in the self-destruct register, and if the count is exceeded, the global_cnt is reset to bit 0.
30. A system comprises:
a network processor having at least a producer microengine and a consumer microengine, a self-destruct register and a local register;
an inter-processor ring structure accessible by the network processor;
the network processor; and
a computer readable medium for storing instructions causing a consumer microengine to:
read the self-destruct register to determine the number of bytes of data to read and remove from the inter-processor ring and set a value in a local register while clearing the self-destruct register,
check the value in the local register and if the local register value indicates that messages are available,
process data off of the inter-processor ring, and
remove one of the set bits from the local register;
a media access controller device to send packets to and from the network processor.
31. The system of claim 30 wherein the media access controller device is a 10100 BaseT Octal media access controller.
32. The system of claim 30 wherein the media access controller device is a Gigabit Ethernet device.
33. The system of claim 30 wherein the register that a producer processor uses to select the next bit to set in the self-destruct register is global to all threads on the producer processor that place data on the inter-processor ring.
34. The system of claim 30 wherein the system is a router.
35. A computer program product residing on a computer readable medium for synchronizing messaging between a pair of processing engines, comprises instructions for causing a processor to:
pass data from a producer processor to an inter-processor ring structure, while setting a bit in a self-destruct register;
read the register by a consumer processor to determine the number of bytes of data to read and remove from the inter-processor ring, while clearing the self-destruct register and removing from the ring, data passed to the ring from the producer processor, with the amount of data removed from the ring corresponding to a number of bits set in the self-destruct register.
36. The computer program product of claim 35 wherein the producer processor data are messages that it places on the inter-processor ring.
37. The computer program product of claim 35 wherein the bit location in the self-destruct register are determined by using a counter on the producer processor.
38. The computer program product of claim 35 wherein the counter that the producer processor uses to select the next bit to set in the self-destruct register is global to all threads on the producer processor that place data on the inter-processor ring.
39. The computer program product of claim 35 wherein the computer program executes an instruction in the consumer processor to determine if the ring needs processing.
40. The computer program product of claim 35 further comprising instructions to:
signal by the producer thread in the producer microengine of a consumer microengine when the producer microengine places data on the inter-processor ring.
41. The computer program product of claim 35 further comprising instructions to:
check the inter-processor ring by the consumer processor if by the consumer processor receives a signal that indicates that at least one message is waiting in the ring; and
checking the self-destruct register once the signal is received by the consumer processor to determine the number of messages waiting on the ring.