Author: claimsbot

1. A photo- andor thermo-curable copolymer having polymerizable unsaturated groups in side chains, which is obtainable by reacting a copolymer (P) with an epoxy-containing polymerizable unsaturated compound (C), the copolymer (P) containing monomer units derived from a carboxyl-containing polymerizable unsaturated compound (A) and monomer units derived from at least one selected from epoxy-containing polymerizable unsaturated compounds (B) represented by following Formulae (1) and (2):
wherein Ras each represent a hydrogen atom or a hydroxyl-substituted or -unsubstituted alkyl group having 1 to 4 carbon atoms; and Rbs each represent a single bond or an alkylene group having 1 to 18 carbon atoms which may contain heteroatom(s),
wherein the epoxy group of the epoxy-containing polymerizable unsaturated compound (C) has been added to part of the carboxyl groups of the copolymer (P).
2. The photo- andor thermo-curable copolymer according to claim 1, wherein the copolymer (P) further contains monomer units derived from a carboxyl- and epoxy-free polymerizable unsaturated compound (D), in addition to the monomer units derived from the carboxyl-containing polymerizable unsaturated compound (A) and the monomer units derived from the at least one epoxy-containing polymerizable unsaturated compound (B).
3. The photo- andor thermo-curable copolymer according to claim 2, wherein the carboxyl- and epoxy-free polymerizable unsaturated compound (D) is at least one polymerizable unsaturated compound selected from the group of monomers consisting of (D1) styrene which may be substituted with alkyl or hydroxyl, (D2) an unsaturated carboxylic acid ester represented by following Formula (3):
wherein R1 represents a hydrogen atom or an alkyl group having 1 to 7 carbon atoms; R2 represents one selected from a linear or branched-chain alkyl group having 1 to 18 carbon atoms, an alkenyl group having 2 to 18 carbon atoms, an aryl group, an aralkyl group, a \u2014(R3\u2014O)m\u2014R4 group (wherein R3 represents a bivalent hydrocarbon group having 1 to 12 carbon atoms, R4 represents hydrogen atom or a hydrocarbon group, and \u201cm\u201d denotes an integer of 1 or more), and a group with a monocyclic or polycyclic structure containing five or more members,
and (D3) a N-substituted maleimide represented by following Formula (4):
wherein R5 represents one selected from a substituted or unsubstituted phenyl group, a substituted or unsubstituted aralkyl group, and a substituted or unsubstituted cycloalkyl group.
4. A curable resin composition comprising the photo- andor thermo-curable copolymer of any one of claims 1 to 3.
5. The curable resin composition according to claim 4, further comprising a curing agent andor a curing catalyst.
6. A cured article prepared through curing of the curable resin composition of claim 4.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of locating a fault within an array of integrated circuits comprising:
establishing row propagation speeds for gated timing signals passed through a number of rows of serially connected interconnect modules of an array of serially connected interconnect modules;
establishing a row reference propagation speed based upon said row propagation speeds;
comparing said row propagation speeds individually to said row reference propagation speed to establish a row fault criteria;
establishing column propagation speeds for gated timing signals passed through a number of columns of serially connected interconnect modules of said array of serially connected interconnect modules;
establishing a column reference propagation speed based upon said column propagation speeds;
comparing said column propagation speeds individually to said column reference propagation speed to establish a column fault criteria;
generating a matrix of row and column fault conditions based upon said row and column fault criteria; and,
locating said fault within said-array of interconnect modules by utilizing said row and column fault conditions within said matrix that correspond to an array location.
2. The method of claim 1 wherein said step of establishing row propagation speeds for gated timing signals passed through a number of rows of serially connected interconnect modules of an array of serially connected interconnect modules further comprises:
aligning said number of rows of serially connected interconnect modules substantially parallel with a first axis.
3. The method of claim 1 wherein said step of establishing column propagation speeds for gated timing signals passed through a number of columns of serially connected interconnect modules of said array of serially connected interconnect modules further comprises:
aligning said number of columns of serially connected interconnect modules substantially parallel to a second axis that is substantially perpendicular to said first axis.
4. The method of claim 1 further comprising the step of:
applying a row select signal input into said array of interconnect modules to switch a data-in signal path only through said rows of said array of interconnect modules.
5. The method of claim 1 further comprising the step of:
applying a column select signal input into said array of interconnect modules to switch a data-in signal path through said columns of said array of interconnect modules.
6. The method of claim 1 further comprising the step of:
registering said row propagation speeds for said rows of serially connected interconnect modules of said subarray with a row scan flop logic circuit.
7. The method of claim 6 wherein said step of registering said row propagation speeds for said rows of serially connected interconnect modules of said subarray with said row scan flop logic circuit further comprises:
driving a row clock circuit with a gated clock and generating a gated row clock signal to load data from said row scan flop logic circuit.
8. The method of claim 7 further comprising the step of:
varying said gated row clock pulse signal so that said row clock pulse will arrive at a predetermined time.
9. The method of claim 1 further comprising the step of:
registering said column propagation speeds for said columns of serially connected interconnect modules of said subarray with a column scan flop logic circuit.
10. The method of claim 9 wherein said step of registering said column propagation speeds for said columns of serially connected interconnect modules of said subarray with said column scan flop logic circuit further comprises:
driving a column clock circuit with a gated clock and generating a gated column clock signal to load data from said column scan flop logic circuit.
11. The method of claim 10 further comprising the step of:
varying said gated column clock pulse signal so that said column clock pulse will arrive at a predetermined time.
12. The method of claim 1 wherein said row reference propagation speed is established for a particular row by said row propagation speeds within physical proximity of said particular row.
13. The method of claim 1 wherein said row reference propagation speed is established for a particular row by statistical methods performed on one or more row propagation speeds of said rows of serially connected interconnect modules.
14. The method of claim 1 wherein said column reference propagation speed is established for a particular column by said column propagation speeds within physical proximity of said particular column.
15. The method of claim 1 wherein said column reference propagation speed is established for a particular column by statistical methods performed on one or more column propagation speeds of said column of serially connected interconnect modules.
16. The method of claim 1 wherein said method of locating a fault within an array of integrated circuits process is repeated on multiple layers of said arrays of serially connected interconnect modules.
17. The method of claim 16 further comprising the step of:
generating a layer matrix of said row and said column fault conditions based upon said row and column fault criteria for each said layer of said arrays of serially connected interconnect modules; and,
locating a fault within said three-dimensional array of interconnect modules by utilizing two or more said layer matrix of said row and said column fault conditions.
18. A method of testing an array of interconnect modules comprising:
providing a speed fault reliability and yield test vehicle, said test vehicle comprising:
a first gated clock circuit with at least one layer comprising a number of rows of serially connected interconnect modules with row outputs connected within an array of serially connected interconnect modules, a second gated clock circuit with at least one layer comprising a number of columns of serially connected interconnect modules with column outputs connected within said array of serially connected interconnect modules, a level select circuit that allows input from one or more said row outputs or one or more said column outputs, a row scan flop logic circuit that receives said row outputs of said rows of serially connected interconnect modules from said level select circuit and loads data in a parallel manner from each row into row shift registers, a column scan flop logic circuit that receives said column outputs of said columns of serially connected interconnect modules from said level select circuit and loads data in a parallel manner from each column into column shift registers, a row select switch and a column select switch input into said first gated clock circuit, said second gated clock circuit that switches the path of said data-in signal either through said rows of said array of interconnect modules or through said columns of said array of interconnect modules, a gated clock signal that clocks said column scan flop logic circuit to output data through a column data-out signal output when said column select signal is selected or clocks said row scan flop logic circuit to scan data out through a row data-out signal output when said row select signal is selected, a select enable input to reset said row and column scan flop logic circuits and allow input of a data-in signal, said data-in signal that is input into said array of interconnect modules, said data signal traveling through and registering propagation timing through either said rows or said columns of said array of interconnect modules, a row data-out signal output from said row shift registers when said data-in signal is transmitted through said rows of said interconnect modules, said row data-out signal containing propagation timing of each said row of said interconnect modules, a column data-out signal output from said column shift registers when said data-in signal is transmitted through said columns of said interconnect modules, said column data-out signal containing propagation timing of each said column of said interconnect modules;
applying a signal to either said row select input or said column select input;
applying a signal to a level select input of said level select circuit;
applying a first select enable signal to said select enable input;
applying a first clock signal to said clock signal input applying a first data-in signal to said data-in input;
reading a row data signal from said row data-out output;
applying a second scan enable signal to said scan enable input;
applying a second clock signal to said clock signal input applying a second data-in signal to said data-in input;
reading a column data signal from said column data-out output;
determining if said row and column data is within specification by comparing said row and column data output to expected values;
locating a failure on said test vehicle by utilizing row and column output data that is not within said specification to form an error matrix array, wherein said error matrix array correspond to said rows and columns of said array of interconnect modules; and,
determining said row and column data and creating said error matrix array for each said layer of said array of serially connected interconnect modules to form a dimensional error array map of said interconnect modules.
19. A speed fault test vehicle for locating a fault within an array of interconnect modules comprising:
a first gated clock circuit with at least one layer comprising a number of rows of serially connected interconnect modules with row outputs and connected within an array of serially connected interconnect modules that establishes row propagation characteristics for each said row of serially connected interconnect modules;
a second gated clock circuit with at least one layer comprising a number of columns of serially connected interconnect modules with column outputs and connected within said array of serially connected interconnect modules that establishes column propagation characteristics for each said column of serially connected interconnect modules;
a level select circuit that allows serial input of one or more said row propagation characteristics or one or more said column propagation characteristics;
a row scan flop logic circuit that receives said row propagation characteristics;
a column scan flop logic circuit that receives said column propagation characteristics;
a first comparator that compares said row propagation characteristics of each said row of serially connected interconnect modules to a reference row value, said comparison establishing a row fault criteria;
a second comparator that compares said column propagation characteristics of each said column of serially connected interconnect modules to a reference column value, said comparison establishing a column fault criteria;
a matrix of row and column fault conditions that is generated based upon one or more said layers of said row and column fault criteria; and,
a fault location map generated by utilizing said layers of said row and column fault conditions within said matrix that correspond to array locations.
20. The device of claim 19 wherein said number of rows of serially connected interconnect modules is substantially parallel has a first axis and said number of columns of serially connected interconnect modules is substantially parallel to a second axis that is substantially perpendicular to said first axis.
21. The device of claim 19 wherein a rowcolumn select signal input into said array of interconnect modules is used to switch a data-in signal path either through said rows of said array of interconnect modules or said columns of said array of interconnect modules.
22. The device of claim 19 wherein a gated row clock pulse signal is varied so that a row clock pulse will arrive at said a row scan flop logic circuit at a predetermined time.
23. The device of claim 19 wherein a gated column clock pulse signal is varied so that a column clock pulse will arrive at said a column scan flop logic circuit at a predetermined time.
24. The device of claim 19 wherein said reference row value is established for a particular row by said row propagation characteristics within physical proximity of said particular row of serially connected interconnect modules.
25. The device of claim 19 wherein said reference row value is established for a particular row by statistical methods performed on one or more row propagation characteristics of said rows of serially connected interconnect modules.
26. The device of claim 19 wherein said reference column value is established for a particular column by said column propagation characteristics within physical proximity of said particular column of serially connected interconnect modules.
27. The device of claim 19 wherein said reference column value is established for a particular column by statistical methods performed on one or more column propagation characteristics of said columns of serially connected interconnect modules.
28. A speed fault test vehicle for locating a fault within an array of interconnect modules comprising:
a first gated clock circuit with at least one layer comprising a number of rows of serially connected interconnect modules and with row outputs connected within an array of serially connected interconnect modules that establishes row propagation characteristics for each said row of serially connected interconnect modules;
a second gated clock circuit with at least one layer comprising a number of columns of serially connected interconnect modules and with column outputs connected within said array of serially connected interconnect modules that establishes column propagation characteristics for each said column of serially connected interconnect modules;
a level select circuit that allows serial input of one or more said row outputs or one or more said column outputs;
a row scan flop logic circuit that receives said row outputs of said rows of serially connected interconnect modules from said level select circuit and loads data in a parallel manner from each row into row shift registers;
a column scan flop logic circuit that receives said column outputs of said columns of serially connected interconnect modules from said level select circuit and loads data in a parallel manner from each column into column shift registers;
a row select switch and a column select switch input into said first gated clock circuit, said second gated clock circuit of interconnect modules that switches the path of said data-in signal either through said rows of said array of interconnect modules or through said columns of said array of interconnect modules
a gated clock signal that clocks said column scan flop logic circuit to output data through a column data-out signal output when said column select signal is selected or clocks said row scan flop logic circuit to scan data out through a row data-out signal output when said row select signal is selected;
a select enable input to reset said row and column scan flop logic circuits and allow input of a data-in signal, said data-in signal that is input into said array of interconnect modules, said data signal traveling through and registering propagation timing through either said rows or said columns of said array of interconnect modules;
a row data-out signal output from said row shift registers when said data-in signal is transmitted through said rows of said interconnect modules, said row data-out signal containing propagation timing of each said row of said interconnect modules; and,
a column data-out signal output from said column shift registers when said data-in signal is transmitted through said columns of said interconnect modules, said column data-out signal containing propagation timing of each said column of said interconnect modules.

1. A method of friction plug welding repair comprising the steps of:
a) locating a defect in a weld that joins two sections of material together;
b) removing weld material at the defect to form an opening;
c) placing a plug in the opening, wherein the plug has top and bottom end portions, the top end portion being tapered and larger in diameter than the opening, wherein the top end portion has two sections including a gradually tapering section and a rapidly tapering section, said rapidly tapering section defining the maximum diameter of the top end portion;
d) pulling the bottom end portion of the plug so that the top end portion of the plug engages the opening; and
e) rotating the plug to heat up the plug during pulling of step d.
2. The method of claim 1 wherein in step c, the plug top end portions includes two separate sections including a frustoconical smaller diameter section and a larger diameter section.
3. The method of claim 1 wherein the defect in step a is less than one inch in length.
4. The method of claim 1, further comprising the step of placing a backing plate member against the sections of material.
5. The method of claim 1 wherein step b includes drilling a hole to form the opening.
6. The method of claim 1 wherein the opening formed in step b is a tapered opening.
7. The method of claim 6 wherein the opening has a maximum diameter, and the top end portion of the plug has a section with a diameter larger than said opening maximum diameter.
8. The method of claim 1 wherein the plug top end portion has a gradually tapering section along a majority of the length of the top end portion, and a rapidly tapering section of maximum diameter that extends over a minority of the length of the top end portion.
9. The method of claim 1 wherein the top end portion includes an annular curved surface.
10. The method of claim 9 wherein the curved surface has a radius of less than inches.
11. The method of claim 9 wherein the curved surface has a radius of less than about {fraction (316)} inches.
12. A method of friction plug welding repair comprising the steps of:
a) locating a defect in a weld that joins two sections of material together;
b) removing weld material at the defect to form an opening;
c) placing a plug in the opening, the plug having top and bottom end portions, the top end portion being generally frustoconically shaped at least in part, the top end portion having an enlarged diameter tapered portion that is larger in diameter than the frustoconical section’s largest diameter;
d) pulling the bottom end portion of the plug so that the top end portion of the plug engages the opening; and
e) rotating the plug with sufficient revolutions per unit time that the combined effect of the enlarged diameter of the plug at the top end and the rotation enables the plug to heat up the plug top, and wherein the plug top provides radial and axial pressure.
13. The method of claim 12 wherein the plug is rotated in step e at between 1,000 and 7,000 revolutions per minute.
14. The method of claim 12 wherein the plug is rotated instep e at between 1,000 and 7,000 revolutions per minute.
15. The method of claim 12 wherein the plug is pulled in step d with a tension of between 1,000 and 20,000 pounds.
16. The method of claim 12 wherein the plug is pulled in step d with a tension of between 1,000 and 20,000 pounds.
17. A method of friction plug welding repair comprising the steps of:
a) locating a defect in a weld that joins two sections of material together;
b) removing weld material at the defect to form an opening;
c) placing a tapered plug in the opening, a first end of the plug having an annular curved portion that defines the greatest amount of taper per unit length of the plug;
d) pulling a second end portion of plug so that the first end portion of the plug engages the opening; and
e) rotating the plug to heat up the plug at the first end during the pulling step d.
18. The method of claim 17 wherein the plug is rotated in step e at between about 1,000 and 7,000 revolutions per minute.
19. The method of claim 17 wherein the plug is rotated in step e at between about 1,000 and 7,000 revolutions per minute.
20. The method of claim 17 wherein the plug is pulled in step d with a tension of between about 1,000 and 20,000 pounds.
21. The method of claim 17 wherein the plug is pulled in step d with a tension of between about 1,000 and 20,000 pounds.
22. A friction pull plug welding apparatus for repairing a defect in a weld that has been removed, leaving a defect opening in the weld, comprising;
a) a rotary tool;
b) a chuck that is supported by the rotary tool;
c) a backing member;
d) a pull plug body that fits the defect opening, wherein the pull plug includes first and second sections, the first section being sized and shaped to fit through the defect opening, the second section having a part that is sized and shaped to not fit through the opening, said second section including a maximum diameter portion with an annular surface that rapidly increases in diameter when measured longitudinally and when compared to the overall length of the pull plug body.
23. The friction pull plug welding apparatus of claim 22 wherein the rotary tool rotates at between about 4000-6000 revolutions per minute during use.
24. The friction pull plug welding apparatus of claim 22 wherein the rotary tool rotates at least about 4000 revolutions per minute during use.
25. The friction pull plug welding apparatus of claim 22 wherein the chuck has a tensile strength of at least 1,000 pounds.
26. The friction pull plug welding apparatus of claim 22 wherein the chuck has a tensile strength of between about 1,000 and 20,000 pounds.
27. The friction pull plug welding apparatus of claim 22 wherein the chuck and pull plug body are removably connectable.
28. The friction pull plug welding apparatus of claim 22 wherein the chuck and pull plug body are removably connectable with a threaded connection.
29. The friction pull plug welding apparatus of claim 22 wherein the pull plug body annular surface is a curved annular surface.
30. The friction pull plug welding apparatus of claim 22 wherein the pull plug body annular surface is a curved annular surface having a cross section with a radius of curvature of less than one inch.
31. The friction pull plug welding apparatus of claim 22 wherein the pull plug body annular surface is a curved annular surface having a cross section with a radius of curvature of about three sixteenths inches.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Stripping tool for a coaxial cable, said cable comprising a jacket, a non-helically corrugated outer conductor comprising a repeated pattern of crests and valleys and a dielectric material between said outer conductor and an inner conductor, said tool comprising means for cutting off the jacket, the outer conductor, the dielectric material between the outer conductor and inner conductor and the inner conductor at well-defined relative positions in the longitudinal direction of the cable, characterised in that a guide part (10) is provided for determining a well-defined position relative to said pattern of the corrugation of the outer conductor (9), such that said relative cut-off-positions are defined relative to this pattern.
2. Stripping tool according to claim 1, characterised in that said guide part (10) comprises at least one position-determining member (12, 13, 14, 16), a part (16) of which member being adapted to sense the longitudinal position of said valleys of the corrugation of the outer conductor (9).
3. Stripping tool according to claim 1, characterised in that said guide part (10) comprises at least one position determining member (12, 13, 14, 16), a part (16) of which member being adapted to sense the longitudinal position of said crests of the corrugation of the outer conductor (9).
4. Stripping tool according to any of the preceding claims, characterised in that said guide part (10) comprises a radially resilient tubular body, the outer circumferential surface of which is subdivided into a first region (12) with a first diameter, a second region (14), the diameter of which can be either equal to the diameter of said first region or different herefrom, and a third region forming a radially outwardly extending abutment surface (13).
5. Stripping tool according to claim 4, characterised in that said first (12), second (14) and third (13) regions are provided with a plurality of longitudinally extending slits (15) through the wall of said guide part (10) in order to provide said radial resiliency, and that said guide part (10) at the longitudinal end hereof adjoining said second region (14) is provided with a resilient tubular section (11)
6. Stripping tool according to any of the preceding claims characterised in that the inner diameter of said guide part (10) corresponds to the outer diameter of the coaxial cable.
7. Stripping tool according to any of the preceding claims, characterised in that it furthermore comprises a jacket cutting means (1) for removing the jacket (7) of the cable over a predetermined longitudinal distance (I, X2) from one end (8) of the cable, where said jacket cutting means (1) comprises a tubular body (2), the inner diameter of which corresponds to the outer diameter of the cable, where said tubular body (2) is open at one of its longitudinal ends (3) and completely or partially closed by an end wall (4) at the opposite longitudinal end, and which tubular body (2) on the inner circumferential surface is provided with a cutting means (5) for stripping the jacket (7) of the cable.
8. Stripping tool according to any of the preceding claims, characterised in that it furthermore comprises a second cutting means (18) for cutting the outer conductor (9), the inner conductor (31) and the dielectric material (32) off at predetermined longitudinal positions relative to said pattern of the corrugated outer conductor (9), where said second cutting means (18) is formed as a tubular body comprising a first longitudinal section (21) of the inner circumferential wall of said body, the diameter of which first section (21) corresponds to the outer diameter of said first region (12) of the guide part (10), and where said first longitudinal section (21) is provided with an end face (29) such that this end face (29), during use of the stripping tool, is brought into contact with said abutment surface (13) of the guide part (10), whereby said predetermined longitudinal positions relative to the pattern of the corrugated outer conductor (9) are determined, and where said second cutting means (18) in its interior and coaxially herewith is provided with cutter means (26) comprising two cutting edges (22, 23), the longitudinal distance (d) between which corresponds to the longitudinal distance between the end (B) of the outer conductor (9) and the end of the inner conductor (31) and the insulating material (32), and where said second cutting means (18) is furthermore provided with a coaxially extending guide shaft (19) to be inserted into the hollow inner conductor (31) during use of the stripping tool.
9. A method for stripping a coaxial cable comprising a non-helically corrugated outer conductor (9) and a hollow inner conductor (31) using the stripping tool according to any of the preceding claims, where said method comprises the following steps:
(a) Stripping a predetermined length of said jacket (7) by inserting the end of the cable into the open end (3) of said jacket cutting means (1) to a point where the end of the cable is brought into contact with the cutting edge (6) of the cutting means (5) provided within the jacket cutting means (1), whereafter the jacket cutting means (1) is rotated relative to the cable, the cable being still advanced longitudinally within the jacket cutting means (1), until the end of the cable reaches the end wall (4) of the jacket cutting means (1);
(b) Removal of the jacket cutting means (1) from the end of the cable;
(c) Inserting the end of the cable into that open end of the guide part (10) furthest away from the position-determining tongues (16) to a longitudinal position, where said tongues (16) fit into that valley (17) of the corrugation on the outer conductor (9) which is closest to the end of the jacket (7), thereby obtaining a well-defined longitudinal position of the abutment surface (13) relative to this valley (17),
(d) Inserting the first longitudinal section (21) of the second cutting means (18) over the first region (12) of the guide part (10), and when a point is reached where the inner conductor (31) and the insulating material (32) is brought into contact with the first cutting edge (22) provided on the cutter means (26) rotating said second cutting means (18) relative to the guide part (10) and still advancing said second cutting means (18) longitudinally relative to the guide part (10) until the end face (29) of the second cutting means (18) is brought into contact with the abutment surface (13) provided on the guide part (10);
(e) Finally removing the second cutting means (18) and the guide part (10) from the finished cable.
10. A method according to claim 9, where step (c) is replaced by the following step:
(f) Inserting the end of the cable into that open end of the guide part (10) furthest away from the position-determining tongues (16) to a longitudinal position where said tongues (16) fit into that crest (33) of the corrugation on the outer conductor (9) which is closest to the end of the outer conductor (9), thereby obtaining a well-defined longitudinal position of the abutment surface (13) relative to this crest (33).