Author: claimsbot

1. An epitope of the lipopolysaccharide inner core of a Neisseria meningitidis strain, wherein the epitope selectively reacts with the monoclonal antibody B5 produced by the hybridoma deposited with the accession number IDAC 260900-1.
2. The epitope according to claim 1, wherein the epitope is of the lipopolysaccharide inner core of a galE mutant strain of Neisseria meningitidis H4476 immunotype L3.
3. The epitope according to claim 1, wherein said epitope:
(i) is an epitope of the lipopolysaccharide inner core of a Neisseria meningitidis strain having an immunotype selected from the group consisting of: L1, L3, L7, L8, L9, L10, L11, and L12, but not of the lipopolysaccharide inner core of a Neisseria meningitidis strain having an immunotype selected from the group consisting of: L2, L4, L5, and L6;
(ii) when administered to a recipient subject in an immunogenic composition, generates an antibody in the recipient subject, wherein the antibody is capable of selectively binding to said epitope when said epitope is within the lipopolysaccharide of a strain of Neisseria meningitidis strain having an immunotype selected from the group consisting of: L1, L3, L7, L8, L9, L10, L11, and L12; and
(iii) when in the inner core of the lipopolysaccharide of a Neisseria meningitidis strain, is accessible to an antibody specifically reactive to said epitope.
4. The epitope according to claim 1, wherein said epitope consists essentially of a phosphoethanolamine (PEtn) group linked to position 3, but not to position 6 or 7, of the HepII moiety of the lipopolysaccharide inner core of Neisseria meningitidis immunotype L3, and wherein the epitope is included in a region of the lipopolysaccharide inner core of a strain of Neisseria meningitidis, said inner core region having the formula:
5. The epitope according to claim 4 wherein the Glc and the GlcNAc moieties of the lipopolysaccharide inner core region are in co-operative proximity to the phosphoethanolamine group, whereby co-operative interaction between the Glc and the GlcNAc moieties with the phosphoethanolamine group increases the affinity of an antibody specifically binding to said epitope.
6. The epitope according to claim 5, wherein the antibody specifically binding to said epitope is monoclonal antibody B5 produced by the hybridoma deposited with the accession number IDAC 260900-1.
7. The epitope according to claim 4, wherein the region of the lipopolysaccharide inner core is linked to a-KDO-KDO-Lipid A moiety.
8. The epitope according to claim 4, wherein the Glc is further linked to a moiety, wherein said moiety does not prevent access to the epitope of an antibody specifically reactive to said epitope.
9. The epitope according to claim 4, wherein the region of the lipopolysaccharide inner core is linked to the outer core of a strain of Neisseria meningitidis, or a fragment thereof.
10. The epitope of claim 1, wherein the epitope, when in the lipopolysaccharide inner core of a cell of Neisseria meningitidis, is accessible by an antibody specific to the epitope in the presence and absence of a bacterial capsule.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A combined predistorter and feedforward corrector apparatus suitable for use in a transmitter for improving at least one of power dissipation and linearity in the transmitter, comprising:
a predistorter, for receiving an input signal, and for providing a predistorted signal by performing as much linearization as necessary to predistort the input signal within the predetermined bounds of linearizer efficiency and correction required by the transmitter;
a power amplifier, for receiving the predistorted signal, and for providing an amplified predistorted signal by amplifying the predistorted signal, connected to said predistorter;
a feedforward corrector, for receiving the input signal, and for providing a correction signal by correcting any remaining distortion that the power amplifier produces that the predistorter did not correct; and
a summator, for receiving the amplified predistorted signal and the correction signal, and for providing an output signal by summing the amplified predistorted signal and the correction signal, connected to said feedforward corrector, and connected to said power amplifier.
2. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
an actuator, for receiving the input signal and for providing at least one of a predistorted input signal and a corrected input signal.
3. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
an adjustment block, for receiving an adjustment input signal comprising at least one of the input signal and an input adjusted amplified predistorted signal, and for providing a respective one of an adjusted input signal and an unamplified correction signal respectively, by adjusting at least one of gain, phase, and delay of the adjustment input signal.
4. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
an adaptor, for receiving at least one of the input signal, the output signal, the amplified predistorted signal, and an input adjusted amplified predistorted signal, and for providing an adapted signal which is adapted to a change in the electronics environment to be used by one of an actuator and an adjustment block.
5. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
an error amplifier, for receiving an unamplified error signal including at least one of an unamplified correction signal, an adjusted input signal, and a corrected input signal, and for providing the correction signal by amplifying the unamplified error signal.
6. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
a second summator, for receiving the amplified predistorted signal and an adjusted input signal, and for providing an input adjusted amplified predistorted signal by summing the amplified predistorted signal and the adjusted input signal, connected to said adjustment block, and connected to said power amplifier.
7. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
an upconverter, for receiving an upconverter input signal comprising at least one of the predistorted input signal, an adjusted input signal, and a corrected input signal, and for upconverting the upconverter input signal.
8. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
a downconverter, for receiving a downconverter input signal comprising at least one of the amplified predistorted signal, the output signal, and an input adjusted amplified predistorted signal, and for downconverting the downconverter input signal.
9. The combined predistorter and feedforward corrector apparatus suitable for use in a transmitter as recited in claim 1, further comprising:
a controller, for sensing at least one of the output signal, and the amplified predistorted signal, the input adjusted amplified predistorted signal, and for controlling at least one adaptor, connected to said predistorter, and connected to said feedforward corrector.
10. A method of controlling the apparatus recited in claim 1, the method comprising the acts of:
sensing signals, including at least one of the output signal, and the amplified predistorted signal;
determining if predistorter linearization is sufficient enough to predistort the input signal within the predetermined bounds of linearizer efficiency and correction required by the transmitter
if predistorter linearization is determined to be sufficient enough, then decreasing the amount of feedforward correction in the feedforward corrector; and
if predistorter linearization is determined not to be sufficient enough, then increasing the amount of feedforward correction in the feedforward corrector.
11. The method as recited in claim 10, wherein the act of decreasing the amount of feedforward correction in the feedforward corrector comprises the act of disabling the feedforward corrector.
12. The method as recited in claim 10, wherein the act of increasing the amount of feedforward correction in the feedforward corrector comprises the act of enabling the feedforward corrector.

1. A method of image compression in a digital data processor having a CPU that is coupled to an associated GPU comprising the steps of:
A. transforming, with the GPU, image values from a color representation to a frequency-based representation,
B. with the GPU, re-ordering coefficients comprising the frequency-based representation such that coefficients of like order from multiple sub-blocks of the frequency-based representation of the image are ordered together,
C. transferring the re-ordered coefficients to the CPU, the CPU at least one of storing and transmitting said coefficients.
2. The method of claim 1, comprising using the CPU to compress the re-ordered coefficients.
3. The method of claim 1, comprising using the CPU to transmit the compressed coefficients to a further digital data processor in communications coupling with the CPU.
4. The method of claim 3, wherein the GPU and the CPU are co-housed, and the further digital data processor is remote from said GPU and CPU.
5. The method of claim 1, further comprising
D. with the CPU, compressing the coefficients via a run length encoding-based compression technique.
6. The method of claim 1, wherein step (A) further comprises transforming, with the GPU, the image values from an RGB color space to a YCbCr color space before transforming said image values to the frequency-based representation.
7. The method of claim 1, wherein step (A) further comprises transforming, with the GPU, the image values from the color representation to the frequency-based representation via a Fourier-related transform.
8. The method of claim 1, wherein step (A) further comprises transforming, with the GPU, the image values from the color representation to the frequency-based representation via a discrete cosine transform (DCT).
9. The method of claim 8, wherein step (A) further comprises transforming, with the GPU, the image values from a color representation into a frequency-based representation via a first pass of the DCT transform and a second pass of the DCT transform, wherein the first pass is performed on lines of the image values, and the second pass is performed on columns of the image values.
10. The method of claim 9, wherein step (A) further comprises quantizing the coefficients with the GPU.
11. The method of claim 1, wherein step (B) further comprises re-ordering the coefficients so that coefficients of a first order are followed by coefficients of a second order, which are followed by coefficients of a third order, and so forth.
12. A method of image decompression in a digital data processor having a CPU that is coupled to an associated GPU comprising the steps of:
A. receiving compressed image values in memory associated with the CPU,
B. transferring the compressed image values to the GPU, the compressed image values comprising coefficients of like order from multiple sub-blocks of a frequency-based representation of an image that are ordered together,
C. with the GPU, re-ordering the compressed image values such that coefficients of like sub-blocks of the frequency-based representation of the image are stored together.
13. The method of claim 12, wherein step (B) further includes decompressing, with the CPU, the compressed image values before transferring the image values to the GPU.
14. The method of claim 12, wherein the step (A) comprises receiving compressed quantized image values in a memory associated with the CPU, wherein the quantized image values comprise coefficients having a data size reduced from a first size to a second size.
15. The method of claim 14, further comprising
D. with the GPU, unquantizing the compressed quantized image values such that the data size of the coefficients are expanded from the second size to the first size.
16. The method of claim 12, further comprising
D. with the GPU, transforming the image values from a frequency-based representation to a color space representation.
17. The method of claim 16, wherein step (D) transforms the image values from a frequency-based representation to a YCbCr color space via an inverse Discrete Cosine Transform (DCT).
18. The method of claim 17, wherein step (D) further comprises transforming, with the GPU, the image values from the YCbCr color space to an RGB color space.
19. The method of claim 17 further comprising
E. with the GPU, generating a three-dimensional image (14D) from the RGB color space image values, and storing that image in a memory.
20. In a digital data processing system, the improvement for image compression comprising:
A. a graphics processing unit (GPU) coupled to a central processing unit (CPU),
B. the GPU transforming image values from a color representation to a frequency-based representation and re-ordering coefficients comprising that frequency-based representation such that coefficients of like order from multiple sub-blocks of the frequency-based representation are ordered together,
C. the CPU receiving the re-ordered coefficients from the GPU and at least any of storing and transmitting the re-ordered coefficients.
21. The digital data processing system of claim 20, wherein the CPU compresses the re-ordered coefficients prior to storing andor transmitting said coefficients.
22. The digital data processing system of claim 21, wherein the GPU compresses the re-ordered coefficients via any of a run length encoding-based compression technique and Zlib algorithm.
23. The digital data processing system of claim 20, wherein the GPU transforms the image values from an RGB color space to a YCbCr color space before said GPU transforms the image values to the frequency-based representation.
24. The digital data processing system of claim 23, wherein the GPU transforms the image values from the YCbCr color space to the frequency-based representation via a Fourier-related transform.
25. The digital data processing system of claim 23, wherein the GPU transforms the image values from the YCbCr color space to the frequency-based representation via a discrete cosine transform (DCT).
26. The digital data processing system of claim 25, wherein the GPU applies a quantization factor to said coefficients.
27. The digital data processing system of claim 20, wherein the GPU renders the image values to a texture stored in a buffer associated with the GPU.
28. In a digital data processing system, the improvement for image decompression comprising:
A. a graphics processing unit (GPU) coupled to a central processing unit (CPU),
B. the CPU receiving compressed image values in a memory associated with the CPU,
C. the CPU transferring the compressed image values to the GPU, the compressed image values comprising coefficients of like order from multiple sub-blocks of a frequency-based representation of an image that are ordered together,
D. the GPU re-ordering the compressed image values such that coefficients of like sub-blocks of the frequency-based representation of the image are stored together.
29. The digital data processing system of claim 28, wherein the CPU decompresses the compressed image values before transferring the image values to the GPU.
30. The digital data processing system of claim 28, wherein the CPU receives compressed quantized image values in a memory associated with the CPU, wherein the quantized image values comprise coefficients having a data size reduced from a first size to a second size.
31. The digital data processing system of claim 30, further comprising the GPU unquantizing the compressed quantized image values such that the data size of the coefficients are expanded from the second size to the first size.
32. The digital data processing system of claim 28, further comprising the GPU transforming the image values from a frequency-based representation to a color space representation.
33. The digital data processing system of claim 32, wherein the GPU transforms the image values from a frequency-based representation to a YCbCr color space via an inverse Discrete Cosine Transform (DCT).
34. The digital data processing system of claim 33, wherein the GPU transforms the image values from the YCbCr color space to an RGB color space.
35. The digital data processing system of claim 33, wherein the GPU generates a three-dimensional image (4D) from the RGB color space image values and stores that generated image in a memory.
36. A digital data processing system for remote visualization comprising:
A. a digital data processor having a graphics processing unit (GPU) associated with a central processing unit (CPU)
B. the GPU transforming image values from a color representation to a frequency-based representation and ordering coefficients comprising that frequency-based representation such that coefficients of like order from multiple sub-blocks of the frequency-based representation are ordered together,
C. the CPU receiving the ordered coefficients from the GPU and transmitting image values values comprising said coefficients to a remote digital data processor.
37. The digital data processing system of claim 36, wherein the remote digital data processor comprises a remote GPU associated with a remote CPU that receives the transmitted image values.
38. The digital data processing system of claim 37, wherein the remote CPU transfers the image values to the remote GPU, the remote GPU re-ordering the image values such that coefficients of like sub-blocks of the frequency-based representation are stored together.
39. The digital data processing system of claim 38, wherein the remote GPU transforms the image values from a frequency-based representation to a color space representation.
40. The digital data processing system of claim 39, wherein the remote GPU transforms the image values from a frequency-based representation to a YCbCr color space via an inverse Discrete Cosine Transform (DCT).
41. The digital data processing system of claim 40, wherein the remote GPU transforms the image values from the YCbCr color space to an RGB color space.
42. The digital data processing system of claim 38, wherein the remote GPU renders an image from the color space image values and outputs that rendered image to a display coupled to the remote digital data processor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of controlling power consumption of a backlight in an electronic display, wherein the backlight comprises two or more LED arrays, each corresponding to a respective color channel in an image to be displayed, the method characterized by:
generating separate histograms of transmittance values for two or more of said color channels in said image;
stretching the histograms for said two or more color channels by respective stretching factors to generate a stretched image;
displaying the stretched image on said electronic display; and
separately controlling two or more led arrays in said backlight to reduce a brightness of light emitted by said two or more led arrays in dependence on respective stretching factors applied to the histograms for the corresponding color channels.
2. The method of claim 1 wherein the two or more color channels comprise primary color channels and wherein stretching the histograms for said two or more color channels comprises stretching the histograms for each primary color channel independently.
3. The method of claim 2 wherein the two or more color channels comprises at least one composite color channel and at least one primary color channel and wherein stretching the histograms for said two or more color channels comprises stretching the histogram for said primary color channel in dependence stretching of the histogram for the composite color channel.
4. The method of claim 1 wherein separately controlling two or more LED arrays in said backlight to reduce a brightness of light emitted by said two or more LED arrays in dependence on respective stretching factors for the corresponding color channel comprises reducing a supply current to each LED array proportionally to the stretching of the histogram for the corresponding color channel.
5. A display assembly for an electronic device comprising:
an electronic display;
a backlight for said electronic display including two or more LED arrays;
characterized by:
a control circuit for controlling the electronic display and backlight to reduce power consumption of the backlight, said control circuit configured to:
generate separate histograms of transmittance values for two or more of said color channels in said image;
stretch the histograms for said two or more color channels by respective stretching factors to generate a stretched image;
output the stretched image to said electronic display for display; and
separately control two or more LED arrays in said backlight to reduce a brightness of light emitted by said two or more LED arrays in dependence on respective stretching factors for the corresponding color channel.
6. The display assembly of claim 5 wherein the two or more color channels comprise primary color channels and wherein, to stretch the histograms for said two or more color channels, the control circuit is configured to stretch the histograms for each primary color channel independently.
7. The display assembly of claim 5 wherein the two or more color channels comprises at least one composite color channel and at least one primary color channel and wherein, to stretch the histograms for said two or more color channels, the control circuit is configured to stretch the histogram for said primary color channel in dependence stretching of the histogram for the composite color channel.
8. The display assembly of claim 5 wherein, to separately control two or more LED arrays in said backlight, the control circuit is configured to reduce a supply current to each LED array proportionally to the stretching of the histogram for the corresponding color channel.
9. An electronic device comprising a user input device, a display including a backlight with two or more LED arrays, and a processor configured to receive user input via said user input device and to output information for display on said display, characterized by a control circuit for controlling the electronic display and backlight to reduce power consumption of the backlight, said control circuit configured to:
generate separate histograms of transmittance values for two or more of said color channels in said image;
stretch the histograms for said two or more color channels by respective stretching factors to generate a stretched image;
output the stretched image to said electronic display for display; and
separately control two or more LED arrays in said backlight to reduce a brightness of light emitted by said two or more LED arrays in dependence.
10. The electronic device of claim 9 wherein the two or more color channels comprise primary color channels and wherein, to stretch the histograms for said two or more color channels, the control circuit is configured to stretch the histograms for each primary color channel independently.
11. The electronic device of claim 9 wherein the two or more color channels comprises at least one composite color channel and at least one primary color channel and wherein, to stretch the histograms for said two or more color channels, the control circuit is configured to stretch the histogram for said primary color channel in dependence stretching of the histogram for the composite color channel.
12. The electronic device of claim 9 wherein, to separately control two or more LED arrays in said backlight, the control circuit is configured to reduce a supply current to each LED array proportionally to the stretching of the histogram for the corresponding color channel.