Author: claimsbot

1. An interface adapted for use with an audiometer, comprising:
a digital wireless interface supported by a base unit and a remote unit wherein the base unit receives signals comprising test sound information corresponding to a test sound from the audiometer and provides the signals as digitally encoded test sound information corresponding the test sound to the remote unit via the digital wireless interface.
2. The interface as in claim 1, wherein the digital wireless interface comprises high density coding.
3. The interface as in claim 2, wherein the high density coding comprises minimum shift keying.
4. The interface as in claim 1, further comprising earphones coupled to the remote unit.
5. The interface as in claim 1, further comprising insert earphones coupled to the remote unit.
6. The interface as in claim 1, further comprising a bone conduction transducer coupled to the remote unit.
7. A base unit adapted for receiving signals from an audiometer, comprising:
a receiver for receiving test sound information corresponding to a test sound and transmitting digitally encoded test sound information corresponding to a test sound to a remote unit through a digital wireless interface.
8. The base unit as in claim 7, further comprising a user interface.
9. The base unit as in claim 7, wherein the base unit comprises at least one of an analog base unit and a digital base unit for receiving the test sound information.
10. The base unit as in claim 7, wherein the base unit comprises a computer-processing unit adapted for running a digital audiometer.
11. A remote unit adapted for providing a test sound, the remote unit comprising:
a digital wireless interface for receiving digitally encoded test sound information corresponding to a test sound and outputting a test sound signal to a transducer for providing the test sound.
12. The remote unit as in claim 11, further comprising a response switch configured to communicate actuation of the response switch to a base unit via the digital wireless interface.
13. A method for conducting an audiometric test of a test subject, the method comprising:
receiving test sound information from an audiometer;
digitally encoding the test sound information into digitally encoded test sound information corresponding to a test sound;
transmitting the digitally encoded test sound information corresponding to the test sound using a digital wireless interface;
converting the digitally encoded test sound information into the test sound information; and
providing the test sound information to the test subject as at least one test sound.
14. The method as in claim 13, further comprising calibrating a sound pressure level of the at least one test sound to at least one ear canal of the test subject.
15. The method as in claim 13, further comprising identifying an ear canal of the test subject to which a masking sound is transmitted.
16. The method as in claim 13, further comprising transmitting a masking sound to an ear canal of the test subject.
17. The method as in claim 13, further comprising measuring ambient noise in at least one ear canal of the test subject.
18. The method as in claim 13, further comprising canceling ambient noise in at least one ear canal of the test subject.
19. The method as in claim 13, further comprising sending a response via a response switch from the test subject.
20. A system for conducting an audiometric test, the system comprising:
means for receiving test sound information for the audiometric test;
means for producing digitally encoded test sound information corresponding to a test sound from the test sound information;
means for transmitting the digitally encoded test sound information corresponding to the test sound over a digital wireless interface;
means for receiving the digitally encoded test sound information; and
means for producing test sounds from the digitally encoded test sound information.
21. The system as in claim 20, further comprising means for calibrating a sound pressure level of at least one test sound to at least one ear canal of a test subject.
22. The system as in claim 20, further comprising means for transmitting a masking sound to an ear canal of a test subject.
23. The system as in claim 20, further comprising means for identifying an ear canal of a test subject to which a masking sound is transmitted.
24. The system as in claim 20, further comprising means for measuring ambient noise in at least one ear canal of a test subject.
25. The system as in claim 20, further comprising means for canceling ambient noise in at least one ear canal of a test subject.
26. The system as in claim 20, further comprising means for sending a response from a test subject.
27. The system as in claim 20, further comprising means for generating test sound information.
28. An audiometer adapted for providing input to a remote unit, comprising:
a test sound information generator for generating test sounds and a transceiver for transmitting the test sounds as digitally encoded test sound information corresponding to the test sounds to the remote unit through a digital wireless interface.
29. A method for calibrating an audiometric testing system having a digital wireless interface, the method comprising:
producing a test sound in an ear canal of a test subject, the producing using the digital wireless interface to transmit the test sound as digitally encoded test sound information corresponding to the test sound;
monitoring a corresponding sound pressure level; and
adjusting the audiometric testing system via the digital wireless interface to match the sound pressure level to a predetermined value.
30. An interface for providing an appropriate dynamic range for audiometric testing comprising:
a digital wireless interface supported by a base unit and a remote unit wherein the base unit receives a signal comprising test sound information corresponding a test sound from an audiometer and provides the signal as digitally encoded test sound information corresponding to the test sound to the remote unit via the digital wireless interface, wherein the amplitude of the signal provided via the wireless interface is automatically scaled based on a comparison of an average amplitude of the signal to preset thresholds.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. In a passenger transport aircraft having a passenger cabin therein bounded from below by a cabin floor, a cable channel arrangement arranged adjacent to said cabin floor in said passenger cabin, and power andor data conductor cables received in said cable channel arrangement,
an improvement wherein said cable channel arrangement comprises:
a longitudinal guide element extending longitudinally in said cabin and forming a longitudinal cable channel with at least a respective one of said cables received therein;
a transverse guide element extending transversely in said cabin and forming a transverse cable channel with at least a respective one of said cables received therein; and
a cable branch junction that is joined to and interconnects said longitudinal guide element and said transverse guide element, and that forms a cable passage therein including a longitudinal cable receiving area communicating into said longitudinal cable channel and a transverse cable receiving area communicating into said transverse cable channel, with said at least one respective cable passing through said passage;
wherein each respective one of said guide elements respectively comprises a lower part secured to said cabin floor and an upper part arranged on said lower part to cover said cable channel of said respective guide element.
2. The improvement in the passenger transport aircraft according to claim 1, wherein said longitudinal guide element and said transverse guide element extend perpendicular to each other, and said cable branch junction forms an intersection therebetween.
3. The improvement in the passenger transport aircraft according to claim 1, wherein said lower part of each said guide element is arranged on top of said cabin floor and is secured thereto.
4. The improvement in the passenger transport aircraft according to claim 1, wherein said upper part and said lower part of each said guide element are separate individual components relative to each other, and said upper part is removably secured onto said lower part.
5. The improvement in the passenger transport aircraft according to claim 1, wherein said upper part and said lower part of each said guide element respectively comprise mating snap-fit fasteners that snap-engage each other so as to removably secure said upper part onto said lower part.
6. The improvement in the passenger transport aircraft according to claim 1, wherein:
said lower part of said longitudinal guide element comprises a base, a central web extending upwardly from said base, and two side webs respectively extending from said base parallel to each other on opposite sides of and spaced apart from said central web, forming respective ones of said longitudinal cable channel between said side webs and said central web respectively on each side of said central web; and
said upper part of said longitudinal guide element comprises a downwardly facing catch element that matingly corresponds with said central web of said lower part, and two lateral cover strips that protrude laterally on opposite sides of said catch element so as to cover said longitudinal cover channels and that include elastically flexible free edge rims protruding laterally beyond said side webs of said lower part.
7. The improvement in the passenger transport aircraft according to claim 6, wherein the aircraft further has a seat mounting rail set into or arranged on said cabin floor and a floor covering arranged on said cabin floor, wherein said longitudinal guide element extends along and adjacent to said seat mounting rail with a first one of said cover strips oriented toward said seat mounting rail and a second one of said cover strips oriented toward said floor covering with an edge of said floor covering received between said cabin floor and said free edge rim of said second one of said cover strips.
8. The improvement in the passenger transport aircraft according to claim 1, wherein the aircraft includes side wall trim paneling and a side trim base angle that forms a transition and joint between said cabin floor and said side wall trim paneling, and wherein said longitudinal guide element extends along said side trim base angle and bridges and covers a joint gap between said cabin floor and said side trim base angle.
9. The improvement in the passenger transport aircraft according to claim 1, wherein the aircraft further includes a seat mounting rail set into or arranged on said cabin floor, and further comprising a seat rail cover that comprises a central member with catch elements that engage into said seat mounting rail to hold said seat rail cover thereon, and two lateral cover strips that protrude laterally in opposite directions from said central member and that respectively have elastically flexible free edge rims protruding away from said seat mounting rail and toward said cabin floor.
10. The improvement in the passenger transport aircraft according to claim 9, wherein each said free edge rim of said seat rail cover and an upper surface of said upper part of said longitudinal guide element are respectively configured to join and flushly complement each other.
11. The improvement in the passenger transport aircraft according to claim 9, wherein said longitudinal guide element extends along and next to said seat mounting rail, and one of said lateral cover strips of said seat rail cover extends over and at least partially covers said longitudinal guide element with said free edge rim of said one of said lateral cover strips partially overlapping said upper part of said longitudinal guide element and seated flushly into a recessed step provided in an upper surface of said upper part.
12. The improvement in the passenger transport aircraft according to claim 9, wherein the aircraft further includes at least one of a cable guide channel extending along next to said seat mounting rail and a floor covering provided on said cabin floor with a floor covering edge of said floor covering extending along said seat mounting rail, and wherein one of said lateral cover strips of said seat rail cover extends over and at least partially covers at least one of said cable guide channel and said floor covering edge with said free edge rim of said one of said lateral cover strips extending over and pressing against said floor covering edge.
13. The improvement in the passenger transport aircraft according to claim 9, wherein at least said elastically flexible free edge rims of said seat rail cover and said upper part of said longitudinal guide element are each made of a respective plastic.
14. The improvement in the passenger transport aircraft according to claim 1, further comprising an end cap that is engaged into an open end of said longitudinal cable channel at an end of said longitudinal guide element so as to close said open end and cover said end.
15. The improvement in the passenger transport aircraft according to claim 1, wherein said lower part of said transverse guide element comprises a base plate interconnecting two tapering ramp members with said transverse cable channel therebetween, and said upper part of said transverse guide element comprises a cover plate that covers said transverse cable channel between said two tapering ramp members.
16. The improvement in the passenger transport aircraft according to claim 1, further comprising friction-fit or form-locking connectors provided at an end of said transverse guide element.
17. The improvement in the passenger transport aircraft according to claim 16, wherein said cable branch junction comprises a lower section forming said cable passage receiving said cable therein, and an upper section that covers at least a portion of said lower section, and wherein connector elements are provided on said transverse cable receiving area of said lower section and are engagingly connected with said connectors provided on said transverse guide element.
18. The improvement in the passenger transport aircraft according to claim 17, wherein said aircraft further includes a floor covering arranged on said cabin floor, and wherein said transverse guide element and said transverse cable receiving area of said lower section of said cable branch junction are arranged under and covered by said floor covering.
19. The improvement in the passenger transport aircraft according to claim 17, wherein said lower section includes a stiffened area and mounting elements in said longitudinal cable receiving area, said upper section covers only said longitudinal cable receiving area and not said transverse cable receiving area, and said upper section includes catch elements that engage said stiffened area and said mounting elements.

1. A graphics plotting apparatus which performs a rendering process, comprising:
a logic circuit block;
a memory block having a capacity sufficient to store display data to be displayed wherein the logic circuit block and the memory block are built in the same chip;
an input buffer provided at an input portion of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
an initialization arithmetic operation circuit block for linear interpolation operation arranged adjacent the input buffer; and
a linear interpolation processing circuit block arranged adjacent the initialization arithmetic operation block for linear interpolation operation wherein the linear interpolation processing circuit block performs processing of pixels within a fixed united range which is set independently of a form of a display memory and independently of a page boundary of the display memory.
2. A graphics plotting apparatus which performs a rendering process, comprising:
a logic circuit block;
a memory block having a capacity sufficient to store display data to be displayed wherein the logic circuit block and the memory block are built in the same chip;
an input buffer provided at an input portion of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive; and
a first-in first-out buffer disposed on a receiving side of a bus between circuit blocks which are physically separated from each other, a signal for notification that the first-in first-out buffer will be fully occupied soon being transmitted to a data transmitting side of one of the circuit blacks so that stopping of transfer from the data transmitting side circuit block may be performed from the other data receiving side circuit block.
3. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit, block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer.
4. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a tendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, and wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.
5. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
a register arranged between the memory block and the texture processing circuit block, operation of the register being uncontrollable from the texture processing circuit block wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.
6. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the liner interpolation processing circuit block is arranged adjacent the initialization arithmetic operation block for linear interpolation operation wherein the texture processing circuit block is, arranged adjacent the linear interpolation operation processing circuit block, and wherein the texture processing circuit block has a block size greater than respective block sizes of the initialization arithmetic operation circuit block for linear interpolation operation and the linear interpolation processing circuit block.
7. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic from including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogenous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the linear interpolation processing circuit block is arranged adjacent said initialization arithmetic operation block for linear interpolation operation, wherein the texture processing circuit block is arranged adjacent the linear interpolation operation processing circuit block, and wherein the texture processing circuit block has a block size greater than those of said initialization arithmetic operation circuit block for linear interpolation operation and said linear interpolation processing circuit block.
8. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer wherein the linear interpolation processing circuit block is arranged adjacent said initialization arithmetic operation block for linear interpolation operation, and wherein the initialization arithmetic operation circuit block for linear interpolation operation discriminates through positivenegative discrimination of a linear expression whether or not a noticed point is in an inside of a triangle.
9. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the linear interpolation processing circuit block is arranged adjacent the initialization arithmetic operation block for linear interpolation operation, and wherein the linear interpolation processing circuit block performs processing of pixels within a fixed united range which is set independently of a form of a display memory and independently of a page boundary of the display memory.
10. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data;
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive; and
a first-in first-out buffer disposed on a receiving side of a bus between circuit blocks which are physically separate from each other, a signal for notification that the first-in first-out buffer will be fully occupied soon being transmitted to a data transmitting side of one of the circuit blocks so that stopping of transfer from the data transmitting side circuit block may be performed from the other data receiving side circuit block, wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An igloo-shaped structure for use as a toy or a portable shelter, comprising:
a plurality of first rectangular blocks, each first rectangular block having a defined length and width, and having a rectangular shaped trough and a rim surrounding the trough, the rim having adjacent each corner of the first rectangular blocks a pin for engaging a fastening plate; and
a plurality of second rectangular blocks, each second rectangular block having a defined length and width less than the length and width of the first rectangular blocks, a rectangular trough, and having a rim surrounding the trough, the rim having at adjacent each corner of the second rectangular blocks a pin for engaging a fastening plate;
a plurality of curved trapezoidal top pieces to form a dome atop the igloo-shaped structure, each curved trapezoidal top piece including a 15 trapezoidal shaped trough, with a rim surrounding the trough, the rim having adjacent each corner of the curved trapezoidal top pieces a pin of engaging a fastening plate; and
a plurality of fastening plates, each fastening plate having a substantially square shape and including an aperture in each of four corners of the fastening plate for capturing or engaging a pin on a rectangular block or a curved trapezoidal top piece;
whereby the first and second rectangular pieces and the trapezoidal top pieces join together with the fastening plates to form an igloo-shaped structure.
2. An igloo-shaped structure according to claim 1, additionally comprising:
a plurality of third rectangular blocks, each third rectangular block having a rectangular trough and a defined length and width less than the length and width of the second rectangular block and a rim surrounding the trough, the rim having at adjacent each corner of the third rectangular blocks a pin of engaging a fastening plate.
3. An igloo-shaped structure in accordance with claim 2, additionally comprising a plurality of fourth rectangular blocks, having a substantially square shape, a pin adjacent each corner of the fourth rectangular blocks, and a substantially square shaped trough in the center of the fourth rectangular blocks and a rim surrounding the trough.
4. An igloo-shaped structure in accordance with claim 2, wherein the blocks are made from transparent or translucent plastic.
5. An igloo-shaped structure in accordance with claim 4, wherein the plastic is substantially rigid.
6. An igloo-shaped structure in accordance with claim 5, wherein the plastic is polyethylene, polypropylene, or polystyrene.
7. An igloo-shaped structure in accordance with claim 2, wherein the fastening plates are made of natural or synthetic rubber.
8. An igloo-shaped structure in accordance with claim 1, wherein the blocks are aluminum or fiberglass.
9. An igloo-shaped structure according to claim 3, wherein the trough slopes inwardly from therein to allow the rim of the blocks to curve as they are stacked.
10. An igloo-shaped structure according to claim 1, wherein the trough slopes inwardly from therein to allow the rim of the blocks to curve as they are stacked.
11. An igloo-shaped structure according to claim 9, wherein each of the first through fourth rectangular blocks have a pair of additional outwardly extending pins approximately midway on an upper edge of the rim and a pair of additional pins on a lower edge of the rim, to allow the blocks to be staggered.
12. An igloo-shaped structure according to claim 11, additionally comprising a plurality of blocks approximately half the length of the first through fourth rectangular block to start a row such that it will stagger the row above or below.