Author: claimsbot

1. A semiconductor device comprising:
a semiconductor substrate including an upper surface;
an insulating film formed above the upper surface of the semiconductor substrate, the insulating film including a contact hole penetrating the insulating film to expose the first upper surface, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary portion as a first lower end of the upper portion and a first upper end of the lower portion, the upper portion including a second upper end having a first inner width, the boundary portion including a second inner width being same as the first inner width, and the lower portion including a second lower end having a third inner width being narrower than the second inner width;
a first conductive plug made from polycrystalline silicon and formed in the lower portion of the contact hole so that the exposed upper surface of the semiconductor substrate is in contact with the first conductive plug; and
a second conductive plug formed on the first conductive plug, and the second conductive plug being made from a conductive material which is different from the polycrystalline silicon.
2. The semiconductor device according to claim 1, wherein the first and second conductive plugs have therebetween an interface with a height lower than a height of the boundary portion of the contact hole relative to the upper surface of the semiconductor substrate.
3. The semiconductor device according to claim 1, wherein the second conductive plug is formed into a metal plug provided with a tungsten layer.
4. The semiconductor device according to claim 1, wherein the second conductive plug includes a barrier metal film and a tungsten layer located inside of the barrier metal film.
5. The semiconductor device according to claim 1, wherein the insulating film includes a first inner side wall facing to the upper portion of the contact hole, and the first inner side wall is formed vertically relative to the upper surface of the semiconductor substrate.
6. The semiconductor device according to claim 5, wherein the insulating film includes a second inner side wall facing to the lower portion of the contact hole, and the second inner side wall has a tapered portion relative to the first inner side wall.
7. The semiconductor device according to claim 1, wherein the semiconductor substrate includes an impurity diffusion layer which contact to the first conductive plug.
8. The semiconductor device according to claim 1, further comprising a silicon nitride film between the upper surface and the insulating film.
9. The semiconductor device according to claim 1, further comprising an element isolation insulating film embedded in the upper surface of the semiconductor substrate and a silicon nitride film formed between the element isolation film and the insulating film.
10. A semiconductor device comprising:
a semiconductor substrate including an upper surface;
an insulating film formed above the upper surface of the semiconductor substrate, the insulating film including a contact hole penetrating the insulating film to expose the first upper surface, the contact hole including an upper portion and a lower portion located on the upper portion via a boundary portion as a first lower end of the upper portion and a first upper end of the lower portion, the upper portion including a second upper end having a first inner width, the boundary portion including a second inner width being same as the first inner width, and the lower portion including a second lower end having a third inner width being narrower than the second inner width;
a first conductive material including a first filling property and formed in the lower portion of the contact hole so that the exposed upper surface of the semiconductor substrate is contact to the first conductive plug; and
a second conductive material including a second filling property being worse than the first filling property of the first conductive plug and formed on the first conductive plug.
11. The semiconductor device according to claim 10, wherein the first conductive material includes polycrystalline silicon.
12. The semiconductor device according to claim 11, wherein the second conductive material includes a metal layer.
13. The semiconductor device according to claim 12, wherein the second conductive material includes a tungsten layer.
14. A method of fabricating a semiconductor device, comprising:
forming an insulating film on an upper surface of a semiconductor substrate;
forming a contact hole in the insulating film to expose the upper surface so that the contact hole includes an upper portion, a lower portion and a boundary portion located between the upper and the lower portions, the upper portion has a first inner width, the boundary portion has a second inner width which is same as the first inner width of the upper portion, the lower portion has a third inner width which is smaller than the second inner width of the boundary portion;
forming a first conductive plug from the exposed upper surface of the semiconductor substrate to a first level which is lower than a second level of the boundary portion relative to the upper surface of the semiconductor substrate; and
forming a second conductive plug which is different from the first conductive plug on the first conductive plug.
15. The method according to claim 14, wherein the contact hole formed by a reactive ion etching (RIE) using an oxide gas and a fluorocarbon gas.
16. The method according to claim 15, wherein the contact hole forming step includes a change step which changes a condition of a flux of the oxide gas and the fluorocarbon gas.
17. The method according to claim 14, wherein the second plug forming step includes a first step of forming a barrier film and a second step of forming a metal film.
18. The method according to claim 14, further comprising a step of forming an impurity diffusion layer, which contact to the first conductive plug, in the upper surface of the semiconductor substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for enhancing the deposit resistance of lubricating oil composition used under sustained high load conditions comprising adding to a Group II base stock oil a combination of additives comprising a minor amount of detergent comprising: i) a low TBN calcium alkyl salicylate a low TBN calcium phenate or combinations thereof at from 2.2 to 6.3 vol. % and optional overbased calcium phenate at from 0.3 to 0.5 vol. %, ii) at least two of the three of a phenolic antioxidant, a functionalized glycerine derivative with a grafted hindered phenolic moiety and a hindered phenolic containing a thioether group, wherein the phenolic antioxidant is at from about 0.75 to 2.0 vol. %, the functionalized glycerine derivative with a grafted hindered phenolic moiety is at from 0.50 to 3.0 vol. % and the hinder phenolic containing a thioether group is at from about 0.5 to 3 mass % active ingredient based on the weight of the lubricating oil composition, and iii) an organomolybdenum complex comprising molybdenum dithiocarbamate present in an amount sufficient to provide about 25 wppm to about 2000 wppm elemental molybdenum.
2. The method of claim 1 wherein the base stock oil has a kinematic viscosity at 100\xb0 C. of about 5 to about 20 mm2s.
3. The method of claim 1 wherein the base stock oil has a kinematic viscosity at 100\xb0 C. of about 5 to about 16 mm2s.
4. The method of claim 1 wherein the base stock oil has a kinematic viscosity at 100\xb0 C. of about 9 to about 13 mm2s.
5. The method of claim 1, 2, 3 or 4 wherein the low TBN calcium alkyl salicylate and low TBN calcium phenate detergent has a TBN of about 114 mg KOHg or less and the optional overbased calcium phenate detergent has a TBN of about 250 mg KOHg or more.
6. The method of claim 1 wherein the organo molybdenum complex is present in an amount sufficient to provide about 50 wppm to about 500 wppm elemental molybdenum.
7. The method of claim 1, 2, 3 or 4 wherein the lubricating oil composition further includes about 0.5 vol. % of neutral calcium sulphonate detergent.
8. The method of claim 1, 2, 3 or 4 wherein the lubricating oil composition additionally contains one or more other additives comprising antioxidants, viscosity index improvers, pour point depressants, antiwearextreme pressure additives, antifoamants, dyes, metal deactivators, additional detergents, dispersants.
9. The method of claim 1, 2, 3 or 4 wherein the lubricating oil composition is a stationary gas engine oil, stationary diesel engine oil, locomotive diesel engine oil, marine diesel engine oil.
10. The method of claim 8 wherein the one or more other additives are ashless additives.

1. A nonvolatile programmable logic switch comprising:
a memory cell; and
a pass transistor,
the memory cell including:
a nonvolatile first memory element including a first terminal connected to a first wiring line, and a second terminal;
a nonvolatile second memory element including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory element;
a first transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and
a second transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other of the source and the drain is connected to a gate of the pass transistor, and a gate is connected to a fifth wiring line.
2. The logic switch according to claim 1, wherein one of the first memory element and the second memory element is in a write state, and the other is in a no-write state.
3. The logic switch according to claim 1, further comprising a control circuit that controls voltages applied to the first to the fifth wiring lines.
4. The logic switch according to claim 1, wherein:
the first and second memory elements comprise first and second memory transistors respectively,
the first terminal of the first memory element is a gate of the first memory transistor, and the second terminal is one of a source and a drain of the first memory transistor, and
the third terminal of the second memory element is a gate of the second memory transistor, and the fourth terminal is one of a source and a drain of the second memory transistor.
5. The logic switch according to claim 4, further comprising a control circuit that controls voltages applied to the first to fifth wiring lines.
6. The logic switch according to claim 1, wherein the first memory element and the second memory element comprise a pn junction respectively.
7. A nonvolatile programmable logic switch comprising:
a first memory cell and a second memory cell; and
a first pass transistor and a second pass transistor corresponding to the first memory cell and the second memory cell respectively,
the first memory cell including:
a nonvolatile first memory element including a first terminal connected to a first wiring line, and a second terminal;
a nonvolatile second memory element including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory element;
a first transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other is connected to a third wiring line, and a gate is connected to a fourth wiring line; and
a second transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other is connected to a gate of the first pass transistor, and a gate is connected to a fifth wiring line,
the second memory cell including:
a nonvolatile third memory element including a fifth terminal connected to a sixth wiring line, and a sixth terminal;
a nonvolatile fourth memory element including a seventh terminal connected to a seventh wiring line, and an eighth terminal connected to the sixth terminal of the third memory element;
a third transistor, of which one of a source and a drain is connected to the sixth terminal and the eighth terminal, the other is connected to the third wiring line, and a gate is connected to an eighth wiring line; and
a fourth transistor, of which one of a source and a drain is connected to the sixth terminal and the eighth terminal, the other is connected to a gate of the second pass transistor, and a gate is connected to a ninth wiring line.
8. The logic switch according to claim 7, wherein:
one of the first memory element and the second memory element is in a write state, and the other is in a no-write state, and
one of the third memory element and the fourth memory element is in a write state, and the other is in a no-write state.
9. The logic switch according to claim 7, further comprising a control circuit that controls voltages applied to the first to the ninth wiring lines.
10. The logic switch according to claim 7, wherein:
the first to fourth memory elements comprise first to fourth memory transistors respectively;
the first terminal of the first memory element is a gate of the first memory transistor, and the second terminal is one of a source and a drain of the first memory transistor;
the third terminal of the second memory element is a gate of the second memory transistor, and the fourth terminal is one of a source and a drain of the second memory transistor;
the fifth terminal of the third memory element is a gate of the third memory transistor, and the sixth terminal is one of a source and a drain of the third memory transistor; and
the seventh terminal of the fourth memory element is a gate of the fourth memory transistor, and the eighth terminal is one of a source and a drain of the fourth memory transistor.
11. The logic switch according to claim 10, further comprising a control circuit that controls voltages applied to the first to ninth wiring lines.
12. The logic switch according to claim 7, wherein the first to fourth memory elements comprise a pn junction respectively.
13. A nonvolatile programmable logic switch comprising:
first to fourth memory cells; and
first and second pass transistors;
the first memory cell including:
a nonvolatile first memory element including a first terminal connected to a first wiring line, and a second terminal;
a nonvolatile second memory element including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory element;
a first transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other is connected to a third wiring line, and a gate is connected to a fourth wiring line; and
a second transistor, of which one of a source and a drain is connected to the second terminal and the fourth terminal, the other is connected to a gate of the first pass transistor, and a gate is connected to a fifth wiring line,
the second memory cell including:
a nonvolatile third memory element including a fifth terminal connected to a sixth wiring line, and a sixth terminal;
a nonvolatile fourth memory element including a seventh terminal connected to a seventh wiring line, and an eighth terminal connected to the sixth terminal of the third memory element;
a third transistor, of which one of a source and a drain is connected to the sixth terminal and the eighth terminal, the other is connected to the third wiring line, and a gate is connected to an eighth wiring line; and
a fourth transistor, of which one of a source and a drain is connected to the sixth terminal and the eighth terminal, the other is connected to a gate of the second pass transistor, and a gate is connected to a ninth wiring line,
the third memory cell including:
a nonvolatile fifth memory element including a ninth terminal connected to the first wiring line, and a tenth terminal;
a nonvolatile sixth memory element including an eleventh terminal connected to the second wiring line, and a twelfth terminal connected to the tenth terminal of the fifth memory element;
a fifth transistor, of which one of a source and a drain is connected to the tenth terminal and the twelfth terminal, the other is connected to a tenth wiring line, and a gate is connected to the fourth wiring line; and
a sixth transistor, of which one of a source and a drain is connected to the tenth terminal and the twelfth terminal, the other is connected to the gate of the first pass transistor, and a gate is connected to an eleventh wiring line,
the fourth memory cell including:
a nonvolatile seventh memory element including a thirteenth terminal connected to the sixth wiring line, and a fourteenth terminal;
a nonvolatile eighth memory element including a fifteenth terminal connected to the seventh wiring line, and a sixteenth terminal connected to the fourteenth terminal of the seventh memory element;
a seventh transistor, of which one of a source and a drain is connected to the fourteenth terminal and the sixteenth terminal, the other is connected to the tenth wiring line, and a gate is connected to the eighth wiring line; and
an eighth transistor, of which one of a source and a drain is connected to the fourteenth terminal and the sixteenth terminal, the other is connected to the gate of the second pass transistor, and a gate is connected to a twelfth wiring line.
14. The logic switch according to claim 13, wherein:
one of the first memory element and the second memory element is in a write state, and the other is in a no-write state;
one of the third memory element and the fourth memory element is in a write state, and the other is in a no-write state;
one of the fifth memory element and the sixth memory element is in a write state, and the other is in a no-write state; and
one of the seventh memory element and the eighth memory element is in a write state, and the other is in a no-write state.
15. The logic switch according to claim 13, further comprising a control circuit that controls voltages applied to the first to twelfth wiring lines.
16. The logic switch according to claim 13, wherein:
the first to eighth memory elements comprise first to eighth memory transistors respectively;
the first terminal of the first memory element is a gate of the first memory transistor, and the second terminal is one of a source and a drain of the first memory transistor;
the third terminal of the second memory element is gate of the second memory transistor, and the fourth terminal is one of a source and a drain of the second memory transistor;
the fifth terminal of the third memory element is a gate of the third memory transistor, and the sixth terminal is one of a source and a drain of the third memory transistor;
the seventh terminal of the fourth memory element is a gate of the fourth memory transistor, and the eighth terminal is one of a source and a drain of the fourth memory transistor;
the ninth terminal of the of the fifth memory element is a gate of the fifth memory transistor, and the tenth terminal is one of a source and a drain of the fifth memory transistor;
the eleventh terminal of the sixth memory element is a gate of the sixth memory transistor, and the twelfth terminal is one of a source and a drain of the sixth memory transistor;
the thirteenth terminal of the seventh memory element is a gate of the seventh memory transistor, and the fourteenth terminal is one of a source and a drain of the seventh memory transistor; and
the fifteenth terminal of the eighth memory element is a gate of the eighth memory transistor, and the sixteenth terminal is one of a source and a drain of the eighth memory transistor.
17. The logic switch according to claim 16, further comprising a control circuit that controls voltages applied to the first to twelfth wiring lines.
18. The logic switch according to claim 13, wherein the first to eighth memory elements comprise a on junction respectively.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A cable drawn snubbing apparatus, comprising:
a first track having an upper end and a lower end;
a second track in parallel spaced relation to the first track, the second track having an upper end and a lower end;
a carriage extending between and engaging the first track and the second track;
pipe engaging slips carried by the carriage;
upper cables extending from the carriage to the upper end of the first track and the upper end of the second track;
lower cables extending from the carriage to the lower end of the first track and the lower end of the second track;
upper drive means for exerting a force upon the upper cables to pull the carriage toward the upper end of the first track and the upper end of the second track; and
lower drive means for exerting a force upon the lower cables to pull the carriage toward the lower end of the first track and the lower end of the second track.
2. The cable drawn snubbing apparatus as defined in claim 1, wherein the upper drive means includes two upper winches coupled by a timing belt to operate synchronously.
3. The cable drawn snubbing apparatus as defined in claim 1, wherein the lower drive means includes two lower winches coupled by a timing belt to operate synchronously.
4. The cable drawn snubbing apparatus as defined in claim 1, wherein the first track and the second track are rigid.
5. The cable drawn snubbing apparatus as defined in claim 1, wherein the first track and the second track are flexible cables placed in tension.
6. A winch and cable driven pipe snubbing apparatus, comprising:
a stationary body adapted to be affixed onto a well head, the stationary body having at least one pair of spaced apart rotatably mounted pulleys;
a first set of slips on the stationary body;
a travelling body disposed above the stationary body, the travelling body having at least one pair of spaced apart rotatably mounted pulleys;
means for moving the travelling body vertically upward and away from the stationary body;
at least one winch mounted to one of the stationary body or the travelling body; and
cable extending from the at least one winch around one pulley of each of the at least one pairs of pulleys mounted on the stationary body and around one pulley of each of the at least one pairs of pulleys mounted on the travelling body, such that when the at least one winch draws in cable the travelling body is pulled vertically downward toward the stationary body, thereby forcing pipe into the well head.
7. The winch and cable driven pipe snubbing apparatus as defined in claim 6, wherein the stationary body and the travelling body come in physical contact, with impact absorbing stops being provided to dampen such physical contact.
8. The winch and cable driven pipe snubbing apparatus as defined in claim 6, wherein more than one pair of pulleys is provided on each of the stationary body and the travelling body in order to increase the mechanical advantage.
9. The winch and cable driven pipe snubbing apparatus as defined in claim 6, wherein a pair of winches are provided in spaced relation.
10. The winch and cable driven pipe snubbing apparatus as defined in claim 6, wherein a timing chain extends between the pair of winches and serves to coordinate the operation of the pair of winches.
11. The winch and cable driven pipe snubbing apparatus as defined in claim 6, wherein at least one secondary winch is positioned on the travelling body and serves as means for moving the travelling body vertically upward and away from the stationary body when cables are extended from the at least one secondary winch to a rig.
12. A winch and cable driven pipe snubbing apparatus, comprising:
a stationary body adapted to be affixed onto a well head, the stationary body having more than one pair of spaced apart rotatably mounted pulleys;
a first set of slips on the stationary body;
a travelling body disposed above the stationary body, the travelling body having more than one pair of spaced apart rotatably mounted pulleys;
a primary pair of winches mounted in spaced apart relation to the stationary body;
cable extending from each winch of the primary pair of winches around one pulley of each of the more than one pair of pulleys mounted on the stationary body and around one pulley of each of the more than one pair of pulleys mounted on the travelling body;
a timing chain extending between the primary pair of winches to coordinate the operation of the primary pair of winches so that they draw in cable in unison to pull the travelling body vertically downward toward the stationary body, thereby forcing pipe into the well head;
impact absorbing stops being provided to dampen physical contact when the travelling body comes in physical contact with the stationary body; and
a secondary pair of winches positioned on the travelling body and serving as means for moving the travelling body vertically upward and away from the stationary body by means of cables extended from the each of the secondary pair of winches to a rig.