Author: claimsbot

1. A pseudo synchronous random access ram (SRAM) with common pad for address pin and data pin, the pseudo SRAM comprising:
an address input unit for receiving an address through a pin and outputting the received address as an internal address;
a transition detecting unit for detecting a transition of the internal address;
a word line (WL) driving signal generating unit for generating a WL driving signal; and
a control signal generating unit, in response to a pin select signal indicating whether a signal input through the pin is an address signal or a data signal, for generating a first control signal for controlling the address input unit to output only an valid address as the internal address, and a second control signal for controlling the WL driving signal generating unit,
wherein the WL driving signal generating unit is configured for generating the WL driving signal in response to an output signal of the transition detecting unit and the second control signal.
2. The pseudo SRAM as recited in claim 1, wherein the first control signal includes an active control signal for activating the address input unit, and an output control signal for outputting only the valid address as the internal address.
3. The pseudo SRAM as recited in claim 2, wherein the control signal generating unit includes:
a first control signal generator for receiving the pin select signal to generate the active control signal and the output control signal; and
a second control signal generator for receiving the active control signal to generate the second control signal.
4. The pseudo SRAM as recited in claim 3, wherein the second control signal generator delays the active control signal by an internal delay time given until the address is outputted as the output signal of the transition detecting unit, and generating the second control signal.
5. The pseudo SRAM as recited in claim 2, wherein the address input unit includes:
an address buffer for receiving the address in response to the active control signal; and
a transfer gate for transferring an output signal of the address buffer as the internal address in response to the output control signal.
6. The pseudo SRAM as recited in claim 5, wherein the first control signal generator includes:
an active control signal generator for delaying the pin select signal by a predetermined time to output the active control signal; and
an output control signal generator for delaying the pin select signal by an internal delay time until the address is outputted as the output signal of the address buffer, and outputting the output control signal.
7. The pseudo SRAM as recited in claim 6, wherein the output control signal generator includes:
a first inverter for inverting the pin select signal;
a first delay unit for delaying an output signal of the first inverter;
a first NAND gate configured to receive an output signal of the first delay unit and the output signal of the first inverter; and
a second inverter for inverting an output signal of the first NAND gate to output the active control signal.
8. The pseudo SRAM as recited in claim 7, wherein the active control signal generator includes:
a second delay unit for delaying the pin select signal;
a second NAND gate configured to receive an output signal of the second delay unit and the pin select signal; and
a third inverter for inverting an output signal of the second NAND gate to output the active control signal.
9. The pseudo SRAM as recited in claim 8, wherein the first delay unit has a delay time corresponding to an internal delay until the address is transferred as the output signal of the address buffer.
10. The pseudo SRAM as recited in claim 9, wherein the address buffer includes:
a first PMOS transistor having a gate receiving the active control signal, and a source connected to a first voltage;
a second PMOS transistor having a gate receiving the address, and a drain-source path between a drain of the first PMOS transistor and an output node;
a first NMOS transistor having a gate receiving the address, and a drain-source path between the output node and a second voltage; and
a second NMOS transistor having a gate receiving the active control signal, and a drain-source path between the output node and the second voltage, such that a voltage applied on the output node is outputted as the output signal.
11. The pseudo SRAM as recited in claim 2, wherein the transition detecting unit includes:
a latch for latching the internal address;
a first rising edge detector for detecting a rising edge of an output signal of the latch;
a second rising edge detector for detecting a rising edge of the internal address; and
an output unit for logically combining output signals of the first and second rising edge detectors to output an address transition detecting signal.
12. The pseudo SRAM as recited in claim 11, wherein the first and second rising edge detectors activate the output signal to a logic low level when a rising edge of an input signal is detected.
13. The pseudo SRAM as recited in claim 12, wherein the output unit includes:
a first NAND gate configured to receive the output signals of the first and second rising edge detectors; and
a first inverter for inverting an output signal of the first NAND gate to output the address transition detecting signal.
14. The pseudo SRAM as recited in claim 13, wherein the address input unit includes:
an address buffer for receiving the address in response to the active control signal; and
a transfer gate for transferring an output signal of the address buffer as the internal address in response to the output control signal.
15. The pseudo SRAM as recited in claim 14, wherein the first control signal generator includes:
an active control signal generator for delaying the pin select signal by a predetermined time to output the active control signal; and
an output control signal generator for delaying the pin select signal by an internal delay time until the address is outputted as the output signal of the address buffer, and outputting the output control signal.
16. The pseudo SRAM as recited in claim 15, wherein the output control signal generator includes:
a first inverter for inverting the pin select signal;
a first delay unit for delaying an output signal of the first inverter;
a first NAND gate configured to receive an output signal of the first delay unit and the output signal of the first inverter; and
a second inverter for inverting an output signal of the first NAND gate to output the active control signal.
17. The pseudo SRAM as recited in claim 16, wherein the active control signal generator includes:
a second delay unit for delaying the pin select signal;
a second NAND gate configured to receive an output signal of the second delay unit and the pin select signal; and
a third inverter for inverting an output signal of the second NAND gate to output the active control signal.
18. The pseudo SRAM as recited in claim 17, wherein the first delay unit has a delay time corresponding to an internal delay until the address is transferred as the output signal of the address buffer.
19. The pseudo SRAM as recited in claim 18, wherein the address buffer includes:
a first PMOS transistor having a gate receiving the active control signal, and a source connected to a first voltage;
a second PMOS transistor having a gate receiving the address, and a drain-source path between a drain of the first PMOS transistor and an output node;
a first NMOS transistor having a gate receiving the address, and a drain-source path between the output node and a second voltage; and
a second NMOS transistor having a gate receiving the active control signal, and a drain-source path between the output node and the second voltage, such that a voltage applied on the output node is outputted as the output signal.
20. The pseudo SRAM as recited in claim 2, wherein the WL driving signal generating unit includes:
a signal generator for outputting a signal in response to the second control signal and an output signal of the transition detecting unit;
an output pulse generator for generating a WL driving signal in a pulse form in response to an output signal of the signal generator; and
a standby unit for setting an output node of the signal generator to a standby state in response to the WL driving signal.
21. The pseudo SRAM as recited in claim 20, wherein the address input unit includes:
an address buffer for receiving the address in response to the active control signal; and
a transfer gate for transferring an output signal of the address buffer as the internal address in response to the output control signal.
22. The pseudo SRAM as recited in claim 21, wherein the first control signal generator includes:
an active control signal generator for delaying the pin select signal by a predetermined time to output the active control signal; and
an output control signal generator for delaying the pin select signal by an internal delay time until the address is outputted as the output signal of the address buffer, and outputting the output control signal.
23. The pseudo SRAM as recited in claim 22, wherein the signal generator includes:
a first inverter for inverting the pin select signal;
an AND gate configured to receive an output signal of the first inverter and the chip select signal;
a second inverter for inverting an output signal of the AND gate;
a third inverter for inverting the address transition detecting signal;
a falling edge detector for detecting a falling edge of the second control signal;
a first PMOS transistor having a gate receiving an output signal of the second inverter, and a source-drain path between a first voltage and an output node;
a first NMOS transistor having a gate receiving an output signal of the second inverter and a drain connected to the output node;
a second NMOS transistor having a gate receiving an output signal of the third inverter, a drain connected to a source of the first NMOS transistor, and a source connected to the second voltage; and
a third NMOS transistor having a gate receiving an output signal of the falling edge detector, and a drain-source path between the output node and the second voltage, such that a voltage applied on the output node is outputted as the output signal.
24. The pseudo SRAM as recited in claim 23, wherein the output unit includes:
a latch for latching the output signal of the signal generator;
a rising edge detector for detecting a rising edge of the output signal of the latch; and
a fourth inverter for inverting an output signal of the rising edge detector to output the WL driving signal.
25. The pseudo SRAM as recited in claim 24, wherein the standby unit includes:
a fifth inverter for inverting the WL driving signal; and
a second PMOS transistor having a gate receiving an output signal of the fifth inverter, and a source-drain path between the first voltage and the output node.
26. The pseudo SRAM as recited in claim 25, wherein the output control signal generator includes:
a first inverter for inverting the pin select signal;
a first delay unit for delaying an output signal of the first inverter;
a first NAND gate configured to receive an output signal of the first delay unit and the output signal of the first inverter; and
a second inverter for inverting an output signal of the first NAND gate to output the active control signal.
27. The pseudo SRAM as recited in claim 26, wherein the active control signal generator includes:
a second delay unit for delaying the pin select signal;
a second NAND gate configured to receive an output signal of the second delay unit and the pin select signal; and
a third inverter for inverting an output signal of the second NAND gate to output the active control signal.
28. The pseudo SRAM as recited in claim 27, wherein the first delay unit has a delay time corresponding to an internal delay until the address is transferred as the output signal of the address buffer.
29. A method for driving a pseudo SRAM with common pad for address pin and data pin, the method comprising the steps of:
activating a pin select signal and applying an address together with the activated pin select signal;
outputting the address as an internal address in response to an output control signal generated by delaying the pin select signal during an internal delay time of the address;
detecting a transition of the internal address to generate an address transition detecting signal;
generating a control signal by delaying the pin select signal for an internal delay time given until the address is outputted as the address transition detecting signal; and
generating a word line driving signal in response to the address transition detecting signal and the control signal activated together.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of providing routes through heterogeneous subsystems in an optical network, the method comprising:
generating, using a processing device, a reachability matrix based on subnetwork information associated with the heterogeneous subsystems, the reachability matrix comprising a list of reachable paths in the subnetwork information, the heterogeneous subsystems being associated with different vendors;
generating, using the processing device, a topology associated with the optical network using the reachability matrix;
determining, using the processing device, a shortest path through the optical network using the reachability matrix and a cost model graph; and
displaying, using a graphical user interface, heterogeneous subsystems associated with the shortest path, regeneration locations associated with the shortest path, wavelengths associated with the shortest path, the topology, and the shortest path.
2. The method of claim 1, wherein generating the reachability matrix further comprises:
obtaining network topology information G(V,E) representing the optical network, V representing nodes associated with the optical network, E representing links associated with the optical network, the optical network comprising a plurality of subnetwork types;
determining a plurality of shortest paths p1, . . . pk linking a node pair (u,v), u representing a first node associated with the optical network, v representing a second node associated with the optical network, u and v being elements of V, k representing a parameter greater than 1;
determining whether the plurality of shortest paths p1, . . . pk are reachable, the shortest paths that are reachable being the reachable paths; and
displaying the reachable paths.
3. The method of claim 2, further comprising modifying k such that the reachability matrix remains the same.
4. The method of claim 1, further comprising generating the reachability matrix using a shortest weight path based on the cost model graph.
5. The method of claim 1, further comprising generating the reachability matrix using only at least one longest reachable path.
6. The method of claim 1, further comprising:
displaying optimized routes and link capacity utilization; and
supporting supporting multiple users simultaneously using the graphical user interface, the graphical user interface comprising a menu, control panel, map panel, and information panel.
7. A computer-readable device storing instructions, that when executed by a processing device, cause the processing device to provide routes through heterogeneous subsystems in an optical network by performing operations comprising:
generating a reachability matrix based on subnetwork information associated with the heterogeneous subsystems, the reachability matrix comprising a list of reachable paths in the subnetwork information, the heterogeneous subsystems being associated with different vendors;
generating a topology associated with the optical network using the reachability matrix;
determining a shortest path through the optical network using the reachability matrix and a cost model graph; and
providing, using a graphical user interface, heterogeneous subsystems associated with the shortest path, regeneration locations associated with the shortest path, wavelengths associated with the shortest path, the topology, and the shortest path.
8. The computer-readable device of claims 7, wherein the operations further comprise:
obtaining network topology information G(V,E) representing the optical network, V representing nodes associated with the optical network, E representing links associated with the optical network, the optical network comprising a plurality of subnetwork types;
determining, using a vendor planning tool, a plurality of shortest paths p1, . . . pk linking a node pair (u,v), u representing a first node associated with the optical network, v representing a second node associated with the optical network, u and v being elements of V, k representing a parameter greater than 1; and
determining whether the plurality of shortest paths p1, . . . pk are reachable, the shortest paths that are reachable being the reachable paths.
9. The computer-readable device of claim 8, wherein the operations further comprise modifying k such that the reachability matrix remains the same.
10. The computer-readable device of claim 7, wherein the operations further comprise generating the reachability matrix using a longest reachable path.
11. The computer-readable device of claim 7, wherein the operations further comprise generating the reachability matrix using a shortest weight path based on the cost model graph.
12. An apparatus to provide routes through heterogeneous subsystems in an optical network comprising:
a processing device;
a storage device to store instructions that, when executed by the processing device, causes the processing device to perform operations comprising:
generating a reachability matrix based on subnetwork information associated with the heterogeneous subsystems, the reachability matrix comprising a list of reachable paths in the subnetwork information, the heterogeneous subsystems being associated with different vendors,
generating a topology associated with the optical network using the reachability matrix;
determining a shortest path through the optical network using the reachability matrix and a cost model graph; and

a graphical user interface, the graphical user interface displaying heterogeneous subsystems associated with the shortest path, regeneration locations associated with the shortest path, wavelengths associated with the shortest path, the topology, and the shortest path.
13. The apparatus of claim 12, wherein the subnetwork information further comprises latitude and longitude information associated with nodes in the optical network.
14. The apparatus of claim 12, wherein the subnetwork information further comprises underlying fiber span information, capacity information, and available wavelength information associated with links in the optical network.
15. The apparatus of claim 12, wherein the subnetwork information represents existing circuits in the optical network.
16. The apparatus of claim 12, wherein the subnetwork information further comprises a section report, the section report comprising system type, node identification, effective date, terminate date, and project identification associated with a dense wavelength division multiplexer section in the subnetwork.
17. The apparatus of claim 12, wherein the operations further comprise:
generating the reachability matrix by obtaining network topology information, G(V,E) representing the optical network, V representing nodes associated with the optical network, E representing links associated with the optical network, the optical network comprising a plurality of subnetwork types;
determining, using a vendor planning tool, a plurality of shortest paths p1, . . . pk linking a node pair (u,v), u representing a first node associated with the optical network, v representing a second node associated with the optical network, u and v being elements of V, k representing a parameter greater than 1; and
determining whether the plurality of shortest paths p1, . . . pk are reachable, the shortest paths that are reachable being the reachable paths.
18. The apparatus of claim 12, wherein the operations further comprise generating the reachability matrix using at least one longest reachable path.
19. The apparatus of claim 12, wherein the operations further comprise generating the reachability matrix using a shortest weight path based on the cost model graph.
20. The apparatus of claim 12, wherein the graphical user interface displays optimized routes and link capacity utilization, the graphical user interface supporting multiple users.

1. A kayak comprising:
a single hull extending longitudinally between a bow and a stern and having a longitudinal axis extending from bow to stern, wherein the hull has a curved or rounded bottom defining a lower most hull portion along the longitudinal axis and wherein the hull includes a port portion and a starboard portion;
a first keel protruding from the port portion of the hull, the first keel positioned between the bow and the stern and sized and positioned to at least partially receive a heel andor a foot of a paddler, the first keel having an axis which is transverse to the longitudinal axis of the hull and is essentially symmetrical on said transverse axis and the first keel being positioned at the lower most hull portion adjacent to the longitudinal axis; and
a second keel protruding from the starboard portion of the hull and essentially parallel to the first keel, the second keel sized to at least partially receive a heel andor a foot of the paddler, the second keel having an axis which is transverse to the longitudinal axis of the hull and is essentially symmetrical on said transverse axis and the second keel being positioned at the lower most hull portion at the longitudinal axis.
2. The kayak of claim 1, further comprising a deck extending from the hull, the deck and the hull together defining an interior volume of the kayak.
3. The kayak of claim 2, further comprising at least one cockpit defined in the deck.
4. The kayak of claim 1, further comprising at least one footrest positioned in each of the first keel and the second keel.
5. The kayak of claim 4, wherein the at least one footrest is repositionable within each of the first keel and the second keel.
6. The kayak of claim 1, further comprising a seat positioned aft of at least a portion of the first and second keels.
7. The kayak of claim 6, wherein the seat is repositionable relative to the first and second keels.
8. The kayak of claim 2, further comprising two or more seats, wherein each of the first and second keels is positioned to simultaneously receive a heel andor foot of a paddler seated in each seat.
9. The kayak of claim 1, further comprising:
a first seat positioned aft of at least a portion of the first and second keels;
a third keel protruding from the port portion of the hull, the third keel positioned aft of the first keel and sized to at least partially receive a heel andor a foot of the paddler;
a fourth keel protruding from the starboard portion of the hull and parallel to the third keel, the fourth keel sized to at least partially receive a heel andor a foot of the paddler;
and a second seat positioned aft of at least a portion of the third and fourth keels.
10. The kayak of claim 1, wherein a length of the first keel and a length the second keel are each less than a length of the hull and a width of the first keel combined with a width of the second keel is less than a width of the hull.
11. The kayak of claim 1, wherein the hull further comprises a hull beam profile, the first keel further comprises a first keel beam profile, and the second keel further comprises a second keel beam profile.
12. The kayak of claim 11, wherein the hull beam profile is different than the first keel beam profile and the second keel beam profile.
13. The kayak of claim 12, wherein the first keel beam profile and the second keel beam profile are essentially the same.
14. The kayak of claim 1, wherein the first keel and the second keel extend away from the hull into a body of water when the kayak is deployed in the body of water.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A limb support system, comprising:
at least one joint configured to rotate about at least two axes that are orthogonal to each other, the at least one joint, comprising:
a first electromagnet and a biasing device positioned generally opposite to each other with at least one first locking member positioned in between the first electromagnet and the biasing device, wherein the at least one first locking member is movable between a first locked position and a second unlocked position that enables rotation about a first axis; and
a second locking member in mechanical connection with the first locking member, wherein the second locking member is positioned proximal to the first electromagnet and opposite to the first locking member, wherein the second locking member is configured to control rotation about a second axis that is orthogonal to the first axis; and

at least one support arm extending from the joint and coupled to a support structure to support the at least one joint.
2. The limb support system of claim 1, wherein the biasing device is a second electromagnet.
3. The limb support system of claim 1, wherein the biasing device is a spring configured to bias the at least one first locking member towards biasing device.
4. The limb support system of claim 1, wherein the at least one first locking member is comprised of a rotation control plate and a stationary locking ring with internal teeth that mesh with teeth of the rotation control plate.
5. The limb support system of claim 4, wherein the stationary locking ring is coupled to a lower housing.
6. The limb support system of claim 1, wherein the second locking member is formed from at least one pad having teeth configured to engage teeth extending from a rotating gear coupled to a locking rod that is concentric with the second axis and wherein the at least one pad is movable between a locked position in which the at least one pad is in contact with the rotating gear and an unlocked position in which the at least one pad is not in contact with the rotating gear.
7. The limb support system of claim 6, wherein the at least one pad is positioned generally tangential to an outer tip of a tooth extending from the rotating gear.
8. The limb support system of claim 1, wherein the joint further comprises a housing formed from first and second subhousings, wherein the first subhousing encases the first locking member and is rotatable about the first axis and relative to the second subhousing, and the second subhousing encases the second locking member and is rotatable about the second axis such that the first and second subhousings rotate together about the second axis.
9. The limb support system of claim 8, wherein the first and second subhousings are generally cylindrical.
10. The limb support system of claim 9, wherein first subhousing is formed from a lower housing and a stationary locking ring of the first locking member, wherein the outer surfaces of the lower housing and the stationary locking ring are flush with each other.
11. A limb support system, comprising:
at least one joint configured to rotate about at least two axes that are orthogonal to each other, the at least one joint, comprising:
first and second electromagnets positioned generally opposite to each other with at least one first locking member positioned in between the first and second electromagnets, wherein the at least one first locking member is movable between a first locked position and a second unlocked position that enables rotation about a first axis; and
a second locking member in mechanical connection with the first locking member, wherein the second locking member is positioned proximal to the first electromagnet and opposite to the first locking member, wherein the second locking member is configured to control rotation about a second axis that is orthogonal to the first axis;

at least one support arm extending from the joint and coupled to a support structure to support the at least one joint; and
wherein the joint further comprises a housing formed from first and second subhousings, wherein the first subhousing encases the first locking member and is rotatable about the first axis and relative to the second subhousing, and the second subhousing encases the second locking member and is rotatable about the second axis such that the first and second subhousings rotate together about the second axis.
12. The limb support system of claim 11, wherein the at least one first locking member is comprised of a rotation control plate and a stationary locking ring with internal teeth that mesh with teeth of the rotation control plate.
13. The limb support system of claim 12, wherein the stationary locking ring is coupled to a lower housing.
14. The limb support system of claim 11, wherein the second locking member is formed from at least one pad having teeth configured to engage teeth extending from a rotating gear coupled to a locking rod that is concentric with the second axis and wherein the at least one pad is movable between a locked position in which the at least one pad is in contact with the rotating gear and an unlocked position in which the at least one pad is not in contact with the rotating gear.
15. The limb support system of claim 14, wherein the at least one pad is positioned generally tangential to an outer tip of a tooth extending from the rotating gear.
16. The limb support system of claim 15, wherein the first and second subhousings are generally cylindrical.
17. The limb support system of claim 16, wherein first subhousing is formed from a lower housing and a stationary locking ring of the first locking member, wherein the outer surfaces of the lower housing and the stationary locking ring are flush with each other.
18. A limb support system, comprising:
at least one joint configured to rotate about at least two axes that are orthogonal to each other, the at least one joint, comprising:
first and second electromagnets positioned generally opposite to each other with at least one first locking member positioned in between the first and second electromagnets, wherein the at least one first locking member is movable between a first locked position and a second unlocked position that enables rotation about a first axis; and
a second locking member in mechanical connection with the first locking member, wherein the second locking member is positioned proximal to the first electromagnet and opposite to the first locking member, wherein the second locking member is configured to control rotation about a second axis that is orthogonal to the first axis;

at least one support arm extending from the joint and coupled to a support structure to support the at least one joint;
wherein the joint further comprises a housing formed from first and second subhousings, wherein the first subhousing encases the first locking member and is rotatable about the first axis and relative to the second subhousing, and the second subhousing encases the second locking member and is rotatable about the second axis such that the first and second subhousings rotate together about the second axis;
wherein the at least one first locking member is comprised of a rotation control plate and a stationary locking ring with internal teeth that mesh with teeth of the rotation control plate; and
wherein the second locking member is formed from at least one pad having teeth configured to engage teeth extending from a rotating gear coupled to a locking rod that is concentric with the second axis and wherein the at least one pad is movable between a locked position in which the at least one pad is in contact with the rotating gear and an unlocked position in which the at least one pad is not in contact with the rotating gear.
19. The limb support system of claim 18, wherein the at least one pad is positioned generally tangential to an outer tip of a tooth extending from the rotating gear.
20. The limb support system of claim 18, wherein the first and second subhousings are generally cylindrical, wherein first subhousing is formed from a lower housing and a stationary locking ring of the first locking member, and wherein the outer surfaces of the lower housing and the stationary locking ring are flush with each other.