What is claimed is:
1. A method comprising:
monitoring a segment register to detect a segment register update operation;
once a segment register update operation is detected, identifying a codedata segment contained within the segment register, as one of a segmented codedata segment and a flat codedata segment; and
updating the segment register according to the identification of the codedata segment as one of a flat segment and a segmented segment.
2. The method of claim 1, wherein determining the OS memory model further comprises:
reading a base field of the segment register;
reading a limit field of the segment register;
when the contents of the base portion match a predetermined base value and contents of the limit field match a predetermined limit value, identifying the codedata segment as a flat segment; and
otherwise identifying the codedata segment as a segmented segment.
3. The method of claim 2, wherein reading the base portion of the segment register further comprising:
determining whether the segment register update has completed an update of the base field of the segment register; and
once the base field of the segment register is updated, reading contents of the segment register base field.
4. The method of claim 2, wherein reading the segment register limit field further comprises:
once segment register update of the segment register base field is complete, determining whether the segment register update has a completed updating of the limit field of the segment register; and
once update of the limit field of the segment register is complete, reading contents of the segment register limit field.
5. The method of claim 1, wherein updating the segment register further comprises:
selecting a first predetermined bit within the segment register;
setting the selected bit of the segment register according to contents of a base field of the segment register;
selecting a second predetermined bit within the segment register; and
setting the selected, second predetermined bit of the segment register according to contents of a limit field of the segment register.
6. The method of claim 5, wherein setting the first predetermined bit further comprises:
when the codedata segment is identified as a flat segment, setting a zero-base bit of the segment register to a value of one; and
otherwise setting the zero-base bit of the segment register to a value of zero.
7. The method of claim 5, wherein setting the second predetermined bit of the segment register further comprises:
when the codedata segment is identified as a flat segment, setting a one-limit bit of the segment register to a value of one; and
otherwise setting the one-limit bit of the segment register to a value of zero.
8. The method of claim 2, wherein the predetermined base value equals a value of zero.
9. The method of claim 2, wherein the predetermined limit value equals a hexadecimal value of FFFFF.
10. The method of claim 1, further comprising:
performing a segment register read operation;
selecting a one-limit bit, a zero-base bit, and a granularity bit of the segment register;
when each selected bit is set to a predetermined value, identifying the codedata segment as a flat segment; and
otherwise identifying the codedata segment as a segmented segment.
11. A method comprising:
performing a segment register read operation;
selecting one or more predetermined bits within the segment register; and
identifying a codedata segment within the segment register as one of a flat segment and a segmented segment according to values of the one or more selected, predetermined bits.
12. The method of claim 11, further comprising:
when a flat segment is detected, disabling effective address calculation logic within an address generation unit; and
disabling segment limit calculation logic within the address generation unit.
13. The method of claim 11, further comprising:
when a flat segment is detected, calculating an address of a conditional, direct branch as a code segment base associated with the conditional direct branch.
14. The method of claim 11, further comprising:
disabling, segment limit violation logic for one or more micro-operations of a macro instruction when a flat code segment is detected.
15. The method of claim 11, wherein selecting the one or more predetermined fields further comprises:
selecting a zero-base bit of the segment register;
selecting a one-limit bit of the segment register; and
selecting a granularity bit of the segment register.
16. The method of claim 11 wherein identifying the codedata segment further comprises:
selecting a zero-base bit, a one-limit bit and a granularity bit of the segment register; and
performing a conditional AND operation according to a value of the selected zero-base bit, the selected one-limit bit and the selected granularity bit;
when a result of the conditional AND operation is a one, identifying the codedata segment as a flat segment; and
otherwise identifying the codedata segment as a segmented segment.
17. The method of claim 12, wherein disabling the effective address calculation logic further comprises:
disabling a clock input to a dynamic effective address adder used to calculate an effective address for the codedata segment.
18. The method of claim 12, wherein disabling the segment limit calculation logic further comprises:
disabling a clock input to a dynamic borrow chain used to determine a segment limit violation according to the codedata segment.
19. The method of claim 14, wherein disabling further comprises:
selecting, by a reorder buffer (ROB), a code segment;
disabling a clock input to a dynamic barrow chain used to calculate a segment limit violation when the selected segment is identified as a flat segment.
20. The method of claim 11, wherein prior to performing the segment register read operation, the method further comprises:
monitoring a segment register to detect a segment register update operation;
once a segment register update operation is detected, identifying a codedata segment contained within the segment register, as one of a segmented codedata segment and a flat codedata segment; and
updating the segment register according to the identification of the codedata segment as one of a flat segment and a segmented segment.
21. A segment unit comprising:
a segment register file updated with a codedata segment during a segment register update; and
an interface coupled to the segment register file, the interface to identify a codedata segment contained within the segment register, as one of a segmented codedata segment and a flat codedata segment following a segmented register update, and to update segmented register file according identification of the codedata segment of the codedata segment as one of a flat segment and a segmented segment.
22. The segment unit of claim 21, wherein the interface is to cause assertiondeassertion of a flat segment signal, the interface to cause assertiondeassertion according to one or more control bits of the segment register if a segment register read operation is detected.
23. The segment unit of claim 21, wherein the interface is to set a segment register zero-base bit according to contents of a base field of the segment register and to set a one-limit bit of the segment register according to contents of a limit field of the segment register.
24. The segment unit of claim 22, wherein the interface further comprises:
logic to assertdeassert the flat segment signal according to a conditional AND operation of a zero-base bit, a one-limit bit and a granularity bit of the segment register file.
25. A system comprising:
a bus;
a chipset coupled to the bus; and
a processor, coupled to the bus, comprising:
a segment register file updated with a codedata segment during a segment register update; and
an interface coupled to the segment register file, the interface to identify a codedata segment contained within the segment register, as one of a segmented codedata segment and a flat codedata segment following a segmented register update, and to update segmented register file according to identification of the codedata segment as one of a flat segment and a segmented segment.
26. The system of claim 25, wherein the processor comprises:
an address generation unit to perform a register read operation according to loadstore operations, the address generation unit to disable effective address calculation logic and segment limit violation logic according to a flat segment signal received from the segment unit.
27. The system of claim 25, wherein the processor further comprises:
a retirement unit including a reorder buffer (ROB), the ROB to disableenable segment limit violation logic for selected code segments identified as flat segments if a segment register read operation is performed.
28. An article comprising a machine readable medium that carries data representing an integrated circuit comprising:
a processor, comprising:
a segment register file updated with a codedata segment during a segment register update; and
an interface coupled to the segment register file, the interface to identify a codedata segment contained within the segment register, as one of a segmented codedata segment and a flat codedata segment following a segmented register update, and to update segmented register file according to identification of the codedata segment as one of a flat segment and a segmented segment.
29. The article of claim 28, carrying further data representing the integrated circuit further comprising:
an address generation unit to perform a register read operation according to loadstore operations, the address generation unit to disable effective address calculation logic and segment limit violation logic according to a flat segment signal received from the segment unit.
30. The article of claim 28, carrying further data representing the integrated circuit further comprising:
a retirement unit including a reorder buffer (ROB), the ROB to disableenable segment limit violation logic for selected code segments identified as flat segments if a segment register read operation is performed.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for manufacturing a vehicle body panel, comprising:
applying a plastic film onto a reverse side of a film-like exterior covering;
hardening the plastic film; and
applying a back-foamed layer on top of the hardened plastic film.
2. The method of claim 1, wherein the film is applied by a spraying process.
3. The method as recited in claim 1, wherein the step of applying the back-foamed layer comprises:
applying liquid plastic onto the plastic film after the hardening step; and
foaming the liquid plastic to form the back-foamed layer on the plastic film.
4. The method as recited in claim 1, further comprising adding fibers to the back-foamed layer.
5. The method as recited in claim 4, wherein the fibers are added by a long fiber injection method.
6. The method as recited in claim 4, wherein the fibers are added by placing a fiber mat onto the hardened plastic film before the step of applying the back-foamed layer.
7. The method as recited in claim 4, wherein the fibers are added by being mixed with a material used to form the back-foamed layer.
8. The method as recited in claim 1, wherein the exterior covering is disposed in an open foam die, and wherein the steps of applying the plastic film, hardening the plastic film, and applying the back-foamed layer are conducted in the open foam die.
9. The method as recited in claim 8, further comprising placing at least one insert into the open foam die before the step of applying the back-foamed layer, wherein said at least one insert is embedded into the back-foamed layer after the step of applying the back-foamed layer.
10. The method as recited in claim 8, wherein the open foam die comprises an upper mold half and a lower mold half, and wherein the step of applying the back-foamed layer comprises molding the back-foamed layer against the upper mold half to form varying thicknesses in the back-foamed layer.
11. A vehicle body panel, comprising:
a film-like exterior covering;
a rigid film disposed on a reverse side of the exterior covering; and
a back-foamed layer on top of the rigid film.
12. The vehicle body panel as recited in claim 11, wherein the back-foamed layer is a hardened back-foamed layer, and wherein the hardness of the hardened plastic film is greater than that of the hardened back-foamed layer.
13. The vehicle body panel as recited in claim 11, further comprising fibers disposed in the back-foamed layer.
14. The vehicle body panel as recited in claim 13, wherein the fibers are formed in a fiber mat.
15. The vehicle body panel as recited in claim 13, wherein the fibers are dispersed throughout the back-foamed layer.
16. The vehicle body panel as recited in claim 11, further comprising at least one insert embedded into the back-foamed layer.
17. The vehicle body panel as recited in claim 11, wherein the foamed layer is a single back-foamed layer having varying thicknesses.
18. The vehicle body panel as recited in claim 17, wherein the varying thicknesses in the back-foamed layer differ by at least a factor of two.
19. The vehicle body panel as recited in claim 11, wherein the exterior covering is a sheet made of material selected from the group consisting of aluminum and plastic.
20. The vehicle body panel as recited in claim 11, wherein the rigid film is made of a thermosetting material.
21. The vehicle body panel as recited in claim 20, wherein the thermosetting material is one selected from the group consisting of polyester resin and polyurethane.