Author: claimsbot

What is claimed is:

1. A characterization vehicle, comprising:
a substrate having at least one layer; and
a plurality of pairs of lines on a single surface of a single layer of the substrate, each pair of lines having a shared pad therebetween.
2. The characterization vehicle of claim 1, wherein the lines are nested serpentine lines.
3. The characterization vehicle of claim 2, wherein none of the nested serpentine lines crosses any other one of the nested serpentine lines.
4. The characterization vehicle of claim 2, wherein the nested serpentine lines within each pair are not adjacent to each other.
5. The characterization vehicle of claim 2, wherein:
each pair of lines includes a respective first line and a respective second line;
the first lines are arranged in a first sequence; and
the second lines are arranged in a second sequence different from the first sequence.
6. The characterization vehicle of claim 5, wherein:
each first line has a respective position within the first sequence;
each second line has a respective position within the second sequence; and
within each pair of lines, the position of the second line within the second sequence is different from the position of the corresponding first line within the first sequence.
7. The characterization vehicle of claim 5, wherein:
the first line in each pair is adjacent to one or more neighboring first lines;
the second line in each pair is adjacent to one or more neighboring second lines; and
the one or more neighboring second lines corresponding to the second line in each respective pair belong to different pairs of lines than the one or more neighboring lines corresponding to the first line in that pair.
8. The characterization vehicle of claim 5, wherein:
for each position, the first line having that position in the first sequence belongs to a different pair of lines than the second line having that position within the second sequence.
9. The characterization vehicle of claim 2, wherein:
the surface has first and second sides;
each pair of nested serpentine lines includes a first line and a second line, such that:
the first line extends beyond the pads on the first side of the surface;
the second line extends beyond the pads on the second side of the surface; and

none of the nested serpentine lines crosses any other one of the nested serpentine lines.
10. A method of designing a characterization vehicle, comprising the steps of:
arranging a plurality of pairs of lines on a single surface of a single layer of a substrate; and
locating a respective shared pad between the lines of each pair of lines.
11. The method of claim 10, wherein the lines are nested serpentine lines.
12. The method of claim 11, wherein none of the nested serpentine lines crosses any other one of the nested serpentine lines.
13. The method of claim 11, wherein the nested serpentine lines within each pair are not adjacent to each other.
14. The method of claim 11, wherein:
each pair of lines includes a respective first line and a respective second line;
the first lines are arranged in a first sequence; and
the second lines are arranged in a second sequence different from the first sequence.
15. The method of claim 14, wherein:
each first line has a respective position within the first sequence;
each second line has a respective position within the second sequence; and
within each pair of lines, the position of the second line within the second sequence is different from the position of the corresponding first line within the first sequence.
16. The method of claim 14, wherein:
the first line in each pair is adjacent to one or more neighboring first lines;
the second line in each pair is adjacent to one or more neighboring second lines; and
the one or more neighboring second lines corresponding to the second line in each respective pair belong to different pairs of lines than the one or more neighboring lines corresponding to the first line in that pair.
17. A method of identifying defects, comprising the steps of:
fabricating a characterization vehicle by forming a plurality of pairs of lines on a single surface of a single layer of a substrate, each pair of lines having a shared pad therebetween; and
collecting defect data from the characterization vehicle.
18. The method of claim 17, wherein the lines are nested serpentine lines.
19. The method of claim 18, further comprising determining which one of a pair of serpentine lines sharing a pad therebetween has a defect by identifying a sequence of serpentine lines that are shorted together.
20. A method of determining defect size distributions, comprising the steps of:
(a) collecting defect size distributions from a characterization vehicle by forming a plurality of pairs of lines on a single surface of a single layer of a substrate, each pair of nested having a shared pad therebetween; and
(b) determining which one of a pair of lines sharing a pad therebetween has a defect by identifying a sequence of the that are shorted together.
21. The method of claim 20, wherein the lines are nested serpentine lines.
22. The method of claim 21, wherein step (a) includes forming a histogram of a number of defects detected versus defect size.
23. The method of claim 21, wherein step (a) includes forming a histogram of a number of defects detected versus defect size.
24. The method of claim 23, further comprising using the defect density function to form a yield model.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An amorphous microwire coated with an insulating sleeve, consisting of:
a metal core made up of an alloy of transition metals and metalloid elements, in a proportion between 65%\u201390% and 10%\u201335%, respectively,
an insulating glass sleeve

characterized in that
the transition metals are at least iron, the relative proportion of iron being between 65%\u2013100% of the total transition metals,

and in that
the core diameter (Dc) is comprised between 2 \u03bcm and 20 \u03bcm, such that the magnetostriction constant (\u03bb) of the metal alloy is comprised between 1 and 30 ppm, and the natural ferromagnetic resonance frequency is comprised between 3 and 20 GHz.
2. A microwire according to claim 1, characterized in that the core diameter (Dc) is comprised between 2 \u03bcm and 10 \u03bcm.
3. A microwire according to claim 1, characterized in that the metalloid elements are manganese, silicon, boron and carbon.
4. A microwire according to claim 1, characterized in that the proportion of the core diameter (Dc) to the total diameter (Dt) of the microwire is comprised between 0.18 and 0.6.
5. A microwire according to claim 1, characterized in that the composition of the metal core is Fe89B1Si3C3Mn4.
6. A microwire according to claim 1, characterized in that the composition of the metal core is Fe69B16Si10C5.
7. A microwire according to claim 1, characterized in that it has a bistable magnetic behavior.
8. A microwire according to claim 1, characterized in that it has an anisotropy field comprised between 0.5 and 10 Oe.
9. A microwire according to claim 1, characterized in that its natural ferromagnetic resonance frequency increases with the anisotropy field.

1. A method of delivering a therapeutic amount of an indole serotonin receptor agonist to an individual in need thereof, the method comprising contacting a topical surface of said individual with a transdermal formulation comprising said indole receptor serotonin agonist.
2. The method according to claim 1, wherein said transdermal formulation is a patch, a gel, a cream, a foam, a lotion, a spray, an ointment.
3. The method according to claim 2, wherein said transdermal formulation is a patch formulation comprising an adhesive polymer.
4. The method according to claim 3, wherein said method comprising adhering said patch formulation to a skin surface of the individual.
5. The method of claim 1, wherein said method is a method of treating a headache.
6. The method of claim 1, wherein said method is a method of preventing a headache.
7. The method of claim 1, wherein the method provides for a level of indole serotonin receptor agonist in the individual that is effective to inhibit migraine pain.
8. The method of claim 1, wherein the method provides a substantially constant level of an indole serotonin receptor agonist in the individual over an extended period of time.
9. A method of preventing a headache in an individual, the method comprising contacting a topical surface of said individual with a transdermal formulation comprising an indole receptor serotonin agonist.
10. The method according to claim 9, wherein said transdermal formulation is a patch, a gel, a cream, a foam, a lotion, a spray, or an ointment.
11. The method according to claim 9, wherein said transdermal formulation is a patch formulation comprising an adhesive polymer.
12. The method according to claim 11, wherein said contacting comprises adhering said patch formulation to a skin surface of the individual.
13. The method according to claim 9, wherein said headache is a migraine headache.
14. The method of claim 9, wherein the method provides a substantially constant level of an indole serotonin receptor agonist in the individual over an extended period of time.
15. A method of treating an individual for a headache, said method comprising: contacting a topical surface of said individual with a transdermal formulation comprising an indole receptor serotonin agonist.
16. The method according to claim 15, wherein said transdermal formulation is a patch, a gel, a cream, a foam, a lotion, a spray, or an ointment.
17. The method according to claim 16, wherein said transdermal formulation is a patch formulation comprising an adhesive polymer.
18. The method according to claim 17, wherein said contacting comprises adhering said patch formulation to a forehead skin of the individual.
19. A transdermal formulation comprising:
a) an adhesive layer comprising an indole serotonin receptor agonist; and
b) a backing layer.
20. The transdermal formulation of claim 19, wherein said agonist is present in an amount of from about 0.5 weight % to about 50 weight %
21. The transdermal formulation according to claim 19, wherein said formulation further comprises a hydrophobic oil.
22. The transdermal formulation according to claim 21, wherein said hydrophobic oil is present in an amount of from about 2 weight % to about 50 weight
23. The transdermal formulation of claim 19, wherein said indole serotonin receptor agonist is selected from sumatriptan, frovatriptan, zolmitriptan, eletriptan, rizatriptan, naratriptan, and almotriptan.
24. The transdermal formulation of claim 21, wherein said hydrophobic oil is selected from a higher fatty acid ester, an oil, a fat, a higher fatty acid, and a higher alcohol.
25. The transdermal formulation of claim 19, wherein the adhesive layer further comprises a transdermal absorption enhancing agent in an amount of from about 0.01 weight % to about 20 weight %.
26. The transdermal formulation of claim 25, wherein said absorption enhancing agent is selected from lauric acid diethanolamine, tetraethyl glycol laurate, glycerol monolaurate, sorbitan trioleate, and a polyol.
27. The transdermal formulation of claim 19, further comprising a detachable protective layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor memory device comprising:
an n-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region; and a gate electrode formed over the charge storage layer;
a power supply circuit formed on the semiconductor substrate and connected to the first diffused region, the power supply circuit, pumping a voltage supplied from an outside power supply and outputting the pumped voltage; and
writing means which, upon writing to the n-channel memory cell transistor, applies a ground voltage to the second diffused region, and applies a negative voltage supplied from the power supply circuit to the first diffused region to thereby flow current between the first diffused region and the second diffused region and to store charges in the charge storage layer.
2. The semiconductor memory device according to claim 1, wherein
the power supply circuit is connected to the gate electrode.
3. The semiconductor memory device according to claim 1, wherein
the first diffused region is connected to the power supply circuit via a bit line, and
the second diffused region is connected to the ground voltage via a source line.
4. The semiconductor memory device according to claim 1, wherein,
the first diffused region is connected to the power supply circuit via a source line, and
the second diffused region is connected to the ground voltage via a bit line.
5. A method for writing to a semiconductor memory device comprising an n-channel memory cell transistor including a first diffused region and a second diffused region formed in a semiconductor substrate, a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region, and a gate electrode formed over the charge storage layer; and a power supply circuit formed on the semiconductor substrate, the power supply circuit being connected to the first diffused region, pumping a voltage supplied from an outside power supply and outputting the pumped voltage, comprising:
applying a ground voltage to the second diffused region, supplying a negative voltage from the power supply circuit, and applying the negative voltage to the first diffused region, whereby current is flowed between the first diffused region and the second diffused region, and charges are stored in the charge storage layer.
6. The method for writing to a semiconductor memory device according to claim 5, wherein
a negative voltage is applied to the gate electrode to thereby execute a write-back programming in the n-channel memory cell transistor.
7. The method for writing to a semiconductor memory device according to claim 6, wherein
the negative voltage supplied from the power supply circuit is applied to the gate electrode.
8. The method for writing to a semiconductor memory device according to claim 5, wherein
a positive voltage is applied to the gate electrode to thereby write a memory information in the n-channel memory cell transistor.
9. The method for writing to a semiconductor memory device according to claim 5, wherein
the negative voltage is applied to the first diffused region via a bit line, and
the ground voltage is applied to the second diffused region via a source line.
10. The method for writing to the semiconductor memory device according to claim 5, wherein
the negative voltage is applied to the first diffused region via a source line, and
the ground voltage is applied to the second diffused region via a bit line.
11. The method for writing to a semiconductor memory device according to claim 5, wherein
the n-channel memory cell transistor is formed in a p-well formed in an n-well formed in the semiconductor substrate, and
a negative voltage supplied from another power supply circuit which is different from said the power supply circuit is applied to the p-well.
12. A semiconductor memory device comprising:
a p-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region; and a gate electrode formed over the charge storage layer;
a power supply circuit formed on the semiconductor substrate and connected to the first diffused region, the power supply circuit pumping a voltage supplied from an outside power supply and outputting the pumped voltage; and
writing means which, upon writing to the p-channel memory cell transistor, applies a ground voltage to the second diffused region, and applies a positive voltage supplied from the power supply circuit to the first diffused region to thereby flow current between the first diffused region and the second diffused region and to store charges in the charge storage layer.
13. The semiconductor memory device according to claim 12, wherein the power supply circuit is connected to the gate electrode.
14. The semiconductor memory device according to claim 12, wherein the first diffused region is connected to the power supply circuit via a bit line, and the second diffused region is connected to the ground voltage via a source line.
15. The semiconductor memory device according to claim 12, wherein,
the first diffused region is connected to the power supply circuit via a source line, and
the second diffused region is connected to the ground voltage via a bit line.
16. A method for writing to a semiconductor memory device comprising a p-channel memory cell transistor including a first diffused region and a second diffused region formed in a semiconductor substrate, a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region, and a gate electrode formed over the charge storage layer; and a power supply circuit formed on the semiconductor substrate, the power supply circuit being connected to the first diffused region, pumping a voltage supplied from an outside power supply and outputting the pumped voltage, comprising:
applying a ground voltage to the second diffused region, supplying a positive voltage from the power supply circuit, and applying the positive voltage to the first diffused region, whereby current is flowed between the first diffused region and the second diffused region, and charges are stored in the charge storage layer.
17. The method for writing to a semiconductor memory device according to claim 16, wherein
a positive voltage is applied to the gate electrode to thereby execute a write-back programming in the p-channel memory cell transistor.
18. The method for writing to a semiconductor memory device according to claim 17, wherein
the positive voltage supplied from the power supply circuit is applied to the gate electrode.
19. The method for writing to a semiconductor memory device according to claim 16, wherein
the positive voltage is applied to the first diffused region via a bit line, and the ground voltage is applied to the second diffused region via a source line.
20. The method for writing to the semiconductor memory device according to claim 16, wherein
the positive voltage is applied to the first diffused region via a source line, and
the ground voltage is applied to the second diffused region via a bit line.
21. The method for writing to a semiconductor memory device according to claim 16, wherein
the p-channel memory cell transistor is formed in a n-well formed in an p-well formed in the semiconductor substrate, and
a positive voltage supplied from another power supply circuit which is different from said the power supply circuit is applied to the n-well.
22. The method for writing to a semiconductor memory device according to claim 16, wherein
a negative voltage is applied to the gate electrode to thereby write a memory information in the p-channel memory cell transistor.