Author: claimsbot

1. A method for decompressing image data, that is compressed by discarding pixels along a direction parallel to an edge while maintaining pixels along a direction perpendicular to the edge, representing a plurality of pixels and represented by a plurality of bitwords, each pixel corresponding to a separate bitword, the process comprising:
decompressing data from a compressed-data-bitword to provide data indicative of a plurality of explicit pixels; and
synthesizing data from the data indicative of the plurality of explicit pixels to provide data corresponding to at least one synthesized pixel, the at least one synthesized pixel representing at least one discarded pixel.
2. The method of claim 1, wherein decompressing a quantity of non-continuous tone data is increased to approximately four times of a quantity of uncompressed non-continuous tone data present in a plurality of bitwords representing a plurality of pixels.
3. The method of claim 1, wherein, during decompression, non-continuous tone data with a high spatial resolution in one dimension is decompressed into a high spatial resolution bitword-map with reference to information indicating the direction of the edge within the image data.
4. The method of claim 1, wherein, decompressing the data from the compressed bitword for a single data pixel comprises:
identifying a bit word as continuous tone data; and
decompressing continuous tone data to provide image data for a single pixel at a higher spatial resolution corresponding to a plurality of pixels.
5. The method of claim 4, wherein, decompressing the data from the compressed bitword for a single data pixel comprises: synthesizing bitwords of information corresponding to discarded non-continuous tone data; and
copying the single pixel to provide the image for the surrounding pixels.
6. The method of claim 1, wherein each of the bitwords are bytes.
7. The method of claim 6, wherein, for each bitword, synthesizing the data is performed in either a fastscan direction or a slowscan direction based on a direction bit contained in that bitword.
8. The method of claim 7, wherein, synthesizing the data comprises determining which pixel positions are to be synthesized during decompression based on the direction bit.
9. A method for decompressing image data, that is compressed by discarding pixels along a direction parallel to an edge, representing a plurality of pixels and represented by a plurality of bitwords, each pixel corresponding to a separate bitword, the process comprising:
decompressing data from a compressed-data-bitword to provide data indicative of a plurality of explicit pixels; and
synthesizing data from the data indicative of the plurality of explicit pixels to provide data corresponding to at least one synthesized pixel, the at least one synthesized pixel representing at least one discarded pixel,
wherein each of the bitwords are bytes;
wherein decompressing the data from the compressed bitword comprises:
referencing a segmentation bit of the bitword to determine whether the bitword contains non-continuous tone data;
referencing a direction bit to determine whether the direction of the edge located in spaced relationship to a first and a second pixel;
referencing a three-bit value indicative of the first pixel; and
referencing a three-bit value indicative of the second pixel.
10. A method for decompressing image data, that is compressed by discarding pixels along a direction parallel to an edge, representing a plurality of pixels and represented by a plurality of bitwords, each pixel corresponding to a separate bitword, the process comprising:
decompressing data from a compressed-data-bitword to provide data indicative of a plurality of explicit pixels; and
synthesizing data from the data indicative of the plurality of explicit pixels to provide data corresponding to at least one synthesized pixel, the at least one synthesized pixel representing at least one discarded pixel;
wherein each of the bitwords are bytes;
wherein for each bitword, synthesizing the data is performed in either a fastscan direction or a slowscan direction based on a direction bit contained in that bitword;
wherein synthesizing the data comprises:
determining which pixel positions are to be synthesized during decompression based on the direction bit;
rendering from each bitword twice as many pixels in a direction perpendicular to an edge indicated by the direction bit of that bitword.
11. A method for decompressing image data, that is compressed by discarding pixels along a direction parallel to an edge, representing a plurality of pixels and represented by a plurality of bitwords, each pixel corresponding to a separate bitword, the process comprising:
decompressing data from a compressed-data-bitword to provide data indicative of a plurality of explicit pixels; and
synthesizing data from the data indicative of the plurality of explicit pixels to provide data corresponding to at least one synthesized pixel, the at least one synthesized pixel representing at least one discarded pixel;
wherein each of the bitwords are bytes;
wherein for each bitword, synthesizing the data is performed in either a fastscan direction or a slowscan direction based on a direction bit contained in that bitword;
wherein synthesizing the data comprises:
determining which pixel positions are to be synthesized during decompression based on the direction bit;
when the direction bit indicates a vertical edge, using the three-bit value associated with the first pixel and the three-bit value associated with the second pixel in the compressed-data-bitword to determine slope in the fast scan direction to render the vertical edge.
12. A method for decompressing image data, that is compressed by discarding pixels along a direction parallel to an edge, representing a plurality of pixels and represented by a plurality of bitwords, each pixel corresponding to a separate bitword, the process comprising:
decompressing data from a compressed-data-bitword to provide data indicative of a plurality of explicit pixels; and
synthesizing data from the data indicative of the plurality of explicit pixels to provide data corresponding to at least one synthesized pixel, the at least one synthesized pixel representing at least one discarded pixel;
wherein each of the bitwords are bytes;
wherein for each bitword, synthesizing the data is performed in either a fastscan direction or a slowscan direction based on a direction bit contained in that bitword;
wherein synthesizing the data comprises:
determining which pixel positions are to be synthesized during decompression based on the direction bit;
when the direction bit indicates a horizontal edge, using the three-bit value associated with the first pixel and the three-bit value associated with the second pixel in the byte of compressed data to determine slope in the slow scan direction to render the horizontal edge.
13. A method for decompressing compressed image data that is compressed by discarding pixels along a direction parallel to an edge while maintaining pixels along a direction perpendicular to the edge, the method comprising:
decompressing a single byte of compressed data to produce four pixels of non-continuous tone data.
14. The method of claim 13, further comprising, transmitting the byte of data to a print engine where the step of decompressing is performed, the step of decompressing including extracting data necessary to render two non-continuous tone data pixels and fabricating two more non-continuous tone data pixels in a low-spatial resolution direction based on a set of values of the extracted data.
15. The method of claim 13, wherein the four pixels represent a two-by-two pixel array.
16. A decompression system for decompressing image data, the image data containing non-continuous tone data and continuous tone data, the non-continuous tone data compressed by discarding pixels along a direction parallel to an edge while maintaining pixels along a direction perpendicular to the edge, the system comprising:
a decompressor that decompresses a data bitword-map to provide high spatial resolution data containing non-continuous tone data using extra resolution in a direction substantially perpendicular to an edge of marks, and that decompresses the data bitword-map to provide low spatial resolution continuous tone data.
17. The decompression system of claim 16, further comprising an image forming device, wherein the decompression system is incorporated in the image forming device.
18. The decompression system of claim 17, wherein the image forming device is one of at least a facsimile machine, a laser printer, an inkjet printer, a digital copier or a full-width-print bar printer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for executing a processing routine utilizing an internal memory and an external memory and requiring more than one external memory access, comprising the step of:
distributing the external memory accesses based on a predetermined number of consecutive external memory accesses wherein distributing external memory accesses comprises interrupting access to the external memory after a predetermined number of external memory accesses with a predetermined number of internal memory accesses.
2. The method of claim 1, further comprising the step of distributing the external memory accesses such that the number of consecutive external memory accesses is minimized.
3. The method of claim 1, further comprising the step of distributing the external memory accesses substantially evenly.
4. The method of claim 1, wherein the step of distributing the external memory accesses comprises temporarily interrupting access to the external memory for a predetermined amount of time after a predetermined number of consecutive external memory accesses.
5. The method of claim 1, wherein the predetermined number of consecutive external memory accesses is based on an available energy supply.
6. A method for executing a processing routine utilizing an internal memory and an external memory, comprising the steps of:
determining an available energy supply;
accessing the external memory only if the available energy supply exceeds a threshold value; and
accessing the internal memory if the available energy supply does not exceed the threshold value.
7. The method of claim 6, further comprising the step of distributing the external memory accesses if the available energy supply does not exceed a threshold value.
8. The method of claim 7, further comprising the step of distributing the external memory accesses based on a predetermined number of consecutive external memory accesses.
9. The method of claim 8, wherein the predetermined number of consecutive external memory accesses is determined at least in part by the available energy supply level.
10. The method of claim 7, wherein the processing routine further utilizes an internal memory and the method further comprises the step of distributing access to the external memory by interrupting access to the external memory after a predetermined number of consecutive external memory accesses with a predetermined number of internal memory accesses.
11. A processing system (100), comprising:
an internal memory (102) and an external memory (103); and
a processor (101) adapted to execute a processing routine utilizing the internal memory (102) and the external memory (103), wherein the processor (101) is configured to:
distribute external memory accesses based on a predetermined number of consecutive external memory accesses; and
distribute external memory accesses by interrupting access to the external memory (103) after a predetermined number of external memory accesses with a predetermined number of internal memory accesses.
12. The processing system (100) of claim 11, wherein the processor (101) is further configured to distribute the external memory accesses such that the number of consecutive external memory accesses is minimized.
13. The processing system (100) of claim 11, wherein the processor (101) is further configured to substantially evenly distribute the external memory accesses.
14. The processing system (100) of claim 11, wherein the processor (101) is further configured to temporarily interrupt access to the external memory (103) for a predetermined amount of time after a predetermined number of consecutive external memory accesses.
15. The processing system (100) of claim 11, wherein the predetermined number of consecutive external memory accesses is based on an available energy supply.

1. A valve comprising:
a housing assembly having an inlet in fluid communication with an inlet passage, an outlet in fluid communication with an outlet passage and a valve chamber, said inlet passage and said outlet passage each in fluid communication with said valve chamber;
a stem assembly rotatably disposed within said housing assembly, said stem assembly having an exposed handle extending out of said housing assembly and a second end disposed within said valve chamber;
a surge suppression device comprising:
an initial flowpath between said inlet and said outlet;
a primary flowpath between said inlet and said outlet;
a first valve assembly coupled to said stem assembly and threadably engaging said housing assembly and structured to move between a first, closed position wherein said primary flowpath is blocked and a second, open position wherein said primary flowpath is not blocked;
a second valve assembly threadably coupled, indirectly, to said housing assembly and structured to move between a first, closed position wherein said initial flowpath is blocked and a second, open position wherein said initial flowpath is not blocked;
wherein said second valve assembly is threadably coupled, indirectly, to said first valve assembly;
said stem assembly second end is coupled to said second valve assembly; and
upon rotation of said stem assembly, said second valve assembly is structured to rotate relative to said first valve assembly prior to said first valve assembly rotating relative to said housing assembly.
2. The valve of claim 1 wherein said second valve assembly threadably engages said first valve assembly and said second valve assembly is structured to move between said first and second positions prior to said first valve assembly moving between said first and second positions.
3. The valve of claim 2 wherein
said valve chamber includes internal threads;
said first valve assembly includes a body having an outer threaded surface; and
said first valve assembly outer threaded surface is structured to engage said valve chamber internal threads.
4. The valve of claim 3 wherein
said first valve assembly is cup-shaped having a disk and a sidewall defining an upwardly opening cavity, said cavity having an inner threaded surface;
said second valve assembly includes a body having an outer threaded surface; and
said second valve assembly outer threaded surface is structured to engage said cavity inner threaded surface.
5. The valve of claim 4 wherein
said first valve assembly disk includes a micro-passage and
said second valve assembly includes a sealing member structured to engage said micro-passage; and
said micro-passage being part of said initial flowpath.
6. The valve of claim 5 wherein said micro-passage has a cross-section area between about 0.00000707 and 0.0000283 in2.
7. The valve of claim 5 wherein said micro-passage has a cross-section area of about 0.0000283 in2.
8. The valve of claim 5 wherein
said first valve assembly includes a sealing member structured to engage the periphery of said first inlet passage and having a central opening therethrough;
said central opening aligned with said micro-passage.
9. The valve of claim 8 wherein a filter is disposed in said initial flowpath.
10. The valve of claim 8 wherein said first valve assembly includes a filter in fluid communication with said micro-passage and wherein said initial flowpath extends through said filter.
11. The valve of claim 2 wherein a filter is disposed in said initial flowpath.
12. The valve of claim 11 wherein said first valve assembly includes a micro-passage and a filter in fluid communication with said micro-passage and wherein said initial flowpath extends through said filter and said micro-passage.
13. The valve of claim 2 wherein
said first valve assembly threadably engages said housing assembly, said first valve assembly having a body with a disk, a sidewall forming an upwardly opening threaded cavity, an upper stop means, a micro-passage through said disk, and a sealing member;
said first valve assembly structured to move between a first position wherein said first valve seal member sealingly engages the periphery of said inlet passage and a second position wherein said first valve seal member is spaced from said inlet passage;
said upwardly opening, threaded cavity in fluid communication with said valve chamber;
said micro-passage extending between, and in fluid communication with, said inlet passage and said upper, treaded cavity;
a second valve assembly disposed within, and threadably engaging, said upper, threaded cavity, said second valve assembly having a sealing member and a stem assembly coupling, said second valve assembly further coupled to said stem assembly second end;
said second valve assembly structured to move between a first position wherein said second valve seal member sealingly engages said micro-passage and a second position wherein said second valve seal member is spaced from said micro-passage; and
wherein rotation of said stem assembly initially causes said second valve member to rotate in said upper, threaded cavity until said second valve member either engages said upper stop means or said second seal member engages said micro-passage, whereupon rotation of said stem assembly causes said first valve member to rotate and thereby move between said first valve first position and said first valve second position.
14. The valve of claim 13 wherein the surface of said valve chamber adjacent said first valve assembly includes threads structured to engage said first valve assembly.
15. The valve of claim 14 wherein said upper, threaded cavity threads are structured so that said stem assembly must be turned more than 360 degrees to move said second valve assembly between said first position and contacting said stop means.
16. The valve of claim 14 wherein a friction reducing coating is disposed between said first valve assembly and said second valve assembly.
17. The valve of claim 16 wherein a filter is disposed in said initial flowpath.
18. The valve of claim 17 wherein said first valve assembly includes a filter in fluid communication with said micro-passage and wherein said initial flowpath extends through said filter.
19. The valve of claim 18 wherein said micro-passage has a cross-section area between about 0.00000707 and 0.0000283 in2.
20. The valve of claim 18 wherein said micro-passage has a cross-section area of about 0.0000283 in2.
21. The valve of claim 1 wherein there is a low-friction coating disposed between said first valve assembly and said second valve assembly.
22. A high pressure gas cylinder having a valve with a pressure rate reduction device comprising:
a rigid housing having at least one opening therethrough;
a valve coupled to said housing at said opening, said valve comprising:
a housing assembly having an inlet in fluid communication with an inlet passage, an outlet in fluid communication with an outlet passage and a valve chamber, said inlet passage and said outlet passage each in fluid communication with said valve chamber;
a stem assembly rotatably disposed within said housing assembly, said stem assembly having an exposed handle extending out of said housing assembly and a second end disposed within said valve chamber;
a pressure rate reduction device comprising:
an initial flowpath between said inlet and said outlet;
a primary flowpath between said inlet and said outlet;
a first valve assembly coupled to said stem assembly and threadably engaging said housing assembly and structured to move between a first, closed position wherein said primary flowpath is blocked and a second, open position wherein said primary flowpath is not blocked; and
a second valve assembly threadably coupled to said housing assembly and structured to move between a first, closed position wherein said initial flowpath is blocked and a second, open position wherein said initial flowpath is not blocked;
wherein said second valve assembly is threadably coupled to said first valve assembly;
said stem assembly second end is coupled to said second valve assembly; and
upon rotation of said stem assembly, said second valve assembly is structured to rotate relative to said first valve assembly prior to said first valve assembly rotating relative to said housing assembly.
23. The cylinder of claim 22 wherein said second valve assembly threadably engages said first valve assembly and said second valve assembly is structured to move between said first and second positions prior to said first valve assembly moving between said first and second positions.
24. The cylinder of claim 23 wherein
said first valve assembly threadably engages said housing assembly, said first valve assembly having a body with a disk, a sidewall forming an upwardly opening threaded cavity, an upper stop means, a micro-passage through said disk, and a sealing member;
said first valve assembly structured to move between a first position wherein said first valve seal member sealingly engages the periphery of said inlet passage and a second position wherein said first valve seal member is spaced from said inlet passage;
said upwardly opening, threaded cavity in fluid communication with said valve chamber;
said micro-passage extending between, and in fluid communication with, said inlet passage and said upper, treaded cavity;
a second valve assembly disposed within, and threadably engaging, said upper, threaded cavity, said second valve assembly having a sealing member and a stem assembly coupling, said second valve assembly further coupled to said stem assembly second end;
said second valve assembly structured to move between a first position wherein said second valve seal member sealingly engages said micro-passage and a second position wherein said second valve seal member is spaced from said micro-passage; and
wherein rotation of said stem assembly initially causes said second valve member to rotate in said upper, threaded cavity until said second valve member either engages said upper stop means or said second seal member engages said micro-passage, whereupon rotation of said stem assembly causes said first valve member to rotate and thereby move between said first valve first position and said first valve second position.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power detector comprising:
a detection power input circuit for receiving an RF signal, said detection power input circuit comprises;
a first resistor including a first terminal for receiving the RF signal and including a second terminal,
a first capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal, and
a second resistor including a first terminal coupled to the second terminal of the first capacitor and including a second terminal;

a bias circuit including an output for generating a bias signal in response to a reference control voltage, said bias circuit comprising;
a third resistor including a first terminal coupled to a reference voltage terminal and including a second terminal coupled to the second terminal of the second resistor,
a first bipolar transistor including a collector coupled to the second terminal of the third resistor, a base coupled to said collector, and an emitter, and
a fourth resistor including a first terminal coupled to the emitter of the first bipolar transistor and including a second terminal coupled to a ground terminal;

a detection circuit, having a second bipolar transistor having a collector, emitter and base, for generating a power control voltage at the emitter, having a voltage characteristic that offsets temperature characteristics of the received RF signal, which can be adjusted independently by the size of the first and second bipolar transistors, with the detection circuit forming a current mirror with the bias circuit, wherein said detection circuit comprises;
said second bipolar transistor including a collector coupled to a voltage supply terminal, including a base coupled to the first terminal of the second resistor, and including an emitter,
a fifth resistor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal coupled to the ground terminal,
a second capacitor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal coupled to the ground terminal, and
a sixth resistor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal for providing the detector voltage output;
wherein the detection circuit operates as a current mirror circuit to the bias circuit with temperature compensation which is independently adjustable by the fourth resistor and the fifth resistor.
2. The power detector of claim 1 wherein the detection circuit is further arranged as an emitter follower for enveloping the RF signal.
3. The power detector of claim 1 wherein the bias circuit provides DC compensation to a power amplifier coupled thereto.
4. The power detector of claim 1 wherein a power amplifier is coupled to the bias circuit, the power amplifier including a driver stage providing said RF signal.
5. The power detector of claim 1 wherein the detection power input circuit, the bias circuit, the detection circuit, and a power amplifier are formed on a single integrated circuit.
6. The power detector of claim 4 wherein the detection circuit compensates temperature variation of an inputted detection voltage.
7. The power detector of claim 6 wherein the inputted detection voltage is received from an interstage of a power amplifier.
8. The power detector of claim 4 wherein the power amplifier comprises a driver stage and a power stage.
9. The power detector of claim 1, wherein the emitter of the first bipolar transistor is not directly electrically connected to the emitter of the second bipolar transistor.