Author: claimsbot

1. A method for making a lens barrel having at least one inner cam groove, comprising the steps of:
(a) forming a fusible alloy into a fusible mold core having an outer peripheral surface and at least one flange protruding from the outer peripheral surface;
(b) applying an insulating layer on the outer peripheral surface and the flange of the fusible mold core;
(c) disposing the fusible mold core in a mold cavity of a lens-barrel-forming mold;
(d) feeding a molding material into the mold cavity of the lens-barrel-forming mold so as to form the lens barrel between the lens-barrel-forming mold and the fusible mold core and adhered to the fusible mold core, the lens barrel having an inner surface corresponding to the outer peripheral surface of the fusible mold core and defining an inner hole and the inner cam groove recessed from the inner surface and corresponding to the flange of the fusible mold core;
(e) removing the lens barrel together with the fusible mold core from the mold cavity of the lens-barrel-forming mold; and
(f) fusing the fusible mold core for separating the fusible mold core from the lens barrel.
2. The method as claimed in claim 1, wherein the step (a) is conducted by preparing a mold-core-forming die having a die cavity corresponding to the fusible mold core, and feeding the fusible alloy into the die cavity of the mold-core-forming die so as to form the fusible mold core.
3. The method as claimed in claim 2, further comprising a step of removing the fusible mold core from the mold-core-forming die before the step (b).
4. The method as claimed in claim 3, wherein the molding material is a plastic material, the step (d) being conducted by injection molding.
5. The method as claimed in claim 4, wherein the step (f) is conducted by eddy current induction heating.
6. The method as claimed in claim 5, further comprising a step of cleaning the lens barrel by supersonic cleaning treatment.
7. The method as claimed in claim 1, wherein the fusible alloy includes bismuth, lead, tin, cadmium, and indium.
8. The method as claimed in claim 7, wherein the fusible alloy has a melting temperature not less than 186\xb0 C.
9. The method as claimed in claim 1, wherein the insulating layer is made of a graphite-containing release agent having a refractory temperature not less than 315\xb0 C.
10. The method as claimed in claim 1, wherein the molding material includes polycarbonate and fiber.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of making a micro-wire structure, comprising:
providing a substrate having an edge area and a central area separate from the edge area;
providing first, second, and third different stamps;
providing a curable bottom layer in relation to the substrate;
forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area;
locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area;
providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire;
forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer;
forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire;
providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire;
forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer;
forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire; and
wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.
2. The method of claim 1, wherein the substrate has at least one edge and the edge area is adjacent to the edge.
3. The method of claim 1, wherein the step of forming the imprinted connecting-layer micro-channel further includes contacting the bottom-layer micro-wire with the second stamp.
4. The method of claim 1, wherein the step of forming the imprinted edge micro-channel further includes contacting the connecting-layer micro-wire with the third stamp.
5. The method of claim 1, wherein the bottom and connecting layers include cross-linkable material and further including cross linking the cross-linkable first-layer material to the cross-linkable second-layer material or wherein the connecting and top layers include cross-linkable material and further including cross linking the cross-linkable second-layer material to the cross-linkable third-layer material.
6. The method of claim 1, wherein a portion of the edge micro-wire forms at least a portion of a connection pad.
7. The method of claim 6, wherein the connection pad further includes a plurality of micro-wires.
8. The method of claim 1, further including forming a plurality of edge micro-wires electrically connected through a corresponding plurality of connection micro-wires to a corresponding plurality of bottom-layer micro-wires.
9. The method of claim 8, further including forming a plurality of top-layer micro-wires electrically isolated from the edge micro-wires.
10. The method of claim 1, further including removing a portion of the cured connecting layer or removing a portion of the cured top layer.
11. The method of claim 10, further including removing the portion of the cured second or cured top layer by treating the cured second or cured top layer with a plasma treatment.
12. The method of claim 10, further including thinning the cured second or cured top layer by a thinning depth.
13. The method of claim 12, wherein the thinning depth is less than the difference between the depth of the cured second or cured top layer and the depth of any micro-channels in the corresponding cured second or cured top layer.
14. A method of making a micro-wire structure, comprising:
providing a substrate having an edge area and a central area separate from the edge area;
providing first, second, and third different stamps;
providing a curable bottom layer in relation to the substrate;
forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area;
locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area;
providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire;
forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer;
forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire;
providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire;
forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer;
forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire;
forming a plurality of edge micro-wires electrically connected through a corresponding plurality of connection micro-wires to a corresponding plurality of bottom-layer micro-wires;
forming a plurality of top-layer micro-wires electrically isolated from the edge micro-wires;
wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire; and
wherein the top-layer micro-wires and the bottom-layer micro-wires form a two-dimensional array of overlapping micro-wires.
15. A method of making a micro-wire structure, comprising:
providing a substrate having an edge area and a central area separate from the edge area;
providing first, second, and third different stamps;
providing a curable bottom layer in relation to the substrate;
forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area;
locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area;
providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire;
forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer;
forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire;
providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire;
forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer;
forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire;
forming a plurality of edge micro-wires electrically connected through a corresponding plurality of connection micro-wires to a corresponding plurality of bottom-layer micro-wires;
forming a plurality of top-layer micro-wires electrically isolated from the edge micro-wires;
wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire; and
wherein the substrate has at least first and second edges and at least some of the plurality of edge micro-wires are located in an edge area adjacent to the first edge and at least some of the plurality of top-layer micro-wires extend into a second edge area adjacent to the second edge and separate from the central area.
16. The method of claim 15, wherein the edge micro-wires are in the edge area and the top-layer micro-wires extend into the edge area.
17. The method of claim 16, wherein portions of the top-layer micro-wires are interdigitated between the edge micro-wires in the edge area.
18. A method of making a micro-wire structure, comprising:
providing a substrate having an edge area and a central area separate from the edge area;
providing first, second, and third different stamps;
providing a curable bottom layer in relation to the substrate;
forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area;
locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area;
providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire;
forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer;
forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire;
providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire;
forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer;
forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire;
wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire; and
wherein either:
a) the curable bottom layer includes first curable material and further including locating the first stamp in contact with the first curable material and only partially curing the first curable material, wherein the curable connecting layer includes second curable material and further including locating the second stamp in contact with the second curable material, and at least partially curing both the first curable material and the second curable material in a common step; or
b) the curable connecting layer includes second curable material and further including locating the second stamp in contact with the second curable material and only partially curing the second curable material, wherein the curable top layer includes third curable material and further including locating the third stamp in contact with the third curable material, and at least partially curing both the second curable material and the third curable material in a common step.
19. A method of making a micro-wire structure, comprising:
providing a substrate having an edge area and a central area separate from the edge area;
providing first, second, and third different stamps;
providing a curable bottom layer in relation to the substrate;
forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area;
locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area;
providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire;
forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer;
forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire;
providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire;
forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer;
forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire; and
wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire; and either:
a) depositing first conductive ink in the bottom-layer micro-channel and at least partially curing the first conductive ink, further including depositing second conductive ink in the connecting-layer micro-channel and at least partially curing the first conductive and second conductive ink in a common step; or
b) depositing first conductive ink in the connecting-layer micro-channel and at least partially curing the first conductive ink, further including depositing second conductive ink in the edge micro-channel and at least partially curing the first conductive and second conductive ink in a common step.
20. The method of claim 19, wherein the first and second conductive inks include electrically conductive particles and further including sintering, welding, or agglomerating electrically conductive particles in the second conductive ink to electrically conductive particles in the first conductive ink.

1. A light emitting device comprising:
a submount having first contacts separated by at least one first channel,
a light emitting structure having a metal layer with second contacts separated by at least one second channel, and
one or more elements added to the light emitting structure to reduce a thermally induced stress in the light emitting structure in a vicinity of the second channel,
wherein the one or more elements include one or more gaps in the metal layer, the gaps being situated to distribute the stress beyond the vicinity of the second channel.
2. The light emitting device of claim 1, wherein the one or more elements include a buffer layer between the metal layer and a light emitting element in the light emitting structure, the buffer layer having a higher compliancy than the metal layer.
3. The light emitting device of claim 2, wherein the buffer layer includes gold.
4. (canceled)
5. The light emitting device of claim 1, wherein the one or more elements include a filler material within the second channel, the filler material being selected based on its CTE.
6. The light emitting device of claim 1, wherein the one or more elements include a filler material within the first channel, the filler material being selected based on its CTE.
7. A light emitting device comprising:
a submount having first contacts separated by at least one first channel,
a light emitting structure having a metal layer with second contacts separated by at least one second channel, and
one or more elements added to the light emitting structure to reduce a thermally induced stress in the light emitting structure in a vicinity of the second channel,
wherein the light emitting structure is coupled to the submount by an interconnect material, and
the one or more elements include additional interconnect material in an area adjacent the second channel.
8. The light emitting device of claim 7, wherein the interconnect material includes a plurality of micro bumps.
9. The light emitting device of claim 1, wherein the light emitting structure comprises a flip chip structure.
10. The light emitting device of claim 7, wherein the metal layer comprises an alloy.
11. The light emitting device of claim 10, wherein the alloy includes a copper alloy.
12. The light emitting device of claim 11, wherein the copper alloy includes at least one of: CuNi, CuNiTi, CuW, CuFe, and CuMo.
13. The light emitting device of claim 11, wherein the copper alloy includes CuNiTi.
14. A light emitting device comprising:
a submount having first contacts separated by at least one first channel, and
a light emitting structure having a metal layer with second contacts separated by at least one second channel,
wherein the metal layer includes an alloy having a CTE that is less than a CTE of copper within a temperature range of 20-250\xb0 C.
15. The light emitting device of claim 14, wherein the alloy includes a copper alloy.
16. The light emitting device of claim 15, wherein the copper alloy includes at least one of: CuNi, CuNiTi, CuW, CuFe, and CuMo.
17. The light emitting device of claim 15, wherein the copper alloy includes CuNiTi.
18. The light emitting device of claim 14, wherein the CTE of the alloy is less than 10 ppmK within a temperature range of 20-250\xb0 C.
19. The light emitting device of claim 14, wherein the CTE of the alloy is less than 8 ppmK within a temperature range of 20-250\xb0 C.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a passivation film on a semiconductor substrate comprising forming a first silicon nitride containing layer on said substrate, oxidizing the surface of said first silicon nitride containing layer, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
2. A method as claimed in claim 1, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen-containing gas plasma.
3. A method as claimed in claim 2, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
4. A method as claimed in claim 1, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen containing gas.
5. A method as claimed in claim 1, wherein said first and second silicon nitride containing layers are formed using plasma enhanced chemical vapor deposition.
6. A method as claimed in claim 5, wherein said first and second silicon nitride containing layers are formed by providing a gas mixture comprising N2, SiH4 and, optionally, NH3 and energizing said gas mixture to create a gas plasma and form a silicon nitride containing layer on said semiconductor substrate.
7. A method as claimed in claim 6, wherein the flow rate of N2 is from between about 10 to about 20,000 sccm, the flow rate of SiH4 is from between about 10 to about 1000 sccm,
8. A method as claimed in claim 7, wherein said gas mixture includes NH3, and the flow rate of said NH3 is from between about 0.1 to about 1000 sccm.
9. A method as claimed in claim 6, wherein said energizing step takes place in a PECVD reaction chamber and comprises applying from between about 100 to about 1500 watts of RF power to said PECVD chamber while the chamber is maintained at a pressure of from between about 1 to about 50 Torr, and a temperature of from between about 100\xb0 to about 550\xb0 C.
10. A method as claimed in claim 1, wherein said first silicon nitride containing layer has a thickness of from between about 4000 to about 8000 angstroms, and said second silicon nitride containing layer has a thickness of from between about 4000 to about 8000 angstroms.
11. A method as claimed in claim 1, wherein said semiconductor substrate comprises a DRAM memory device.
12. A method of forming a passivation film on a semiconductor substrate, comprising forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
13. A method as claimed in claim 12, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen-containing gas plasma.
14. A method as claimed in claim 13, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
15. A method of forming a passivation film on a semiconductor substrate, comprising providing a semiconductor substrate in a reaction chamber, forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma in said reaction chamber, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
16. A method as claimed in claim 15, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
17. A method of forming a passivation film on a semiconductor substrate, comprising providing a semiconductor substrate in a reaction chamber, exposing said semiconductor substrate to a first gas plasma comprising N2 and SiH4, forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma in said reaction chamber, exposing said oxidized surface of said first silicon nitride containing layer to a second gas plasma comprising N2 and SiH4, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
18. A method as claimed in claim 17, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
19. A method as claimed in claim 17, wherein said first and second gas plasmas include NH3.
20. A method as claimed in claim 17, wherein said reaction chamber comprises a PECVD chamber.
21. A semiconductor device comprising a substrate and a passivation film on said substrate, wherein said passivation film comprises first and second silicon nitride containing layers and an oxidized interface between said first and second silicon nitride containing layers.
22. A semiconductor device as claimed in claim 21 wherein, said oxidized interface is formed by exposing the surface of said first silicon nitride containing layer to an oxygen-containing plasma.