Author: claimsbot

1. A semiconductor memory device, comprising:
a memory cell array in which electrically programmable memory cells are arranged in a matrix form, the memory cells being connected to word lines;
a first voltage generating circuit which generates a first voltage,
a second voltage generating circuit which generates a second voltage using the first voltage, the second voltage being lower than the first voltage;
a third voltage generating circuit which generates a third voltage;
a word line selecting circuit which selects at least one of the word lines of the memory cells in accordance with an inputted address;
a word line voltage supplying circuit which supplies the second voltage to the selected word line and supplies the third voltage to the non-selected word line through the word line selecting circuit; and
a transfer voltage supplying circuit which supplies the first voltage to the word line selecting circuit and stops supplying the first voltage so as to be in a floating state before transferring the second voltage from the word supplying circuit to the selected word line, in an operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting circuit.
2. The semiconductor memory device as set forth in claim 1, wherein the third voltage is lower than the second voltage.
3. The semiconductor memory device as set forth in claim 1, wherein the third voltage is supplied to at least two of the non-selected word lines, and the third voltage supplied to the non-selected word lines contributes to raise a floating voltage of the floating state in the word line selecting circuit.
4. The semiconductor memory device as set forth in claim 1, wherein the memory cell array is divided into a plurality of blocks;
the word line selecting circuit selects at least one of the blocks; and
the third voltage is supplied to at least two of the non-selected word lines in the selected block.
5. The semiconductor memory device as set forth in claim 1, wherein the operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting circuit is performed in a program operation for programming data in the memory cells.
6. The semiconductor memory device as set forth in claim 5, wherein the second voltage is a program voltage supplied to the selected word line and the third voltage is an intermediate voltage supplied to the non-selected word line in the program operation.
7. The semiconductor memory device as set forth in claim 1, wherein the semiconductor memory device is a nonvolatile memory device.
8. The semiconductor memory device as set forth in claim 7, wherein the memory cell array includes a plurality of NAND-type cells.
9. A semiconductor memory device, comprising:
a memory cell array in which electrically programmable memory cells are arranged in a matrix form, the memory cells being connected to word lines;
a first voltage generating circuit which generates a first voltage;
a second voltage generating circuit which generates a second voltage using the first voltage, the second voltage being lower than the first voltage,
a third voltage generating circuit which generates a third voltage;
a word line selecting circuit which selects at least one of the word lines of the memory cells in accordance with an inputted address;
a word line voltage supplying circuit which supplies the second voltage to the selected word line and supplies the third voltage to the non-selected word line through the word line selecting circuit; and
a transfer voltage supplying circuit which supplies the first voltage in the word line selecting circuit.
10. The semiconductor memory device as set forth in claim 9, wherein the third voltage is lower than the second voltage.
11. The semiconductor memory device as set forth in claim 9, wherein the third voltage is supplied to at least two of the non-selected word lines, and the third voltage supplied to the non-selected word lines contributes to raise a floating voltage of the floating state in the word line selecting circuit.
12. The semiconductor memory device as set forth in claim 9, wherein the memory cell array is divided into a plurality of blocks;
the word line selecting circuit selects at least one of the blocks; and
the third voltage is supplied to at least two of the non-selected word lines in the selected block.
13. The semiconductor memory device as set forth in claim 9, wherein the operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting is performed in a program for programming data in the memory cells.
14. The semiconductor memory device as set forth in claim 13, wherein the second voltage is a program voltage supplied to the selected word line and the third voltage is an intermediate voltage supplied to the non-selected word line in the program operation.
15. The semiconductor memory device as set forth in claim 9, wherein the semiconductor memory device is a nonvolatile semiconductor device.
16. The semiconductor memory device as set forth in claim 15, wherein the memory cell array includes a plurality of NAND-type cells.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a semiconductor substrate including a diffusion area;
a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, the lower electrode being flat;
a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode; and
a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode and not connected to the upper electrode.
2. The semiconductor device according to claim 1, wherein the dummy plug is placed below an area including a periphery and outside of the lower electrode.
3. The semiconductor device according to claim 1, further comprising an insulating film provided between the semiconductor substrate and the capacitor, wherein the plug and the dummy plug are provided in the insulating film, and upper ends of the plug and dummy plug project from a surface of the insulating film.
4. The semiconductor device according to claim 2, further comprising an insulating film provided between the semiconductor substrate and the capacitor, wherein the plug and the dummy plug are provided in the insulating film, and upper ends of the plug and dummy plug project from a surface of the insulating film.
5. The semiconductor device according to claim 3, further comprising metal or its compound which fills an area between the upper ends of the plug and dummy plug projecting from the surface of the insulating film.
6. The semiconductor device according to claim 4, further comprising metal or its compound which fills an area between the upper ends of the plug and dummy plug projecting from the surface of the insulating film.
7. The semiconductor device according to claim 5, wherein the metal or its compound is titanium or titanium nitride.
8. The semiconductor device according to claim 6, wherein the metal or its compound is titanium or titanium nitride.
9. The semiconductor device according to claim 1, wherein the plug and the dummy plug comprise the same material.
10. The semiconductor device according to claim 2, wherein the plug and the dummy plug comprise the same material.
11. The semiconductor device according to claim 9, wherein the plug and dummy plug projecting from the surface of the insulating film comprises a material which is etched at a lower etching rate than the lower electrode.
12. The semiconductor device according to claim 10, wherein the plug and dummy plug projecting from the surface of the insulating film comprise a material which is etched at a lower etching rate than the lower electrode.
13. The semiconductor device according to claim 11, wherein the plug and dummy plug projecting from the surface of the insulating film comprise a material which is etched at a lower etching rate than the lower electrode.
14. The semiconductor device according to claim 3, wherein the plug and dummy plug in the insulating film comprise a semiconductor, and the plug and dummy plug projecting from the surface of the insulating film comprise a compound of the semiconductor and a refractory metal.
15. The semiconductor device according to claim 1, wherein the diffusion area is a sourcedrain area of a MOS transistor.
16. The semiconductor device according to claim 15, wherein the dielectric film is a ferroelectric film, and the MOS transistor and the capacitor are for a ferroelectric random access memory.
17. A method for manufacturing a semiconductor device comprising:
forming an insulating film on a semiconductor substrate including a diffusion area;
forming a connection hole in the insulating film which reaches the diffusion area and forming a trench in a surface of the insulating film;
filling an inside of the connection hole and trench with a semiconductor film;
forming a refractory metal film on the insulating film and semiconductor film;
executing a thermal treatment to allow the semiconductor film and the refractory metal film to react with each other to form a compound film of the semiconductor film and refractory metal film;
removing the refractory metal film and compound film outside the connection hole and trench and forming a plug and a dummy plug each including the semiconductor film and the refractory metal film inside the connection hole and the trench, respectively;
removing an oxide film formed on a surface of the compound film;
burying metal or its compound in a removed area in a surface of the insulating film between the connection hole and the trench which area results from the removal of the oxide film; and
forming a capacitor including a lower electrode, a dielectric film, and an upper electrode on the insulating film, the lower electrode having a lower end being connected to upper ends of the plug and dummy plug.
18. The method for manufacturing a semiconductor device according to claim 17, wherein burying the metal or its compound in the removed area in the surface of the insulating film between the connection hole and the trench which area results from the removal of the oxide film comprises depositing a film containing the metal or its compound and polishing the film containing the metal or its compound.
19. The method for manufacturing a semiconductor device according to claim 17, wherein the insulating film is a silicon oxide film, and removing the oxide film formed on the surface of the compound film is carried out by a treatment using a diluted fluoric acid.
20. The method for manufacturing a semiconductor device according to claim 18, wherein the insulating film is a silicon oxide film, and removing the oxide film formed on the surface of the compound film is carried out by a treatment using a diluted fluoric acid.

1. A method for determining amplitude and phase versus frequency of an incoming beam of pulsed laser light, comprising the steps of:
setting an apparatus to an initial configuration;
splitting the incoming beam into two beams of substantially equal intensity;
delaying one of the two split beams for a delay period t;
recombining the two split beams to form a recombined beam;
shining the recombined beam onto a thick SHG crystal at rotation angle \u03b8;
detecting light emitted from the thick SHG crystal as data;
storing the data with reference to the delay period t and the angle \u03b8;
rotating the thick SHG crystal by an angle \u03b4\u03b8;
repeating the steps of splitting, delaying, recombining, shining, detecting, storing, and rotating until the thick SHG crystal has completed 360\xb0 of rotation;
increasing the delay period t by \u03b4t;
repeating the steps of splitting, delaying, recombining, shining, detecting, storing, rotating, repeating and increasing until a selected beam delay period range has been completed; and
processing the stored data to determine amplitude and phase versus frequency of the incoming beam of pulsed laser light.
2. The method of claim 1, further comprising the steps of:
passing the recombined beam through a half-wave plate at angle \u03c6 prior to the step of shining the recombined beam onto the thick SHG crystal;
storing the data with reference to the delay period t, the angle \u03c6, and the angle \u03b8;
rotating the half-wave plate by angle \u03b4\u03c6; and
repeating the steps of splitting, delaying, recombining, passing, shining, detecting, storing and rotating until the half-wave plate has completed 360\xb0 of rotation.
3. A system for determining amplitude and phase versus frequency of an incoming beam of pulsed laser light, comprising:
a first beam splitter for splitting the incoming beam into first and second beams having substantially equal intensity;
a translation time delay stage for delaying one of the first and second beams;
a second beam splitter for recombining the first and second beams into a combined beam;
a second-harmonic generation crystal mounted in a rotational stage, the second-harmonic generation crystal generating second-harmonic light from the combined beam;
a detector for detecting the second harmonic light as data; and
a controller for (a) controlling the translation time delay stage and the second-harmonic generation crystal rotational stage, (b) recording the data in association with positions of the translation time delay stage and the second-harmonic generation crystal rotational stage, and (c) processing the data and positions to determine the amplitude and phase versus frequency of the incoming beam of pulsed laser light;
wherein the second-harmonic generation crystal rotational stage is controlled to rotate through 360\xb0.
4. The system of claim 3, further comprising:
a half-wave plate mounted in a rotational stage and positioned between the second beam splitter and the second harmonic generation crystal, the half-wave plate polarizing the combined beam before the combined beam enters the second-harmonic generation crystal;
wherein the controller further controls the rotation of the half-wave plate with respect to the rotation of the second-harmonic generation crystal and further records the position of the half-wave plate in association with the data, and processes the data and positions to determine the amplitude and phase versus frequency of the incoming beam of pulsed laser light.
5. A method for determining amplitude and phase versus frequency of an incoming beam of pulsed laser light, comprising:
configuring an apparatus to split the incoming beam into a first and a second beam of substantially equal intensity, to use a translation stage to delay the second beam in comparison to the first beam, to pass the first and second beams though a rotating half-wave plate, to converge the first and second beams onto a rotating thick SHG crystal such that an SHG beam is generated by the crystal, to pass the generated SHG beam through a spatial filter and to capture the filtered SHG beam using a detector;
determining a detector sample rate, a half-wave plate rotational velocity, a thick SHG crystal rotational velocity, and a translational stage velocity;
rotating the half-wave plate at the half-wave plate rotational velocity;
rotating the thick SHG crystal at the thick SHG crystal rotational velocity;
initializing the translational stage and moving the translational stage at the translational stage velocity;
detecting light from the thick SHG crystal as data;
storing the data in a data set with a delay period t defined by a position of the translational stage, an angle \u03c6 based upon a rotational position of the half-wave plate, and an angle \u03b8 based upon a rotational position of the thick SHG crystal;
repeating, at the detector sample rate, the steps of detecting and storing until a set of data is complete; and
processing the data set to determine the amplitude and phase versus frequency of the incoming beam of pulsed laser light.
6. A RotaryFROG apparatus for determining amplitude and phase versus frequency of an incoming beam of pulsed laser light, comprising:
a first beam splitter for splitting the incoming beam into first and second beams having substantially equal intensity;
a translation time delay stage for delaying one of the first and second beams;
a second beam splitter for recombining the first and second beams into a combined beam;
a half-wave plate mounted in a rotational stage and rotating at a half-wave plate rotational velocity, the half-wave plate controlling an orientation of the polarized light of the combined beam;
a second-harmonic generation crystal mounted in a rotational stage and rotating at a constant SHG crystal rotational velocity, the second-harmonic crystal generating second-harmonic light from the combined beam;
a detector for detecting the second-harmonic light as data; and
a processor for controlling rotational positions of the half-wave plate and the second-harmonic generation crystal and for storing the data in association with rotational positions of the half-wave plate and the second-harmonic generation crystal;
wherein the processor processes the data and the rotational positions to determine the amplitude and phase versus frequency of the incoming beam of pulsed laser light.
7. A RotaryFROG apparatus for determining amplitude and phase versus frequency of an incoming beam of pulsed laser light, comprising:
optical geometry for splitting the incoming beam into first and second beams having substantially equal intensity, for delaying one of the first and second beams, and for recombining the first and second beams into a combined beam;
a half-wave plate mounted in a rotational stage and rotating at a half-wave plate rotational velocity, the half-wave plate controlling an orientation of the polarized light of the combined beam;
a second-harmonic generation crystal mounted in a rotational stage and rotating at a constant SHG crystal rotational velocity, the second-harmonic crystal generating second-harmonic light from the combined beam;
a detector for detecting the second-harmonic light as data; and
a processor for controlling rotational positions of the half-wave plate and the second-harmonic generation crystal and for storing the data in association with rotational positions of the half-wave plate and the second-harmonic generation crystal;
wherein the processor processes the data and the rotational positions to determine the amplitude and phase versus frequency of the incoming beam of pulsed laser light.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Apparatus for guiding a tensioning wire, in particular at transitions between segments of a pylon of prestressed concrete finished parts, characterised in that the apparatus (8) is of a funnel-shaped configuration, wherein the side of the apparatus (8) of the smaller cross-section (11) is of substantially the same cross-section as jacket tubes (7) incorporated into the segments (4, 6).
2. Apparatus as set forth in claim 1 characterised in that the apparatus (8) has a predetermined flare angle.
3. Apparatus as set forth in claim 2 characterised in that the flare angle of the apparatus (8) is in a range of between 10 and 150.
4. Apparatus as set forth in one of the preceding claims characterised in that the side of the apparatus (8) of the larger cross-section (9) is of external dimensions which are smaller than the wall thickness of a segment (4, 6).
5. Apparatus as set forth in one of the preceding claims characterised in that adjoining the side of the apparatus (8) of the smaller cross-section (11) in the through direction thereof is a tubular portion (12) of substantially the same cross-section.
6. Apparatus as set forth in claim 5 characterised in that the apparatus (8) and the tubular portion (12) are made in one piece.
7. Apparatus as set forth in one of claims 5 and 6 characterised in that the tubular portion (12) is of a predetermined length.
8. Apparatus as set forth in claim 7 characterised in that the length of the tubular portion (12) is at least 20 mm.
9. Apparatus as set forth in one of claims 5 to 8 characterised in that the tubular portion (12) is provided with a male screwthread (14).
10. Apparatus as set forth in one of the preceding claims characterised in that the outer periphery of the opening of the larger cross-section (9) is at least partially surrounded by a support surface (16) extending at a predetermined angle relative thereto.
11. Apparatus as set forth in claim 10 characterised in that provided at the outer edge of the support surface (16) is a substantially upwardly extending edge portion (18) of a predetermined height.
12. A seal for providing a pressure-tight transition between two mutually superposed prestressed concrete finished elements, characterised in that the seal (20) is of a height which corresponds at least to the intended spacing (30) between the mutually superposed segments (4, 6).
13. A seal as set forth in claim 12 characterised in that the seal (20) is of substantially the same cross-sectional shape as the apparatus (8).
14. A seal as set forth in claim 12 or claim 13 characterised in that the internal width (21) of the seal (20) changes in the axial direction.
15. A seal as set forth in one of claims 12 to 14 characterised in that the internal width (21) increases towards the prestressed concrete finished element (4, 6) which is arranged beneath the seal (20).
16. A seal as set forth in one of claims 12 to 15 characterised in that the wall thickness of the seal material does not exceed a predetermined dimension.
17. A seal as set forth in claim 16 characterised in that the wall thickness of the seal material varies along the height of the seal (20).
18. A seal as set forth in claim 16 or claim 17 characterised in that the transition (29) between an outer wall (26) and an inner wall (27) of the upper portion (25) of the seal (20) extends at an acute angle relative to the outer wall (26) and an obtuse angle relative to the inner wall (27) of the seal (20).
19. A seal as set forth in one of claims 12 to 18 characterised in that the opening cross-section of the seal (20), which faces towards the prestressed concrete finished element (4, 6) disposed above the seal (20), is at least of the same size as one of the jacket tubes (7) incorporated into the wall of the prestressed concrete elements (4, 6).
20. A seal as set forth in one of claims 12 to 19 characterised in that a bead (22) is formed thereon at the side of the seal (20) of the larger internal width.
21. A seal as set forth in claim 20 characterised in that the cross-sectional shape and dimensions of the bead (22) substantially correspond to the cross-sectional shape formed by the outer peripheral edge (10) of the opening of the larger cross-section (9) of the apparatus (8), the support surface (16) and the edge portion (18) surrounding the support surface, and substantially correspond to the dimensions thereof.
22. A seal as set forth in one of claims 12 to 21 characterised in that the outer peripheral edge of the seal (20) above the bead (22) has an outwardly directed cantilever portion (23) of a predetermined height and width.
23. A seal as set forth in claim 22 characterised in that the cantilever portion (23) is of a substantially parallelogram-shaped configuration.
24. A prestressed concrete finished part (segment) with one or more jacket tubes integrated into the wall thereof, characterised in that the apparatus (8) as set forth in one of claims 1 to 9 is integrated into the segment in such a way that the side of the apparatus (8) of the smaller cross-section (11) faces towards the jacket tube (7) which is integrated into the wall and the side of the larger cross-section (9) faces towards the edge of the segment (4, 6), which faces upwardly when the pylon is erected.
25. A segment as set forth in claim 24 characterised in that the side of the apparatus (8) of the larger cross-section (9) terminates substantially flush with the surface of the segment (4, 6), which faces upwardly when the pylon is erected.
26. A segment as set forth in claim 24 or claim 25 characterised in that the segment (4, 6) is divided parallel to the vertical axis into at least two separate segments.
27. A method of erecting a pylon from segments, wherein before the segments (4, 6) are brought together a joining material (34) is applied to the upwardly facing surface (36) of the respectively lower segment (6), characterised in that the material (34) is a polymer.
28. A method as set forth in claim 27 characterised in that the layer thickness of the joining material (34) substantially corresponds to the predetermined spacing (30) between the mutually superposed segments (4, 6).
29. A method as set forth in one of claims 27 and 28 characterised in that the layer thickness of the joining material (34) is at least 2 mm.
30. A method as set forth in one of claims 27 to 29 characterised in that the joining material (34) hardens in the air.
31. A method as set forth in one of claims 27 to 30 characterised in that the joining material (34) is applied over the full surface area.
32. A method as set forth in one of claims 27 to 31 characterised in that the openings of the jacket tubes (7) which are incorporated into the segments (4, 6) and the apparatuses (8) are cleared out when the material (34) is applied.
33. A method as set forth in one of claims 27 to 32 characterised in that at least three spacers (32) are inserted between the segments (4, 6).
34. A method as set forth in claim 33 characterised in that the spacers (32) are of a material thickness which substantially corresponds to the predetermined spacing (30) between the segments (4, 6).
35. A method as set forth in one of claims 33 and 34 characterised in that the spacers (32) have a predetermined modulus of elasticity.
36. A method as set forth in one of claims 33 to 35 characterised in that the modulus of elasticity of the spacers (32) used is lower than the modulus of elasticity of the hardened joining material (34).
37. A method as set forth in one of claims 33 to 36 characterised in that the spacers (32) are of wood.
38. A pylon of a wind power installation comprising a plurality of mutually superposed finished parts which are braced together by means of tensioning elements, wherein each finished part substantially comprises a ring element.
39. A pylon as set forth in claim 38 characterised in that each ring element comprises at least two sub-segments, wherein a sub-segment spans a sub-ring element.
40. A pylon as set forth in claim 38 and claim 39 characterised in that the tensioning elements are at least one cable-like tensioning element for bracing the segments, which are passed through a cavity within the wall of the ring elements.
41. A pylon as set forth in one of the preceding claims characterised in that the cavity is filled with a building material, preferably concrete, after the pylon of the wind power installation has been set up.
42. A pylon as set forth in one of the preceding claims characterised in that an element for receiving the tensioning steel element is provided in the transition from a lower concrete finished part to a concrete finished part resting thereon, wherein the receiving part is of a larger diameter in its upper edge than at its lower edge.
43. A pylon of a wind power installation wherein the pylon tapers from the ground upwardly, characterised in that the pylon has a curved pylon profile.
44. A pylon as set forth in claim 43 characterised in that the pylon comprises a plurality of finished elements which in turn are of a curved contour or a linear contour.