Author: claimsbot

What is claimed is:

1. A method for the prevention or treatment of retinopathy which comprises administering to a mammal in need of such prevention or treatment an amount of a carbonic anhydrase inhibitor sufficient to prevent or treat retinopathy.
2. A method according to claim 1, wherein the retinopathy comprises diabetic retinopathy.
3. A method according to claim 2, wherein the diabetic retinopathy comprises non-proliferative diabetic retinopathy.
4. A method according to claim 2, wherein the diabetic retinopathy comprises diabetic macular edema.
5. A method according to claim 2, wherein the diabetic retinopathy comprises preproliferative or proliferative diabetic retinopathy.
6. A method according to claim 2 for the prevention of diabetic retinopathy in a diabetic not suffering from diabetic retinopathy which comprises administering to said diabetic an amount of a carbonic anhydrase inhibitor sufficient to prevent diabetic retinopathy.
7. A method according to claim 1, wherein the retinopathy comprises a vascular retinopathy.
8. A method according to claim 7, wherein the vascular retinopathy comprises branch retinal vein occlusion.
9. A method according to claim 7, wherein the vascular retinopathy comprises central retinal vein occlusion.
10. A method according to claim 7, wherein the vascular retinopathy comprises sickle cell retinopathy.
11. A method according to claim 7, wherein the vascular retinopathy comprises capillary occlusion or ischemia.
12. A method according to claim 1, wherein the carbonic anhydrase inhibitor is administered ophthalmically to the eye or eyes.
13. A method according to claim 1, wherein the carbonic anhydrase inhibitor is administered systemically.
14. A method according to claim 13, wherein the carbonic anhydrase inhibitor is administered orally.
15. A method according to claim 13, wherein the carbonic anhydrase inhibitor is administered parenterally.
16. A method according to claim 1, wherein the carbonic anhydrase inhibitor is dorzolamide.
17. A method according to claim 1, wherein the carbonic anhydrase inhibitor is acetazolamide.
18. A method according to claim 1, wherein the carbonic anhydrase inhibitor is brinzolamide.
19. A method according to claim 1, wherein the carbonic anhydrase inhibitor is methazolamide.
20. A method according to claim 1, wherein the carbonic anhydrase inhibitor is ethoxzolamide.
21. A method according to claim 1, wherein the carbonic anhydrase inhibitor is butazolamide.
22. A method according to claim 1, wherein the carbonic anhydrase inhibitor is dichlorphenamide.
23. A method according to claim 1, wherein the carbonic anhydrase inhibitor is flumethiazide.
24. A method according to claim 12, wherein the carbonic anhydrase inhibitor is dorzolamide, acetazolamide, methazolamide, ethoxyzolamide or brinzolamide.
25. A method according to claim 14, wherein the carbonic anhydrase inhibitor is dorzolamide, acetazolamide, methazolamide, ethoxyzolamide or brinzolamide.
26. A method according to claim 15, wherein the carbonic anhydrase inhibitor is dorzolamide or brinzolamide.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An AGC circuit in a direct conversion receiver for multiplying a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifying the baseband signal using a baseband variable gain amplifying circuit having a variable gain amplifier, low-pass filter and a high-pass filter for cutting off a DC component as structural elements, and performing AD conversion and demodulation on the resultant, the AGC circuit comprising:
a power measuring section that measures reception power based on a signal subjected to AD conversion;
a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;
a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;
a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and
a gain variation amount detecting section that reports to the filter control section upon detecting that the gain of the variable gain amplifier varies by an amount equal to or greater than a predetermined amount as a result of control by the gain control section, wherein:
the filter control section switches the cut-off frequency of the high-pass filter to a high frequency upon receiving the report from the gain variation amount detecting section; and
the gain calculating section and the gain control section perform at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.
2. The AGC circuit in the direct conversion receiver according to claim 1, wherein:
the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again; and
the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.
3. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 1.
4. An AGC circuit in a direct conversion receiver for multiplying a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifying the baseband signal using a baseband variable gain amplifying circuit having a variable gain amplifier, low-pass filter and a high-pass filter for cutting off a DC component as structural elements, and performing AD conversion and demodulation on the resultant, the AGC circuit comprising:
a power measuring section that measures reception power based on a signal subjected to AD conversion;
a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;
a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;
a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and
a determining section that determines whether or not there is a high possibility of increasing a DC offset of a signal passed through the high-pass filter, based on information contained in a demodulated signal, or based on an operation state of the direct conversion receiver, and reports the determination result to the filter control section, wherein:
the filter control section switches the cut-off frequency of the high-pass filter to the high frequency upon receiving the report from the determining section; and
the gain calculating section and the gain control section perform at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.
5. The AGC circuit in the direct conversion receiver according to claim 4, wherein:
the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again; and
the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.
6. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 4.
7. A baseband variable gain amplifying circuit that is provided in a direct conversion receiver and that amplifies a baseband signal, comprising:
a variable gain amplifier that amplifies the baseband signal;
a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;
a gain variation amount detecting section that detects an amount of gain variation at which the variable gain amplifier is set equal to or greater than a predetermined amount;
a filter control section that switches the cut-off frequency of the high-pass filter to a high frequency when the gain variation amount detecting section detects that the amount of gain variation is equal to or greater than the predetermined amount; and
a gain control section that performs at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.
8. A baseband variable gain amplifying circuit that is provided in a direct conversion receiver and that amplifies a baseband signal, comprising:
a variable gain amplifier that amplifies the baseband signal;
a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;
a DA converter that converts data of a gain at which the variable gain amplifier is set and digital data including data for instructing switching of the cut-off frequency of the high-pass filter into an analog signal;
a filter control section that switches the cut-off frequency of the high-pass filter based on a signal corresponding to the data for instructing switching of the cut-off frequency; and
a gain control section that performs at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.

1. A semiconductor structure comprising:
a substrate;
a gate, the gate disposed on the substrate;
at least one source, the at least one source disposed on the substrate adjacent to the gate;
at least one drain, the at least one drain disposed on the substrate adjacent to the gate;
wherein an abrupt junction is formed at the intersection of the gate and at least one of the sources or drains.
2. The semiconductor structure of claim 1, wherein the semiconductor structure comprises one source and one drain.
3. The semiconductor structure of claim 2, wherein the source is a raised source, and wherein the drain is a raised drain.
4. The semiconductor structure of claim 2, wherein an abrupt junction is formed at the intersection of the gate and the source.
5. The semiconductor structure of claim 2, wherein an abrupt junction is formed at the intersection of the gate and the drain.
6. The semiconductor structure of claim 1, wherein the substrate comprises:
a layer of silicon;
a layer of buried oxide, the layer of buried oxide disposed on the layer of silicon; and
an ETSOI layer, the ETSOI layer disposed on the layer of buried oxide.
7. The semiconductor structure of claim 6, wherein the ETSOI layer has a thickness ranging from about 2 nanometers to about 10 nanometers.
8. The semiconductor structure of claim 1, wherein the abrupt junction is less than 3 nanometers per decade.
9. The semiconductor structure of claim 1, wherein the semiconductor structure comprises at least three sources and at least three drains.
10. The semiconductor structure of claim 3, further comprising a first silicide region disposed on the source, a second silicide region disposed on the gate, and a third silicide region disposed on the drain.
11. A method of fabricating a transistor, the transistor comprising a gate, at least one source, and at least one drain, comprising:
performing an abrupt junction implant;
performing an anneal;
forming a plurality of silicide regions, wherein a silicide region is formed on the gate, and on each source, and on each drain.
12. The method of claim 11, wherein the step of performing an abrupt junction implant is performed at an angle ranging from about 5 degrees to about 45 degrees deviation from vertical.
13. The method of claim 11, wherein the step of performing an anneal comprises performing a spike anneal at a temperature ranging from about 900 degrees centigrade to about 1100 degrees centigrade.
14. The method of claim 11, wherein the step of performing an abrupt junction implant is performed using an element selected from the group consisting of Xenon, Germanium, Fluorine, Nitrogen, Silicon, and Carbon.
15. The method of claim 11, wherein the step of performing an abrupt junction implant is applied asymmetrically, wherein each source has an abrupt junction implant applied thereto, and wherein each drain does not have an abrupt junction implant applied thereto.
16. The method of claim 11, wherein the step of performing an abrupt junction implant is applied asymmetrically, wherein each drain has an abrupt junction implant applied thereto, and wherein each source does not have an abrupt junction implant applied thereto.
17. An integrated circuit, the integrated circuit comprising:
a first transistor;
a second transistor;
wherein the first transistor and second transistor have substantially the same physical dimensions, and wherein first transistor has a first effective channel length, and the second transistor has a second effective channel length, wherein the first effective channel length is less than the second effective channel length and wherein the second transistor comprises at least one abrupt junction.
18. The integrated circuit of claim 17, wherein the first effective channel length is at least 2 nanometers less than the second effective channel length.
19. The integrated circuit of claim 18, wherein the first transistor comprises an asymmetric abrupt junction, and wherein the second transistor comprises symmetric abrupt junctions.
20. The integrated circuit of claim 19, further comprising a third transistor, wherein the third transistor is a non-AJI transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A component-containing module, comprising:
a substrate configured from a flat section and a projecting section; and
an electronic component mounted on each of the flat section and the projecting section, wherein the electronic component mounted on the flat section is sealed in a resin, and the electronic component mounted on the projecting section has an upper part thereof exposed on a surface of the resin.
2. The component-containing module of claim 1, wherein a height of the upper part of the electric component mounted on the projecting section is higher than a height of the upper part of the electric component mounted on the flat section.
3. The component-containing module of claim 1, wherein the projecting section includes a trapezoid-shaped cross-section and includes a sloop part and a top face part, and the electric component exposed on the surface of the resin is placed on the top face part.
4. The component-containing module of claim 1, wherein a face opposite to a face of the substrate on which the electric component is mounted includes a recess corresponding to the projecting section, and a back resin is placed in the recess.
5. The component-containing module of claim 4, wherein the back resin includes higher stiffness compared with the resin sealing the electric component.
6. The component-containing module of claim 4, wherein on the face opposite to the face of the substrate on which the electric component is mounted, the back resin is placed to flatten the recess.
7. The component-containing module of claim 3, wherein the rising angle of the slope part relative to the flat section is 60 degrees or less.
8. The component-containing module of claim 1, wherein the electric component mounted on the projecting section is a fingerprint sensor, a temperature sensor, or a humidity sensor.
9. The component-containing module of claim 1, wherein a material of the resin is an acrylic resin, an ABS resin, a polycarbonate resin, an epoxy resin, a urethane resin, and a silicon resin.
10. A method for producing a component-containing module, comprising:
mounting a plurality of electric components on a substrate;
forming a projecting section in a direction away from a face of the substrate on which the electric components are placed;
placing a resin to seal the electric component mounted on a flat section of the substrate and expose an upper part of the electric component mounted on the projecting section.