1. A semiconductor device with an increased effective gate length or an increased effective channel width, comprising:
an active area on a substrate;
an oxide isolation structure in the substrate, wherein the oxide isolation structure surrounds the active area;
a gate across the active area and the oxide isolation structure, wherein the oxide isolation structure below the gate has a top surface lower than a top surface of the active area by a depth;
a gate dielectric layer disposed between the gate and the substrate; and
a source and a drain respectively located in the exposed active area on two sides of the gate.
2. The semiconductor device of claim 1, wherein the oxide isolation structure comprises a shallow trench isolation structure or a field oxide isolation structure.
3. The semiconductor device of claim 1, wherein the gate dielectric layer is made from a high-k dielectric material selected from a group consisting of hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, and any combinations thereof.
4. The semiconductor device of claim 1, wherein the gate is made from a metal selected from a group consisting of Al, W, Ta, TaN, TiN, or any combinations thereof.
5. An integrated circuit (IC) structure having devices with various effective gate lengths or various effective channel widths, the integrated circuit structure comprising:
a first active area and a second active area on a substrate;
a first oxide isolation structure and a second oxide isolation structure in the substrate, wherein the first and the second oxide isolation structures respectively surround the first and the second active areas;
a first gate across the first active area, and a second gate across the second active area, wherein the second oxide isolation structure below the second gate has a top surface lower than a top surface of the second active area by a depth;
a first gate dielectric layer disposed between the first gate and the substrate, and a second gate dielectric layer disposed between the second gate and the substrate; and
a first source and a first drain respectively located in the exposed first active area on two sides of the first gate, and a second source and a second drain respectively located in the exposed second active area on two sides of the second gate.
6. The IC structure of claim 5, wherein the first oxide isolation structure and the second oxide isolation structure comprise a shallow trench isolation structure or a field oxide isolation structure.
7. The IC structure of claim 5, wherein the first and the second gate dielectric layers are made from a high-k dielectric material.
8. The IC structure of claim 5, wherein the gate comprises a metal gate.
9. The IC structure of claim 7, further comprising spacers disposed on sidewalls of the first and the second gates.
10. The IC structure of claim 9, further comprising an etching stop layer disposed on the first and the second gates, the spacers, the first and the second active areas, and the first and the second oxide isolation structures.
11. The IC structure of claim 10, further comprising a dielectric layer disposed on the etching stop layer.
12. A method of adjusting effective gate length of a semiconductor device, the method comprising:
forming a first dummy semiconductor device and a second dummy semiconductor device respectively on a first area and a second area of a substrate;
sequentially forming an etching stop layer and a dielectric layer on the first and the second semiconductor devices and the substrate;
exposing top surfaces of a first dummy gate of the first dummy semiconductor device and a second dummy gate of the second dummy semiconductor device by removing the etching stop layer and the dielectric layer above the top surfaces of the first dummy gate and the second dummy gate;
removing the first dummy gate and the second dummy gate, as well as a first dummy gate oxide layer under the first dummy gate and a second dummy gate oxide layer under the second dummy gate to form a first gate opening and a second gate opening;
lowering a top surface of an oxide isolation structure exposed by the second gate opening by selectively etching the oxide isolation structure exposed by the second gate opening;
forming a first and a second gate dielectric layers respectively in the first and the second gate openings; and
forming a first and a second metal gates respectively on the first and the second gate dielectric layers, whereby the second metal gate has a longer effective gate length than the first gate has.
13. The method of claim 12, wherein the oxide isolation structure exposed by the second gate opening is selectively etched by a method comprising:
forming a photoresist layer on the substrate;
patterning the photoresist layer to expose the second area; and
etching the oxide isolation structure exposed by the second gate opening in the second area.
14. The method of claim 12, wherein the etching stop layer is a silicon oxynitride layer or a silicon nitride layer.
15. The method of claim 12, wherein the dielectric layer comprises a low-k dielectric layer.
16. The method of claim 12, wherein the top surfaces of the first dummy gate and the second dummy gate are exposed by performing a process of blanket etching or chemical mechanical polishing.
17. The method of claim 12, wherein the first dummy gate, the second dummy gate, the first dummy gate oxide layer, and the second dummy gate oxide layer are removed by wet etching or dry etching.
18. The method of claim 12, wherein the first and the second gate dielectric layers comprises a high-k dielectric layer.
19. The method of claim 18, wherein the high-k dielectric layer are formed by metal organic chemical vapor deposition, or molecular beam epitaxial deposition.
20. The method of claim 12, wherein the first and the second metal gates are formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A heating device comprising a ceramic element, wherein the ceramic element comprises a tip on a first end; a base on a second end opposite of the first end; and an outer surface extending from the tip to the base and defining a non-planar three-dimensional shape; and an opening proximate to the base, the opening terminating within the ceramic element defining a hollow inner surface of the ceramic element.
2. The heating device of claim 1, wherein the ceramic element is a positive temperature coefficient ceramic.
3. The heating device of claim 1, further comprising a housing shaped to conform with the outer surface of the ceramic element.
4. The heating device of claim 1, further comprising a protective coating on the outer surface of the ceramic element to protect the ceramic element from abrasion.
5. The heating device of claim 1, wherein the outer surface of the ceramic element is a generally conical shape.
6. The heating device of claim 1, further comprising a conductive coating sputtered onto the ceramic element.
7. The heating device of claim 6, wherein the conductive coating comprises titanium.
8. The heating device of claim 7, wherein the conductive coating further comprises silver and a nickel-vanadium alloy.
9. The heating device of claim 1, further comprising a first electrode and second electrode attached to the ceramic element.
10. The heating device of claim 9, wherein the first electrode is attached to the outer surface of the ceramic element and the second electrode is attached to the hollow inner surface of the ceramic element.
11. The heating device of claim 10, wherein the first electrode and the second electrode are soldered connections.
12. The heating device of claim 1, wherein the ceramic element is proximate to a surface of a sensor.
13. The heating device of claim 12, wherein the sensor is a pitot tube air speed sensor.
14. The heating device of claim 12, wherein the sensor is an angle of attack sensor.
15. The heating device of claim 1, wherein the outer surface of the ceramic element comprises: a length in a first plane having an axis parallel to the first plane; and a diameter in a second plane having an axis orthogonal to the first plane, wherein the diameter varies along the length from the tip to the base.
16. A heating device comprising: a ceramic element, wherein the ceramic element comprises a tip on a first end, a base on a second end opposite of the first end, and an outer surface extending from the tip to the base and defining a non-planar three-dimensional shape; an opening proximate to the base, the opening terminating within the ceramic element defining a hollow inner surface of the ceramic element; a first electrode attached to the outer surface of the ceramic element; a second electrode attached to the hollow inner surface of the ceramic element; and a sensor disposed proximate to the outer surface of the ceramic element.
17. The heating device of claim 16, further comprising a housing shaped to conform with the shape of the outer surface of the ceramic element.
18. The heating device of claim 16, further comprising a protective coating on the outer surface to protect the ceramic element from abrasion.
19. The heating device of claim 16, wherein the ceramic element is a positive temperature coefficient ceramic.