Author: claimsbot

1. A memory device, comprising:
a first terminal structure;
a second terminal structure; and
a re-writeable non-volatile two-terminal memory element directly electrically in series with the first and second terminal structures and operative to store at least one-bit of data as a plurality of conductivity profiles that are retained in the absence of electrical power, the memory element including
a tunnel barrier layer in contact with the first terminal structure and including a first thickness, and
a conductive binary oxide material including mobile oxygen ions and having a form AXOY, where O represents oxygen and A represents a metal, the conductive binary oxide material is in contact with the tunnel barrier layer and with the second terminal structure.
2. The memory device of claim 1, wherein the conductive binary oxide material comprises tin oxide.
3. The memory device of claim 1, wherein the conductive binary oxide material comprises zinc oxide.
4. The memory device of claim 1, wherein the conductive binary oxide material comprises a doped titanium oxide.
5. The memory device of claim 4, wherein the titanium oxide is doped with niobium.
6. The memory device of claim 1, wherein the tunnel barrier layer includes vacancies operative to reversibly receive a portion of the mobile oxygen ions in response to a write voltage applied across the first and second terminal structures.
7. The memory device of claim 6, wherein the tunnel barrier layer is an electrolyte to the mobile oxygen ions and is permeable to the mobile oxygen ions when the write voltage is applied.
8. The memory device of claim 1, wherein the first thickness is approximately 35 \u212b or less.
9. The memory device of claim 1, wherein the tunnel barrier layer comprises a material selected from the group consisting of a rare earth oxide, a rare earth metal oxide, yttria stabilized zirconia (YSZ), zirconium oxide, yttrium oxide, hafnium oxide, gadolinium oxide, and erbium oxide.
10. The memory device of claim 1, wherein the conductive binary oxide material includes a structure selected from the group consisting of an amorphous structure, a single crystalline structure, a polycrystalline structure, a multi-phase crystalline structure, a mixed-phase crystalline structure, a columnar crystalline structure, and a micro-crystalline structure.
11. The memory device of claim 1 and further comprising:
a non-ohmic device electrically in series with the memory element and with the first and second terminal structures.
12. The memory device of claim 1, wherein the first terminal structure is electrically coupled with only one of a plurality of first conductive array lines in a two-terminal cross-point memory array and the second terminal structure is electrically coupled with only one of a plurality of second conductive array lines in the two-terminal cross-point memory array.
13. The memory device of claim 12, wherein the two-terminal cross-point memory array is connected with and is positioned above a substrate including active circuitry electrically coupled with the plurality of first and second conductive array lines and operative to perform data operation on the two-terminal cross-point memory array.
14. The memory device of claim 1, wherein the first thickness is configured for electron tunneling when a voltage for data operations is applied across the first and second terminal structures.
15. The memory device of claim 1, wherein the conductive binary oxide material is doped.
16. The memory device of claim 1, wherein the tunnel barrier layer, the conductive binary oxide material or both are deposited in whole or in part using atomic layer deposition (ALD).
17. A memory device, comprising:
a first terminal structure;
a second terminal structure; and
a re-writeable non-volatile two-terminal memory element directly electrically in series with the first and second terminal structures and operative to store at least one-bit of data as a plurality of conductivity profiles that are retained in the absence of electrical power, the memory element including
a tunnel barrier layer in contact with the first terminal structure and including a first thickness, and
a conductive metal oxide (CMO) including mobile oxygen ions and made from a Ruddlesden-Popper material, the CMO is in contact with the tunnel barrier layer and with the second terminal structure.
18. The memory device of claim 17, wherein the Ruddlesden-Popper material includes a form ABO3, where O represents oxygen, A represents an alkaline earth metal element, and B represents a transition metal element.
19. The memory device of claim 17, wherein the Ruddlesden-Popper material includes a form AO(ABO3)n, where O represents oxygen, A represents at least one alkaline earth metal element, B represents at least one transition metal element, and n represents a Ruddlesden-Popper phase.
20. The memory device of claim 17, wherein the tunnel barrier layer comprises a material selected from the group consisting of a rare earth oxide, a rare earth metal oxide, yttria stabilized zirconia (YSZ), zirconium oxide, yttrium oxide, hafnium oxide, gadolinium oxide, and erbium oxide.
21. The memory device of claim 17 and further comprising:
a non-ohmic device electrically in series with the memory element and with the first and second terminal structures.
22. The memory device of claim 17, wherein the Ruddlesden-Popper material includes a structure selected from the group consisting of an amorphous structure, a single crystalline structure, a polycrystalline structure, a multi-phase crystalline structure, a mixed-phase crystalline structure, a columnar crystalline structure, and a micro-crystalline structure.
23. The memory device of claim 17, wherein the tunnel barrier layer, the Ruddlesden-Popper material or both are deposited in whole or in part using atomic layer deposition (ALD).
24. The memory device of claim 17, wherein the first thickness is configured for electron tunneling when a voltage for data operations is applied across the first and second terminal structures.
25. A memory device, comprising:
a first terminal structure;
a second terminal structure; and
a re-writeable non-volatile two-terminal memory element directly electrically in series with the first and second terminal structures and operative to store at least one-bit of data as a plurality of conductivity profiles that are retained in the absence of electrical power, the memory element including
a tunnel barrier layer in contact with the first terminal structure and including a first thickness, and
a conductive metal oxide (CMO) including mobile oxygen ions and made from a multiple B-site perovskite material including a plurality of perovskite unit cells, the CMO is in contact with the tunnel barrier layer and with the second terminal structure,
the multiple B-site perovskite material includes a form AX(B1,B2)YOZ, where AX represents one or more elements selected from the group consisting of lanthanum, cerium, praseodymium, neodymium, calcium, strontium, and barium that are positioned at A-sites in the plurality of perovskite unit cells, B1 represents a first transition metal element positioned at B-sites in a first portion of the plurality of perovskite unit cells, B2 represents a second transition metal element positioned at B-sites in a second portion of the plurality of perovskite unit cells, the second transition metal element is different than the first transition metal element, where O represents oxygen, where X can be any number, where Y is typically 1, and where Z is typically 3.
26. The memory device of claim 25, wherein the tunnel barrier layer comprises a material selected from the group consisting of a rare earth oxide, a rare earth metal oxide, yttria stabilized zirconia (YSZ), zirconium oxide, yttrium oxide, hafnium oxide, gadolinium oxide, and erbium oxide.
27. The memory device of claim 25 and further comprising:
a non-ohmic device electrically in series with the memory element and with the first and second terminal structures.
28. The memory device of claim 25, wherein the multiple B-site perovskite material includes a structure selected from the group consisting of an amorphous structure, a single crystalline structure, a polycrystalline structure, a multi-phase crystalline structure, a mixed-phase crystalline structure, a columnar crystalline structure, and a micro-crystalline structure.
29. The memory device of claim 25, wherein the tunnel barrier layer, the multiple B-site perovskite material or both are deposited in whole or in part using atomic layer deposition (ALD).
30. The memory device of claim 25, wherein the first thickness is configured for electron tunneling when a voltage for data operations is applied across the first and second terminal structures.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising an element that comprises:
a semiconductor layer;
an insulating film which is provided above said semiconductor layer;
a conductor film which is provided above said insulating film, and which contains p-type impurities; and
a first nitrogen-containing region which is provided in at least part of an upper surface portion and a side surface portion of said conductor film, and which contains nitrogen.
2. The semiconductor device of claim 1,
wherein a second nitrogen-containing region, which is a nitrogen-containing conductor film, is interposed between said insulating film and said conductor film.
3. The semiconductor device of claim 1,
wherein said first nitrogen-containing region is provided within a range at a depth of equal to or more than 10 nm from an upper surface or a side surface of said conductor film.
4. The semiconductor device of claim 1,
wherein a sidewall is provided on a side surface of said conductor film,
a first impurity diffused layer that contains the p-type impurities is provided in a portion of said semiconductor layer which portion is located sideways of said conductor film, and
a second impurity diffused layer that contains the p-type impurities higher in concentration than the p-type impurities of said first impurity diffused layer is provided in a portion of said semiconductor layer which portion is located sideways of said sidewall.
5. The semiconductor device of claim 1,
wherein a third nitrogen-containing region that contains the nitrogen is provided above said second impurity diffused layer.
6. The semiconductor device of claim 1,
wherein an oxynitride film is provided on at least part of a side surface and an upper surface of said conductor film.
7. The semiconductor device of claim 1,
wherein said p-type impurities are boron.
8. The semiconductor device of claim 1,
wherein a peak concentration of the nitrogen contained in said element is equal to or higher than 5 atoms % and equal to or lower than 20 atoms %.
9. The semiconductor device of claim 1,
wherein said conductor film consists of one of polysilicon, amorphous silicon, germanium-containing polysilicon, and germanium-containing amorphous silicon.
10. The semiconductor device of claim 1,
wherein said insulating film is a gate insulating film, and
said conductor film is a gate electrode.
11. The semiconductor device of claim 1,
wherein said element is a resistance element.
12. A method for manufacturing a semiconductor device, comprising:
a step (a) of forming a gate insulating film on a semiconductor layer;
a step (b), after said step (a), of forming a conductor film above said gate insulating film;
a step (c), after said step (b), of forming a first nitrogen-containing region by introducing nitrogen into an upper portion of said conductor film;
a step (d), after said step (c), of forming a gate electrode by patterning said conductor film; and
a step (e), after said step (d), of forming a first impurity layer in a region of said semiconductor layer which region is located sideways of said gate electrode, by introducing p-type impurities into said semiconductor layer while using said gate electrode as a mask.
13. The method of claim 12, further comprising, after said step (e):
a step (f) of forming a sidewall on a side surface of said gate electrode; and
a step (g) of forming a second impurity layer in a portion of said semiconductor layer which portion is located sideways of said sidewall by introducing the p-type impurities into said semiconductor layer while using said sidewall as the mask.
14. The method of claim 12, further comprising:
a step (h), after said step (a) and before said step (b), of forming a thin film conductor layer on said gate insulating film, and of forming a second nitrogen-containing region by introducing the nitrogen into said thin film conductor layer,
wherein at said step (b), said conductor film is formed on said second nitrogen-containing region.
15. The method of claim 12, further comprising:
a step (i), after said step (d) and before said step (e), of forming an oxynitride film that covers a side surface of said gate electrode.
16. The method of claim 15,
wherein at said step (i), an oxide film that covers said gate electrode is formed on said semiconductor layer, said oxynitride film is formed by introducing nitrogen into said oxide film, and then a portion of said oxynitride film which portion is located on at least said semiconductor layer is removed.
17. The method of claim 15,
wherein at said step (i), an oxide film that covers said gate electrode is formed on said semiconductor layer, a portion of said oxide film which portion is located on at least said semiconductor layer is removed, and then said oxynitride film is formed by introducing nitrogen into said oxide film.
18. A method for manufacturing a semiconductor device, comprising:
a step (a) of forming a gate insulating film on a semiconductor layer;
a step (b), after said step (a), of forming a conductor film above said gate insulating film;
a step (c), after said step (b), of forming a gate electrode by patterning said conductor film;
a step (d), after said step (c), of forming a first nitrogen-containing region by introducing nitrogen into at least part of an upper surface portion and a side surface portion of said gate electrode; and
a step (e) of forming a first impurity layer in a region of said semiconductor layer which region is located sideways of said gate electrode by introducing p-type impurities into said semiconductor layer while using said gate electrode as a mask.
19. The method of claim 18, further comprising, after said step (e):
a step (f) of forming a sidewall on a side surface of said gate electrode; and
a step (g) of forming a second impurity layer in a portion of said semiconductor layer which portion is located sideways of said sidewall by introducing the p-type impurities into said semiconductor layer while using said sidewall as the mask.
20. The method of claim 18, further comprising:
a step (h), after said step (a) and before said step (b), of forming a thin film conductor layer on said gate insulating film, and of forming a second nitrogen-containing region by introducing the nitrogen into said thin film conductor layer,
wherein at said step (b), said conductor film is formed on said second nitrogen-containing region.
21. The method of claim 18,
wherein at said step (d), said nitrogen is introduced while a resist covers said semiconductor layer.
22. The method of claim 18,
wherein at said step (d), a third nitrogen-containing region is formed in an upper portion of said semiconductor layer.
23. A method for manufacturing a semiconductor device, comprising:
a step (a) of forming a gate insulating film on a semiconductor layer;
a step (b), after said step (a), of forming a conductor film above said gate insulating film;
a step (c), after said step (b), of forming a gate electrode by patterning said conductor film;
a step (d), after said step (c), of forming a first impurity layer in a region of said semiconductor layer which region is located sideways of said gate electrode by introducing p-type impurities into said semiconductor layer while using said gate electrode as a mask;
a step (e), after said step (d), of forming a sidewall on a side surface of said gate electrode;
a step (f) of forming a second impurity layer in a portion of said semiconductor layer which portion is located sideways of said sidewall by introducing the p-type impurities into said semiconductor layer while using said sidewall as a mask; and
a step (g), after said step (f), of forming a nitrogen-containing region in an upper portion of said gate electrode and in an upper portion of said second impurity layer in said semiconductor layer by supplying nitrogen from above said semiconductor layer.
24. The method of claim 23, further comprising:
a step (h), after said step (a) and before said step (b), of forming a thin film conductor layer on said gate insulating film, and of introducing the nitrogen into said thin film conductor layer, and
wherein at said step (b), said conductor film is formed on said thin film conductor layer.

1. A method of detecting radar signals having a pulse width range and a chirping bandwidth range with a wireless receiver comprising the steps of:
receiving an input signal having a signal power;
processing the signal to relate frequency to signal magnitude to determine a frequency exhibiting maximum signal magnitude;
calculating a rate of change in the frequency exhibiting maximum signal magnitude; and
determining that the rate of change is within parameters established by the pulse width range and the chirping bandwidth range.
2. The method of claim 1, further comprising the step of determining that the signal power exceeds a threshold.
3. The method of claim 1, further comprising the step of determining that the input signal exhibits a pulse width within the pulse width range.
4. The method of claim 1, wherein the step of processing the signal comprises performing a plurality of FFT analyses, wherein each FFT analysis identifies a frequency bin corresponding to the maximum signal magnitude obtained from the output during that FFT analysis.
5. The method of claim 4, wherein the step of calculating the rate of change in the frequency exhibiting maximum signal magnitude comprises finding the difference between two frequency bins identified by sequential FFT analyses.
6. The method of claim 5, wherein the sequential FFT analyses are successive FFT analyses.
7. The method of claim 5, wherein the sequential FFT analyses are separated by at least one intervening FFT analysis.
8. The method of claim 1, wherein the pulse width range has a minimum and a maximum value and the chirping bandwidth range has a minimum and a maximum value and wherein the rate of change parameters comprise a first rate of change parameter corresponding to the ratio of the maximum pulse width value to the minimum chirping bandwidth value and a second rate of change parameter corresponding to the ratio of the minimum pulse width value to the maximum chirping bandwidth value.
9. The method of claim 3, further comprising the step of determining that the rate of change at a first time within the pulse width is within a maximum deviation threshold from the rate of change at a second time within the pulse width.
10. The method of claim 3, wherein the step of calculating the rate of change comprises calculating the rate of change a predetermined number of times and wherein the step of determining that the rate of change is within the parameters comprises determining each calculated rate of change is within the parameters.
11. A wireless network device for detecting radar signals having a pulse width range and a chirping bandwidth range comprising: an analog section; a digital section configured to produce a spectral analysis of an input signal having a signal power by determining a frequency exhibiting maximum signal magnitude; and a radar detection unit configured to calculate a rate of change in the frequency exhibiting maximum signal magnitude and determine that the rate of change is within parameters established by the pulse width range and the chirping bandwidth range.
12. The wireless network device of claim 11, wherein the radar detection unit is configured to determine that the signal power exceeds a threshold.
13. The wireless network device of claim 11, wherein the radar detection unit is configured to determine that the input signal exhibits a pulse width within the pulse width range.
14. The wireless network device of claim 13, wherein the digital section comprises a FFT unit configured to perform a plurality of FFT analyses on the input signal, wherein each FFT analysis identifies a frequency bin corresponding to the maximum signal magnitude obtained from the output during that FFT analysis.
15. The wireless network device of claim 14, wherein the radar detection unit is configured to calculate the rate of change in the frequency exhibiting maximum signal magnitude by finding the difference between two frequency bins identified by sequential FFT analyses.
16. The wireless network device of claim 15, wherein the sequential FFT analyses are successive FFT analyses.
17. The wireless network device of claim 15, wherein the sequential FFT analyses are separated by at least one intervening FFT analysis.
18. The wireless network device of claim 11, wherein the pulse width range has a minimum and a maximum value and the chirping bandwidth range has a minimum and a maximum value and wherein the rate of change parameters comprise a first rate of change parameter corresponding to the ratio of the maximum pulse width value to the minimum chirping bandwidth value and a second rate of change parameter corresponding to the ratio of the minimum pulse width value to the maximum chirping bandwidth value.
19. The wireless network device of claim 13, wherein the radar detection unit is configured to determine that the rate of change at a first time within the pulse width is within a maximum deviation threshold from the rate of change at a second time within the pulse width.
20. The wireless network device of claim 13, wherein the radar detection unit is configured to calculate the rate of change a predetermined number of times and to determine that each calculated rate of change is within the parameters.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for analyzing a mixture of chemical components, comprising:
obtaining a plurality of samples of the mixture, in which the samples include overlapping components;
measuring a plurality of wavelength of each sample of overlapping components;
storing the measured wavelengths of each sample as rows in a first matrix; and
applying independent component analysis to the first matrix to obtain a second matrix and a third matrix, in which columns of the first matrix are elution profiles of distinct component groups and rows of the third matrix are corresponding spectra of the distinct component groups.
2. The method of claim 1, in which the samples are obtained by chromatography, and the wavelengths are measured by spectography.
3. The method of claim 1, in which the mixture includes aromatic components.
4. The method of claim 1, in which the mixture is a diesel fuel.
5. A system for analyzing a mixture of chemical components, comprising:
a chromatograph produces a plurality of samples of the mixture, in which the samples include overlapping components;
a spectrometer measures a plurality of wavelength of each sample of overlapping components;
a memory stores the measured wavelengths of each sample as rows in a first matrix; and
means for applying independent component analysis to the first matrix to obtain a second matrix and a third matrix, in which columns of the first matrix are elution profiles of distinct component groups and rows of the third matrix are corresponding spectra of the distinct component groups.