Author: claimsbot

1-5 (Cancelled)
6. A semiconductor memory device, comprising:
a memory cell array comprising memory cells which require refresh;
an access circuit which performs refresh of the memory cell array after performing reading of the memory cell array for an access address or writing of the memory cell array for the access address based on a write request and write data presented asynchronously for the access address;
an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and
a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included in at least one of a chip select signal which controls the selected or non selected state, and the access address, and in which a completion timing has been set after it is determined whether the write request has been presented taking the time of detection as a reference.
7. A semiconductor memory device according to or claim 6,
wherein the control circuit sets the completion timing of the skew period after the time at which it is determined whether the write request is presented.
8. A semiconductor memory device, comprising:
a memory cell array comprising memory cells which require refresh;
an access circuit which performs refresh of the memory cell array after performing reading or writing of the memory cell array for the access address in the same memory cycle;
an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and
a control circuit which sets a completion timing for a skew period having a length greater than or equal to the maximum value of a skew included in at least one of a chip select signal which controls the selected state or non selected state, and the access address, taking the time of detection as a reference, to a time after a write request and write data presented asynchronously for the access address are determined.
9. A semiconductor memory device according to any one of claims 6 and 8, wherein, if writing, reading, or refresh which was started in a memory cycle preceding to the current memory cycle in which a read request or a write request is supplied has not been completed by the completion timing of a skew period for the current memory cycle, the control circuit delays the start of writing or reading in the current memory cycle until the writing, reading, or refresh has been completed.
10. A semiconductor memory device according to claim 9, wherein the access circuit performs refresh after reading or writing only once in a plurality of memory cycles, and
the control circuit delays the start of writing or reading in a memory cycle which is subsequent to the memory cycle in which the refresh is performed.
11. A semiconductor memory device according to claim 8, wherein the access circuit performs reading or late writing simultaneously for a plurality of addresses in the memory cell array, and
the control circuit performs the operation of sequentially outputting to the outside read data which have been obtained by the reading, or the operation of sequentially taking in write data which are input from the outside for the next late writing, in parallel with the refresh.
12. A semiconductor memory device according to claim 11, wherein the control circuit detects a change of predetermined upper bits in the access address, and, when performing the reading or the late writing, successively outputs the read data or successively takes in the write data for a plurality of addresses for which the predetermined upper bits in the access address are the same, while varying the lower address in the access address which is made up from the bits other than the predetermined upper bits.
13. A semiconductor memory device according to claim 12, wherein the control circuit successively outputs the read data or successively takes in the write data according to the lower address supplied from the outside.
14. A semiconductor memory device according to claim 12, wherein the control circuit successively outputs the read data or successively takes in the write data while varying the lower address according to a predetermined order based upon an initial value of the lower address supplied from the outside.
15. A semiconductor memory device according to claim 8, wherein the control circuit detects that a chip is in the non selected state or the deactivated state, and performs the refresh during the non selected state or the deactivated state.
16. A semiconductor memory device according to claim 8, further comprising:
a refresh control circuit comprising circuitry within the access circuit and the control circuit which performs control of the refresh, and a refresh address generation circuit which generates a refresh address showing memory cells to be refreshed, and which updates the refresh address each time the refresh is performed;
a voltage generation circuit which generates voltages supplied to parts within the device; and
a mode switching circuit which switches to one of a first mode in which power source is supplied both to the refresh control circuit and to the voltage generation circuit, a second mode in which supply of power source to the refresh control circuit is stopped while power source is supplied to the voltage generation circuit, and a third mode in which supply of power source both to the refresh control circuit and to the voltage generation circuit is stopped, and which controls whether supply of power source is performed to the refresh control circuit and the voltage generation circuit according to the switched mode.
17. A semiconductor memory device according to claim 16, wherein the mode switching circuit performs switching of mode by detecting that writing of predetermined data in each mode has been performed for a predetermined address.
18-20 (Cancelled)
21. A semiconductor memory device, comprising:
a memory cell array comprising memory cells which require refresh;
an access circuit which performs refresh of the memory cell array, after simultaneously performing reading for an access address or late writing for the access address based on a write request and writing data presented asynchronously for the access address, for a plurality of addresses in the memory cell array;
an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and
a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included in at least one of a chip selection signal which controls the selected state or non selected state, and the access address, taking the time of detection as a reference, and performs the operation of sequentially outputting the outside read data which has been obtained by the reading, or the operation of sequentially taking in write data which are input from the outside for the next late writing, in parallel with the refresh.
22. A semiconductor memory device according to claim 21, wherein the control circuit detects a change of predetermined upper bits in the access address, and, when performing the reading or the late writing for the plurality of addresses for which the predetermined upper bits in the access address are the same, successively outputs the read data or successively takes in the write data, while varying the lower address in the access address which is made up from the bits other than the predetermined upper bits.
23. A semiconductor memory device according to claim 22, wherein the control circuit successively outputs the read data or successively takes in the write data according to the lower address supplied from the outside.
24. A semiconductor memory device according to claim 22, wherein the control circuit successively outputs the read data or successively takes in the write data while varying the lower address according to a predetermined order, based upon an initial value of the lower address supplied from the outside.
25. A semiconductor memory device, comprising:
a memory cell array comprising memory cells which require refresh;
an access circuit which performs refresh of the memory cell array after performing reading of the memory cell array for an access address or writing of the memory cell array for the access address based on a write request and write data presented asynchronously for the access address;
an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed; and
a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included in at least one of a chip select signal which controls the selected state or non selected state, and the access address, taking the time of detection as a reference, and detects that a chip is in the non selected state or the deactivated state, and performs the refresh during the non selected state or the deactivated state.
26. A semiconductor memory device, comprising:
a memory cell array comprising memory cells which require refresh;
an access circuit which performs refresh of the memory cell array after performing reading of the memory cell array for an access address or writing of the memory cell array for the access address based on a write request and write data presented asynchronously for the access address;
an address transition detect circuit which detects whether a chip has transited from the non selected state to the selected state, or that the access address has changed;
a control circuit which starts the reading or the writing after a skew period has elapsed which is set greater than or equal to the maximum value of a skew included in at least one of a chip select signal which controls the selected or non selected state, and the access address, taking the time of detection as a reference;
a refresh control circuit comprising circuitry within the access circuit and the control circuit which performs control of the refresh, and a refresh address generation circuit which generates a refresh address showing the memory cell to be refreshed, and which updates the refresh address each time the refresh is performed;
a voltage generation circuit which generates voltages supplied to parts within the device; and
a mode switching circuit which switches to one of a first mode in which power source is supplied both to the refresh control circuit and to the voltage generation circuit, a second mode in which supply of power source to the refresh control circuit is stopped while power source is supplied to the voltage generation circuit, and a third mode in which supply of power source both to the refresh control circuit and to the voltage generation circuit is stopped, and which controls whether supply of power source is performed o the refresh control circuit and the voltage generation circuit according to the switched mode.
27. A semiconductor memory device according to claim 26, wherein the mode switching circuit performs switching of mode by detecting that writing of predetermined data in each mode has been performed for a predetermined address.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. For use in a Radio Access Network of a telecommunications system, a method comprising deriving control parameters for controlling an in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) from corresponding cell based parameters.
2. A method according to claim 1 where the control parameters for controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) are derived from the corresponding cell based parameters of the cells of the individual Radio Links of a set of combined radio links (radio link set) in a base station.
3. A method according to claim 2 where the control parameters are derived by taking the largest value of the corresponding cell based parameters.
4. A method according to claim 2 where the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
5. A method according to claim 2 where the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
6. A method according to claim 2 where the control parameters are derived according to any of the methods in claims 3, 4, and 5 for each individual control parameter.
7. A method according to claim 1 where the control parameters for controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) are derived from the corresponding cell based parameters of all cells in the base station.
8. A method according to claim 7 where the control parameters are derived by taking the largest value of the corresponding cell based parameters.
9. A method according to claim 7 where the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
10. A method according to claim 7 where the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
11. A method according to claim 7 where the control parameters are derived according to any of the methods in claims 8, 9, and 10 for each individual control parameter.
12. A method according to claim 1 where the control parameters for controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) are derived from the corresponding cell based parameters of any potential radio link set in a base station, where a potential radio link set corresponds to any combination of one or more cells in a base station.
13. A method according to claim 12 where the control parameters are derived by taking the largest value of the corresponding cell based parameters.
14. A method according to claim 12 where the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
15. A method according to claim 12 where the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
16. A method according to claim 12 where the control parameters are derived according to any of the methods in claims 13, 14, and 15 for each individual control parameter.
17. A method according to claim 1 where the control parameters controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) is controlled by parameters that are derived from the corresponding cell based parameters using any combination of the methods in claims 2, 7, and 12 for the individual control parameters.
18. A method according to claim 17 where the control parameters are derived by taking the largest value of the corresponding cell based parameters.
19. A method according to claim 17 where the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
20. A method according to claim 17 where the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
21. A method according to claim 17 where the control parameters are derived according to any of the methods in claims 18, 19, and 20 for each individual control parameter.
22. A radio access network of a telecommunications system comprising:
an in-and-out of synchronization detector which judges reception quality of a connection with a mobile user equipment unit;
a control parameter determination function which determines control parameters to be utilized by the in-and-out of synchronization detector, the control parameter determination function determining the control parameters for a set of combined radio links (radio link set) from corresponding cell based parameters.
23. An apparatus according to claim 22, wherein the control parameter determination function derives the control parameters for controlling the in-and-out-of-synchronization detector for a set of combined radio links (radio link set) from the corresponding cell based parameters of the cells of the individual Radio Links of a set of combined radio links (radio link set) in a base station.
24. An apparatus according to claim 23, wherein the control parameters are derived by taking the largest value of the corresponding cell based parameters.
25. An apparatus according to claim 23, wherein the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
26. An apparatus according to claim 23, wherein the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
27. An apparatus according to claim 23, wherein the control parameters are derived according to any of the methods in claims 24, 25, and 26 for each individual control parameter.
28. An apparatus according to claim 22, wherein the control parameter determination function derives the control parameters for controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) from the corresponding cell based parameters of all cells in the base station.
29. An apparatus according to claim 28, wherein the control parameters are derived by taking the largest value of the corresponding cell based parameters.
30. An apparatus according to claim 28, wherein the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
31. An apparatus according to claim 28, wherein the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
32. An apparatus according to claim 28, wherein the control parameters are derived according to any of the methods in claims 29, 30, and 31 for each individual control parameter.
33. An apparatus according to claim 22, wherein the control parameter determination function derives the control parameters for controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) from the corresponding cell based parameters of any potential radio link set in a base station, where a potential radio link set corresponds to any combination of one or more cells in a base station.
34. An apparatus according to claim 33, wherein the control parameters are derived by taking the largest value of the corresponding cell based parameters.
35. An apparatus according to claim 33, wherein the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
36. An apparatus according to claim 33, wherein the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
37. An apparatus according to claim 33, wherein the control parameters are derived according to any of the methods in claims 34, 35, and 36 for each individual control parameter.
38. An apparatus according to claim 22, wherein the control parameter determination function derives the control parameters controlling the in-and-out-of-synchronization detection algorithm for a set of combined radio links (radio link set) from the corresponding cell based parameters using any combination of the methods in claims 23, 28, and 33 for the individual control parameters.
39. An apparatus according to claim 38, wherein the control parameters are derived by taking the largest value of the corresponding cell based parameters.
40. An apparatus according to claim 38, wherein the control parameters are derived by taking the lowest value of the corresponding cell based parameters.
41. An apparatus according to claim 38, wherein the control parameters are derived by taking a weighed or non-weighed average value of the corresponding cell based parameters.
42. An apparatus according to claim 38, wherein the control parameters are derived according to any of the methods in claims 39, 40, and 41 for each individual control parameter.
43. An apparatus according to claim 22, wherein the in-and-out of synchronization detector is situated at a base station of the radio access network.
44. An apparatus according to claim 22, wherein the control parameter determination function is situated at a radio network control (RNC) node of the radio access network.
45. An apparatus according to claim 22, wherein the control parameter determination function is situated at a base station of the radio access network.

What is claimed is:

1. A system for performing independent verification, comprising:
a processor;
a question generating unit, connected to the processor, for posing questions to a customer through a communications medium;
a response analysis unit, connected to the processor, configured to analyze customer responses to questions; and
a recording unit configured to record customer responses to questions.
2. The system of claim 1, wherein the question generating unit comprises a speech synthesis unit.
3. The system of claim 1, wherein the question generating unit comprises an audio player for playing pre-recorded sounds.
4. The system of claim 1, further comprising a customer data interface for receiving customer-specific information, wherein the question generating unit is configured to generate at least one question based on customer-specific information received through the customer data interface.
5. The system of claim 1, wherein the system is configured to communicate with a customer over at least one communications medium selected from the group consisting of a telephone network, a local area computer network, a wide area computer network, a worldwide computer network, and a radio communications system.
6. The system of claim 5, wherein the response analysis unit is configured to interpret DTMF tones.
7. The system of claim 5, wherein the response analysis unit is configured to perform voice recognition to interpret oral responses.
8. The system of claim 7, wherein the system is configured to simultaneously record a customer’s oral response and perform voice recognition on the oral response to interpret the oral response.
9. The system of claim 5, wherein a customer response is given by pressing one or more keys on a computer keyboard, and wherein the response analysis unit is configured to determine what keys are pressed.
10. The system of claim 5, wherein a customer response is given by activating one or more buttons of a computer graphical pointing device, and wherein the response analysis unit is configured interpret such responses.
11. The system of claim 1, further comprising an operator interface configured to allow an operator to review recorded customer responses.
12. The system of claim 11, wherein the operator interface allows an operator to input an operator score for a series of recorded customer responses.
13. The system of claim 12, wherein the response analysis unit is configured to automatically generate an automated score for a series of customer responses.
14. The system of claim 13, further comprising a comparing unit for comparing an operator score of a series of customer responses to an automated score for the series of customer responses.
15. The system of claim 14, wherein the comparing unit confirms an independent verification if an operator score for a series of customer responses matches an automated score for the series of customer responses.
16. The system of claim 14, wherein the comparing unit flags a series of customer responses for further analysis if an operator score for the series of customer responses does not match an automated score for the series of customer responses.
17. The system of claim 16, wherein if the comparing unit flags a series of customer responses for further analysis, the response analysis unit re-analyzes the series of customer responses and generates a new automated score, and wherein the comparing unit is configured to compare the new automated score to an operator score for the series of customer responses.
18. The system of claim 1, wherein the system is configured to retrieve a series of customer responses that were recorded by the recording unit based on customer-specific information.
19. The system of claim 1, wherein the system is configured to re-create a series of questions posed to a customer, and the customer’s responses to those questions, based on information recorded by the recording unit.
20. The system of claim 1, wherein the system is configured to generate a transcript of questions posed to a customer and the customer’s responses to those questions based, at least in part, on information stored by the recording unit.
21. A method of performing independent verification, comprising the steps of:
a) posing a question to a customer with an automated question generating unit;
b) recording the customer’s response to the question; and
c) analyzing the customer’s response to the question with a response analysis unit.
22. The method of claim 21, wherein step (c) is performed simultaneously with step (b).
23. The method of claim 21, wherein step (a) comprises generating a question with a voice synthesis unit.
24. The method of claim 21, wherein step (a) comprises generating a question by playing pre-recorded sounds.
25. The method of claim 21, further comprising the step of receiving customer-specific information prior to performing step (a), and wherein step (a) comprises generating a question based on the received customer-specific information.
26. The method of claim 21, wherein step (c) comprises interpreting DTMF tones.
27. The method of claim 21, wherein step (c) comprises performing voice recognition to interpret a customer’s oral response to a question.
28. The method of claim 21, further comprising the step of automatically generating an automated score of at least one customer response.
29. The method of claim 21, further comprising the steps of:
playing at least one recorded customer response for a live operator; and
recording an operator score generated by the live operator based on the at least one recorded customer response.
30. The method of claim 29, further comprising the step of automatically generating and recording an automated score for at least one customer response.
31. The method of claim 30, further comprising the steps of:
comparing an operator score for at least one customer response to an automated score for the at least one customer response;
confirming the independent verification if the operator score corresponds with the automated score; and
flagging the at least one customer response if the operator score does not correspond with the automated score.
32. The method of claim 31, further comprising the steps of:
re-analyzing and automatically generating and recording a new automated score for any flagged customer responses; and
comparing an operator score for any flagged customer responses to the new automated score.
33. The method of claim 21, further comprising the steps of:
d) determining whether to pose an additional question to the customer; and
e) repeating steps (a)-(d) if the result of step (d) is to pose an additional question.
34. The method of claim 33, wherein the determination made in step (d) is based, in part, on an analysis of a previous customer response.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An automated apparatus for treating microscope slides, comprising:
a slide support assembly comprising a plurality of slide support elements, each of which is sized to support a microscope slide thereon, and wherein each slide support element is movable horizontally independently of each other slide support element and wherein said horizontal movement is in a single back and forth direction; and
a treatment chamber able to contain microscope slides disposed on the slide support elements of the slide support assembly; and
wherein each slide support element has a separate heating element corresponding thereto and wherein each heating element of the plurality of slide support elements is separately controllable by a microprocessor.
2. The automated apparatus of claim 1 wherein the horizontal movement of the slide support element is a sliding movement.
3. An automated apparatus for treating microscope slides, comprising:
a slide support assembly comprising a plurality of slide support elements, each of which is sized to support a single microscope slide thereon, and wherein each slide support element is movable horizontally independently of each other slide support element and wherein said horizontal movement is in a single back and forth direction; and
a treatment chamber able to contain microscope slides disposed on the slide support elements of the slide support assembly; and
wherein each slide support element has a separate heating element incorporated therein and which is movable therewith and wherein each heating element of the plurality of slide support elements is separately controllable by a microprocessor.
4. The automated apparatus of claim 3 wherein the horizontal movement of the slide support element is a sliding movement.
5. An automated apparatus for treating microscope slides, comprising:
a slide support assembly comprising a plurality of slide support elements, each of which is sized to support a microscope slide thereon, and wherein each slide support element is movable horizontally independently of each other slide support element and wherein said horizontal movement is in a single back and forth direction; and
a plurality of reagent dispensers; and
wherein each slide support element has a separate heating element corresponding thereto and wherein each heating element of the plurality of slide support elements is separately controllable by a microprocessor.
6. The automated apparatus of claim 5 wherein the horizontal movement of the slide support element is a sliding movement.
7. The automated apparatus of claim 5 wherein the reagent dispensers of the apparatus are positioned above the slide support elements.
8. An automated apparatus for treating microscope slides, comprising:
a slide support assembly comprising a plurality of slide support elements, each of which is sized to support a single microscope slide thereon, and wherein each slide support element is movable horizontally independently of each other slide support element and wherein said horizontal movement is in a single back and forth direction; and
a plurality of reagent dispensers; and
wherein each slide support element has a separate heating element incorporated therein and which is movable therewith and wherein each heating element of the plurality of slide support elements is separately controllable by a microprocessor.
9. The automated apparatus of claim 8 wherein the horizontal movement of the slide support element is a sliding movement.
10. The automated apparatus of claim 8 wherein the reagent dispensers of the apparatus are positioned above the slide support elements.