Author: claimsbot

1. A non-volatile memory comprising:
a plurality of nonvolatile memory cells; and an error correcting circuit,
wherein a program command accompanied with address information and first data are received from outside,
wherein, in a program operation executed in response to said program command, first nonvolatile memory cells of said plurality of nonvolatile memory cells are selected in accordance with said address information and programmed with said first data,
wherein, after said first nonvolatile memory cells are programmed with said first data in said program operation, second nonvolatile memory cells of said plurality of nonvolatile memory cells are selected and second data stored therein are read out,
wherein said error correcting circuit judges whether said second data includes one or more errors and corrects said second data to create third data when said second data includes one or more errors, and
wherein said second nonvolatile memory cells are programmed with said third data after said second data is corrected by said error correcting circuit.
2. A nonvolatile memory according to claim 1, wherein, after said first data is programmed and before said second nonvolatile memory cells are selected:
said first nonvolatile memory cells are selected and fourth data stored therein is read out,
said error correcting circuit judges whether said fourth data includes errors which are correctable or not correctable,
said first nonvolatile memory cells are programmed again with said first data, if said fourth data includes errors which are not correctable by said error correcting circuit, and
programming of said first nonvolatile memory cells with said first data is completed if said fourth data includes errors which are correctable by said error correcting circuit.
3. A nonvolatile memory according to claim 2, wherein after said first data is programmed:
said error correcting circuit judges whether said fourth data includes errors which are correctable or not correctable, and
when said error correcting judges that said fourth data includes errors which are not correctable, third nonvolatile memory cells of said plurality of nonvolatile memory cells, different from said first nonvolatile memory cells, are selected and programmed with said first data.
4. A nonvolatile memory according to claim 3, further comprising a controller including said error correcting circuit.
5. A nonvolatile memory according to claim 4, wherein:
said controller further includes a buffer memory, and
said first data is stored in said buffer memory until completion of programming with said first data.
6. A nonvolatile memory according to claim 1, wherein each of said plurality of nonvolatile memory cells is a one-bit memory cell.
7. A nonvolatile memory according to claim 1, wherein each of said plurality of nonvolatile memory cells is a multiple-bit memory cell.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-90. (canceled)
91. A method of electrochemically processing microelectronic workpieces in a reaction vessel having a workpiece processing zone, the method comprising:
passing a processing fluid through a distributor in the reaction vessel by flowing the processing fluid through a first channel of the distributor and a second channel of the distributor;
receiving the processing fluid from the first channel in a first electrode compartment in the reaction vessel in which a first electrode is positioned and flowing the processing fluid through the first electrode compartment;
receiving the processing fluid from the second channel in a second electrode compartment in the reaction vessel in which a second electrode is positioned and flowing the processing fluid through the second electrode compartment;
applying a first electrical potential to the first electrode and applying a second electrical potential to the second electrode that is different than the first electrical potential; and
inhibiting matter in the processing fluid from passing out of the first and second electrode compartments and to the processing zone.
92. The method of claim 91, further comprising changing at least one of the first electrical potential andor the second electrical potential while processing a workpiece.
93. The method of claim 91, further comprising directing a primary fluid flow through the reaction vessel toward the processing zone, and wherein the processing fluid flowing through the first and second channels of the distributor comprises a secondary flow of processing fluid that is separated from the primary fluid flow through at least a portion of the reaction vessel.
94. The method of claim 93 wherein the primary fluid flow comprises a catholyte and the secondary fluid flow comprises an anolyte.
95. The method of claim 94, further comprising contacting a surface of a microelectronic workpiece with the catholyte.
96. The method of claim 95, further comprising changing at least one of the first electrical potential andor the second electrical potential while contacting the surface of the microelectronic workpiece with the catholyte.
97. The method of claim 91, further comprising:
directing a primary fluid flow of a catholyte through the reaction vessel toward the processing zone;
contacting a surface of a microelectronic workpiece with the catholyte; and
separating the primary fluid flow of the catholyte from the processing fluid flowing through the first and second electrode compartments, wherein the processing fluid flowing through the first and second electrode compartment comprises an anolyte and defines a secondary fluid flow.
98. The method of claim 97 wherein separating the primary fluid flow from the secondary fluid flow comprises providing an ion-membrane in the reaction vessel located between the processing zone and at least one of the first and second electrode compartments.
99. A method of electrochemically processing a microelectronic workpiece in a reaction vessel having a workpiece processing zone, the method comprising:
directing an electrolytic processing fluid through a portion of the reaction vessel by passing the processing fluid through an inlet in the reaction vessel, flowing a first portion of the processing fluid from the inlet and through a first channel in the reaction vessel to a first electrode compartment in the reaction vessel, and flowing a second portion of the processing fluid from the inlet and through a second channel in the reaction vessel to a second electrode compartment in the reaction vessel;
inhibiting matter in the processing fluid from passing out of the electrode compartments and flowing to the processing zone;
applying a first electrical potential to a first electrode in the first electrode compartment and applying a second electrical potential to a second electrode in the second electrode compartment, wherein the first electrical potential is different than the second electrical potential; and
subjecting a surface of a microelectronic workpiece to an electrical field established by the first and second electrodes.
100. The method of claim 99, further comprising changing at least one of the first electrical potential andor the second electrical potential while subjecting the workpiece to the electrical field.
101. The method of claim 99, further comprising directing a primary fluid flow through the reaction vessel toward the processing zone, and wherein the processing fluid flowing through the first and second channels of the distributor comprises a secondary flow of processing fluid that is separated from the primary fluid flow through at least a portion of the reaction vessel.
102. The method of claim 101 wherein the primary fluid flow comprises a catholyte and the secondary fluid flow comprises an anolyte.
103. The method of claim 102 wherein subjecting the surface of the microelectronic workpiece to the electrical field established by the first and second electrodes comprises contacting the surface of a microelectronic workpiece with the catholyte.
104. The method of claim 103, further comprising changing at least one of the first electrical potential andor the second electrical potential while contacting the surface of the microelectronic workpiece with the catholyte.
105. The method of claim 99, further comprising:
directing a primary fluid flow of a catholyte through the reaction vessel toward the processing zone; and
separating the primary fluid flow of the catholyte from the processing fluid flowing through the first and second electrode compartments, wherein the processing fluid flowing through the first and second electrode compartment comprises an anolyte and defines a secondary fluid flow.
106. The method of claim 105 wherein separating the primary fluid flow from the secondary fluid flow comprises providing an ion-membrane in the reaction vessel located between the processing zone and at least one of the first and second electrode compartments.
107. A method of electrochemically processing a microelectronic workpiece in a reaction vessel having a workpiece processing zone, the method comprising:
directing a primary fluid flow through the reaction vessel and to the processing zone;
contacting a surface of a microelectronic workpiece with the primary fluid flow;
directing a secondary fluid flow through at least a portion of the reaction vessel such that a first portion of the secondary fluid flow passes through a first electrode compartment in the reaction vessel in which a first electrode is positioned and a second portion of the secondary fluid flow passes through a second electrode compartment in the reaction vessel in which a second electrode is positioned; and
inhibiting matter in the secondary fluid flow from passing into the primary fluid flow.
108. The method of claim 107, further comprising:
applying a first electrical potential to the first electrode and applying a second electrical potential to the second electrode; and
changing at least one of the first electrical potential andor the second electrical potential while processing a workpiece.
109. The method of claim 107 wherein the secondary fluid flow is separated from the primary fluid flow through at least a portion of the reaction vessel.
110. The method of claim 109 wherein the primary fluid flow comprises a catholyte and the secondary fluid flow comprises an anolyte.
111. The method of claim 107, further comprising separating the primary fluid flow from the secondary fluid flow by providing an ion-membrane in the reaction vessel located between the processing zone and at least one of the first and second electrode compartments.

1. A housing apparatus for placement on a floor and receiving a flowable body cushion, the housing apparatus comprising:
a base portion having opposing first and second surfaces, said first surface facing in a direction towards the floor and said second surface facing in a direction away from the floor and having a maximum distance from the floor;
a back portion extending from said base portion in a direction away from the floor and having a maximum distance from the floor greater than the maximum distance from the floor of said second surface;
said second surface of said base portion and said back portion defining an area designed to receive the flowable body cushion.
2. The housing apparatus of claim 1, wherein said base portion is circular.
3. The housing apparatus of claim 2, wherein said back portion conforms to an outer arcuate portion of said base portion.
4. The housing apparatus of claim 3, wherein said back portion extends at least 180 degrees around the circular shape of said base portion.
5. The housing apparatus of claim 3, wherein said back portion tapers from its maximum distance from the floor to the maximum distance from the floor of said second surface of said base portion.
6. The housing apparatus of claim 5, wherein said back portion extends around at least 180 degrees of the circular shape of said base portion.
7. The housing apparatus of claim 1, wherein said base portion is rectangular.
8. The housing apparatus of claim 1, further comprising feet members extending between said first surface and the floor.
9. The housing apparatus of claim 1, wherein said first and second surfaces of said base portion are substantially parallel to each other.
10. The housing apparatus of claim 1, wherein said second surface of said base portion is generally planar.
11. The housing apparatus of claim 1, wherein said second surface of said base portion is generally concave such that a center portion of said second surface is closer to the floor than an off-center portion of said second surface.
12. The housing apparatus of claim 1, further comprising means for removably attaching the flowable body cushion to said base portion.
13. The housing apparatus of claim 12, wherein said means for attaching the flowable body cushion to said base portion comprises at least one of a zipper, Velcro\xae, snap, and button.
14. A housing apparatus for placement on a floor and receiving a flowable body cushion, the housing comprising a rigid cylinder having a bottom portion, a top portion, and a cylindrical wall surface extending between said bottom and top portions and defining an open center portion, wherein said center portion is designed to receive the flowable body cushion.
15. The housing apparatus of claim 14, wherein said bottom portion is parallel to the floor.
16. The housing apparatus of claim 15, wherein said top portion is non-parallel to the floor.
17. The housing apparatus of claim 14, wherein at least a portion of said housing is upholstered.
18. The housing apparatus of claim 14, further comprising a circular base portion located within said open center portion, said base portion having opposing first and second surfaces, said first surface facing in a direction towards the floor and said second surface facing in a direction away from the floor, said second surface and said cylindrical wall surface defining an area designed to receive the flowable body cushion.
19. The housing apparatus of claim 18, further comprising feet members extending between said first surface and the floor.
20. The housing apparatus of claim 18, wherein said base portion is fixedly attached to said rigid cylinder.
21. A seating device comprising:
a housing apparatus for placement on a floor and receiving a flowable body cushion, the housing apparatus comprising:
a base portion having opposing first and second surfaces, said first surface facing in a direction towards the floor and said second surface facing in a direction away from the floor and having a maximum distance from the floor; and
a back portion extending from said base portion in a direction away from the floor and having a maximum distance from the floor greater than the maximum distance from the floor of said second surface;
said second surface of said base portion and said back portion defining an area designed to receive the flowable body cushion; and

a flowable body cushion placed within said area designed to receive the flowable body cushion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An inline memory module (IMM) architecture comprising:
a printed circuit board (PCB);
a first array of memory devices on a first side of the PCB;
a second array of memory devices on a second side of the PCB; and
a plurality of vias; wherein
at least some of the memory devices of the first array are arranged so as to substantially overlap, relative to a reference axis of the PCB, positional-twin memory devices of the second array, respectively; and
at least some of the plurality of vias include:
a first opening along the first side of the PCB,
a second opening along the second side of the PCB, and
at least one signal path that passes through both the first opening and the second opening of the vias and connects IO terminals of a first memory device in the first array to corresponding IO terminals of a second memory device in the second array that is adjacent to a third memory device in the second array, where the third memory device is a positional-twin corresponding to the first memory device.
2. The IMM architecture of claim 1, wherein:
at least some IO terminals of each memory device are clustered along opposing edges of the memory device; and
locations for a majority of the vias are in regions defined between IO terminals at edges of adjacent memory devices of the first array, respectively.
3. The IMM architecture of claim 2, wherein the regions also are defined as being between signal pads at edges of adjacent memory devices of the second array.
4. The IMM architecture of claim 2, wherein the following is true for the majority of the vias:
the via is located within an area inward from peripheral signal pads of the respective second memory device in the second array.
5. The IMM architecture of claim 2, wherein the adjacent memory devices are considered adjacent relative to the reference axis.
6. The IMM architecture of claim 5, wherein the longitudinal axis of the PCB is the reference axis.
7. The IMM architecture of claim 1, wherein:
at least some signal pads of each memory device are clustered along opposing edges of the memory device; and
the first array is arranged relative to the second array so that a fourth memory device in the first array is displaced, along the reference axis, relative to a corresponding positional-twin fifth memory device in the second array such that signal pads at one edge of the fifth memory device align with a region located aside signal pads at one edge of the fourth memory device.
8. The IMM architecture of claim 7, wherein the following is true for a majority of the vias:
the region is defined between the signal pads at the one edge of the fourth memory device and signal pads at one edge of a sixth memory device in the first array that is adjacent to the fourth memory device.
9. The IMM architecture of claim 1, wherein the following is true for a majority of the memory devices in the first and second arrays:
the first array is arranged relative to the second array so that a fourth memory device in the first array is displaced, along the reference axis, relative to a corresponding positional-twin fifth memory device in the second array such that the fifth memory device partially overlaps a sixth memory device in the first array that is adjacent to the fourth memory device.
10. The IMM architecture of claim 1, wherein the following is true for a majority of the vias:
the vias are located, relative to the reference axis, inward from peripheral signal pads of the memory devices of the first array, respectively.
11. The IMM architecture of claim 10, wherein:
the first array is arranged relative to the second array so that a fourth memory device in the first array is displaced, along the reference axis, relative to a corresponding positional-twin fifth memory device in the second array such that a sixth memory device in the second array adjacent to the fifth memory device partially overlaps the fourth memory device in the first array.
12. The IMM architecture of claim 10, wherein the following is true for a majority of the vias:
the vias are located, relative to the reference axis, inward from peripheral signal pads of the memory devices of the second array, respectively.
13. The IMM architecture of claim 10, wherein the following is true for a majority of the vias:
the via is aligned with an area defined between signal pads at edges of the second and third memory devices in the second array.
14. The IMM architecture of claim 1, wherein the IMM architecture is a type of dual IMM (DIMM) architecture.
15. The IMM architecture of claim 1, wherein the following is true for a majority of the vias:
the signal lead of the given first memory device, for the given signal path that includes the given via, is substantially the same length as the signal lead of the given second memory device.
16. An inline memory module (IMM) architecture comprising:
printed circuit board (PCB) means;
a first array of memory devices on a first side of the PCB means;
a second array of memory devices on a second side of the PCB means; and
a plurality of via means; wherein
at least some of the memory devices of the first array are arranged so as to substantially overlap, relative to a reference axis of the PCB means, positional-twin memory devices of the second array, respectively; and
at least some of the plurality of via means include:
a first opening along the first side of the PCB means,
a second opening along the second side of the PCB means, and
at least one signal path, that passes through both the first and second openings of the via means, for connecting signal leads of a first memory device in the first array to corresponding signal leads of a second memory device in the second array that is adjacent to a third memory device in the second array, where the third memory device is a positional-twin corresponding to the first memory device.
17. The IMM architecture of claim 16, wherein:
at least some signal pads of each memory device are clustered along opposing edges of the memory device; and
locations for a majority of the via means are in regions defined between signal pads at edges of adjacent memory devices of the first array, respectively.
18. The IMM architecture of claim 16, wherein the adjacent memory devices are considered adjacent relative to the longitudinal axis of the PCB means.
19. The IMM architecture of claim 16, wherein:
at least some signal pads of each memory device are clustered along opposing edges of the memory device; and
the first array is arranged relative to the second array so that a fourth memory device in the first array is displaced, along the reference axis, relative to a corresponding positional-twin fifth memory device in the second array such that signal pads at one edge of the fifth memory device align with a region located aside signal pads at one edge of the fourth memory device.
20. The IMM architecture of claim 16, wherein the following is true for a majority of the memory devices in the first and second arrays:
the first array is arranged relative to the second array so that a fourth memory device in the first array is displaced, along the reference axis, relative to a corresponding positional-twin fifth memory device in the second array such that the fifth memory device partially overlaps a sixth memory device in the first array that is adjacent to the fourth memory device.