Author: claimsbot

1. A circuit to convert a first logic signal having a first range to a second logic signal having a second range, comprising:
a first transistor to selectively couple an output node to a first reference voltage when the output node is to be in a first state;
a second transistor to selectively discharge the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state;
a source-follower circuit having a source follower output coupled to the output node and having a current source; and
a third transistor to selectively couple the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
2. A circuit according to claim 1, wherein a gate of the first transistor is coupled to a first control signal;
wherein a gate of the second transistor is coupled to a second control signal, the second control signal being a logical complement of the first control signal;
wherein a gate of the third transistor is coupled to the first control signal.
3. A circuit according to claim 2, further comprising a flip-flop having an input, a first output, and a second output, the second output being a complement of the first output;
wherein the first logic signal is coupled to the input of the flip-flop;
wherein the first output of the flip-flop is coupled to the gate of the second transistor;
wherein the second output of the flip-flop is coupled to the gate of the first transistor;
wherein the second output of the flip-flop is coupled to the gate of the third transistor.
4. A circuit according to claim 2, further comprising an inverter having an input coupled to the first logic signal and an output;
wherein the first logic signal is coupled to the gate of the second transistor;
wherein the output of the inverter is coupled to the gate of the first transistor;
wherein the output of the inverter is coupled to the gate of the third transistor.
5. A circuit according to claim 1, wherein the source-follower circuit comprises a fourth transistor having a source coupled to the output node, a drain coupled to the first reference voltage, and a gate coupled to a first bias voltage;
wherein the current source of the source-follower circuit comprises a fifth transistor having a drain coupled to the output node, a source coupled to the third transistor, and a gate coupled to a second bias voltage.
6. A circuit according to claim 5, wherein a source of the first transistor is coupled to the first reference voltage, and a drain of the first transistor is coupled to the output node;
wherein a source of the second transistor is coupled to the output node, and a drain of the second transistor is coupled to the second reference voltage;
wherein a source of the third transistor is coupled to the second reference voltage, and a drain of the third transistor is coupled to the source of the fifth transistor.
7. A circuit according to claim 6, wherein the first transistor is a p-channel MOS (PMOS) transistor;
wherein the second transistor is a PMOS transistor;
wherein the third transistor is an n-channel MOS (NMOS) transistor;
wherein the fourth transistor is an NMOS transistor; and
wherein the fifth transistor is an NMOS transistor.
8. A circuit according to claim 7, wherein a gate of the first transistor is coupled to a first control signal;
wherein a gate of the second transistor is coupled to a second control signal, the second control signal being a logical complement of the first control signal;
wherein a gate of the third transistor is coupled to the first control signal.
9. A circuit according to claim 1, wherein the source-follower circuit keeps a voltage of the output node in the second state in an approximate range of 100 millivolts to 350 millivolts.
10. A circuit to convert a first logic signal having a first range to a pair of complementary second logic signals having a second range, comprising:
a first transistor to selectively couple a first output node to a first reference voltage when the first output node is to be in a first state;
a second transistor to selectively discharge the first output node toward a second reference voltage when the first output node is to transition from the first state to a second state, the second state being a logical complement of the first state;
a first source-follower circuit having a source follower output coupled to the first output node and having a current source; and
a third transistor to selectively couple the current source of the first source-follower circuit to the second reference voltage when the first output node is to be in the second state;
a fourth transistor to selectively couple a second output node to the first reference voltage when the second output node is to be in the first state;
a fifth transistor to selectively discharge the second output node toward the second reference voltage when the second output node is to transition from the first state to the second state;
a second source-follower circuit having a source follower output coupled to the second output node and having a current source; and
a sixth transistor to selectively couple the current source of the second source-follower circuit to the second reference voltage when the second output node is to be in the second state.
11. A circuit according to claim 10, wherein a gate of the first transistor is coupled to a first control signal;
wherein a gate of the second transistor is coupled to a second control signal, the second control signal being a logical complement of the first control signal;
wherein a gate of the third transistor is coupled to the first control signal;
wherein a gate of the fourth transistor is coupled to the second control signal;
wherein a gate of the fifth transistor is coupled to the first control signal;
wherein a gate of the sixth transistor is coupled to the second control signal.
12. A circuit according to claim 11, further comprising a flip-flop having an input, a first output, and a second output, the second output being a complement of the first output;
wherein the first logic signal is coupled to the input of the flip-flop;
wherein the first output of the flip-flop is coupled to the gate of the second transistor;
wherein the second output of the flip-flop is coupled to the gate of the first transistor;
wherein the second output of the flip-flop is coupled to the gate of the third transistor;
wherein the second output of the flip-flop is coupled to the gate of the fifth transistor;
wherein the first output of the flip-flop is coupled to the gate of the fourth transistor;
wherein the first output of the flip-flop is coupled to the gate of the sixth transistor.
13. A circuit according to claim 11, further comprising an inverter having an input coupled to the first logic signal and an output;
wherein the first logic signal is coupled to the gate of the second transistor;
wherein the output of the inverter is coupled to the gate of the first transistor;
wherein the output of the inverter is coupled to the gate of the third transistor;
wherein the output of the inverter is coupled to the gate of the fifth transistor;
wherein the first logic signal is coupled to the gate of the fourth transistor;
wherein the first logic signal is coupled to the gate of the sixth transistor.
14. A circuit according to claim 10, wherein the first source-follower circuit comprises a seventh transistor having a source coupled to the first output node, a drain coupled to the first reference voltage, and a gate coupled to a first bias voltage;
wherein the current source of the first source-follower circuit comprises an eighth transistor having a drain coupled to the first output node, a source coupled to the third transistor, and a gate coupled to a second bias voltage;
wherein the second source-follower circuit comprises a ninth transistor having a source coupled to the second output node, a drain coupled to the first reference voltage, and a gate coupled to the first bias voltage;
wherein the current source of the second source-follower circuit comprises a tenth transistor having a drain coupled to the second output node, a source coupled to the sixth transistor, and a gate coupled to the second bias voltage.
15. A circuit according to claim 14, wherein a source of the first transistor is coupled to the first reference voltage, and a drain of the first transistor is coupled to the first output node;
wherein a source of the second transistor is coupled to the first output node, and a drain of the second transistor is coupled to the second reference voltage;
wherein a source of the third transistor is coupled to the second reference voltage, and a drain of the third transistor is coupled to the source of the eighth transistor.
16. A circuit according to claim 15, wherein the first transistor is a p-channel MOS (PMOS) transistor;
wherein the second transistor is a PMOS transistor;
wherein the third transistor is an n-channel MOS (NMOS) transistor;
wherein the fourth transistor is a PMOS transistor;
wherein the fifth transistor is a PMOS transistor;
wherein the sixth transistor is an NMOS transistor;
wherein the seventh transistor is an NMOS transistor;
wherein the eighth transistor is an NMOS transistor;
wherein the ninth transistor is an NMOS transistor;
wherein the tenth transistor is an NMOS transistor.
17. A circuit according to claim 16, wherein a gate of the first transistor is coupled to a first control signal;
wherein a gate of the second transistor is coupled to a second control signal, the second control signal being a logical complement of the first control signal;
wherein a gate of the third transistor is coupled to the first control signal;
wherein a gate of the fourth transistor is coupled to the second control signal;
wherein a gate of the fifth transistor is coupled to the first control signal;
wherein a gate of the sixth transistor is coupled to the second control signal.
18. A circuit according to claim 10, wherein the first source-follower circuit keeps a voltage of the first output node in the second state in an approximate range of 100 millivolts to 350 millivolts; and
wherein the second source-follower circuit keeps a voltage of the second output node in the second state in an approximate range of 100 millivolts to 350 millivolts.
19. A circuit to convert a first logic signal having a first range to at least one second logic signal having a second range, comprising:
a first p-channel metal oxide semiconductor (PMOS) transistor having a gate coupled to a first control signal, a source coupled to a first reference voltage, and a drain coupled to a first output node;
a second PMOS transistor having a gate coupled to a second control signal, the second control signal a logical complement of the first control signal, the second PMOS transistor having a source coupled to the first output node and a drain coupled to a second reference voltage;
a first n-channel metal oxide semiconductor (NMOS) transistor having a gate coupled to a first bias voltage, a source coupled to the first output node, and a drain coupled to the first reference voltage;
a second NMOS transistor having a gate coupled to a second bias voltage and a drain coupled to the first output node;
a third NMOS transistor having a gate coupled to the first control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the second NMOS transistor;
wherein a minimum voltage of the first output node when the first control signal is HIGH is within the range 100 millivolts and 350 millivolts, inclusive.
20. A circuit according to claim 19, wherein the circuit is to convert the first logic signal to a pair of complementary second logic signals having the second range, the circuit further comprising:
a third PMOS transistor having a gate coupled to the second control signal, a source coupled to the first reference voltage, and a drain coupled to a second output node;
a fourth PMOS transistor having a gate coupled to the first control signal, a source coupled to the second output node, and a drain coupled to the second reference voltage;
a fourth NMOS transistor having a gate coupled to the first bias voltage, a source coupled to the second output node, and a drain coupled to the first reference voltage;
a fifth NMOS transistor having a gate coupled to the second bias voltage and a drain coupled to the second output node;
a sixth NMOS transistor having a gate coupled to the second control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the fifth NMOS transistor;
wherein a minimum voltage of the second output node when the first control signal is LOW is within the range 100 millivolts to 350 millivolts, inclusive.
21. A circuit according to claim 20, further comprising a flip-flop having an input, a first output, and a second output, the second output a complement of the first output;
wherein the first logic signal is coupled to the input of the flip-flop;
wherein the first output of the flip-flop is coupled to the gate of the second PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the third PMOS transistor;
wherein the second output of the flip-flop is coupled to the gate of the first PMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth PMOS transistor.
22. A circuit according to claim 19, further comprising an inverter having an input coupled to the first logic signal and an output;
wherein the first logic signal is coupled to the gate of the second PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the third PMOS transistor;
wherein the output of the inverter is coupled to the gate of the first PMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth PMOS transistor.
23. A cell of a current steering digital-to-analog converter, comprising:
a current source;
a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to the current source and a drain coupled to a current summing line;
a second PMOS transistor having a source coupled to the current source and a drain coupled to a reference node;
a driver circuit having an input, a first output coupled to a gate of the first PMOS transistor, and a second output coupled to a gate of the second PMOS transistor;
wherein the driver circuit comprises:
a third PMOS transistor having a gate coupled to a first control signal, a source coupled to a first reference voltage, and a drain coupled to the first output of the driver circuit;
a fourth PMOS transistor having a gate coupled to a second control signal, the second control signal being a logical complement of the first control signal, the fourth PMOS transistor having a source coupled to the first output of the driver circuit and a drain coupled to a second reference voltage;
a first n-channel metal oxide semiconductor (NMOS) transistor having a gate coupled to a first bias voltage, a source coupled to the first output of the driver circuit, and a drain coupled to the first reference voltage;
a second NMOS transistor having a gate coupled to a second bias voltage and a drain coupled to the first output of the driver circuit;
a third NMOS transistor having a gate coupled to the first control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the second NMOS transistor;
a fifth PMOS transistor having a gate coupled to the second control signal, a source coupled to the first reference voltage, and a drain coupled to the second output of the driver circuit;
a sixth PMOS transistor having a gate coupled to the first control signal, a source coupled to the second output of the driver circuit, and a drain coupled to the second reference voltage;
a fourth NMOS transistor having a gate coupled to the first bias voltage, a source coupled to the second output of the driver circuit, and a drain coupled to the first reference voltage;
a fifth NMOS transistor having a gate coupled to the second bias voltage and a drain coupled to the second output of the driver circuit;
a sixth NMOS transistor having a gate coupled to the second control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the fifth NMOS transistor;
wherein a minimum voltage of the first output of the driver circuit when the first control signal is HIGH is within the range 100 millivolts to 350 millivolts, inclusive;
wherein a minimum voltage of the second output of the driver circuit when the second control signal is HIGH is within the range 100 millivolts to 350 millivolts, inclusive.
24. A circuit according to claim 23, where the driver circuit further comprises a flip-flop having an input, a first output, and a second output, the second output a complement of the first output;
wherein the input of the driver circuit is the input of the flip-flop;
wherein the first output of the flip-flop is coupled to the gate of the fourth PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the fifth PMOS transistor;
wherein the second output of the flip-flop is coupled to the gate of the third PMOS transistor, the gate of the third NMOS transistor, and the gate of the sixth PMOS transistor.
25. A circuit according to claim 23, where the driver circuit further comprises an inverter having an input and an output;
wherein the input of the inverter is coupled to the input of the driver circuit;
wherein the input of the driver circuit is coupled to the gate of the fourth PMOS transistor, the gate of the sixth NMOS transistor, and the gate of the fifth PMOS transistor;
wherein the output of the inverter is coupled to the gate of the third PMOS transistor, the gate of the third NMOS transistor, and the gate of the sixth PMOS transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device for retaining and dispensing ammunition clips comprising:
a. a top and a bottom;
b. left and right opposing sides;
c. a front and a back, the top, bottom, sides, front and back joined together to form a parallelopiped sized and oriented to retain at least two ammunition clips;
d. an opening through at least one of the top, bottom, sides, front, and back sized and oriented to receive and dispense an ammunition clip; and
e. a first biasing member within the parallelopiped to position an ammunition clip within the parallelopiped adjacent the opening.
2. The device of claim 1, further comprising a bail rotatably mounted to the device, the bail defining a quiescent position over the opening.
3. The device of claim 2, wherein the bail is held in the quiescent position by a biasing spring.
4. The device of claim 2, further comprising a knurled tab on the bail.
5. The device of claim 4, wherein the bail further defines an open position exposing an ammunition clip for dispensing from the device.
6. The device of claim 1, wherein the first biasing member comprises a spring.
7. The device of claim 1, wherein magazines are stacked within the device in a side by side orientation.
8. The device of claim 1, wherein the top, bottom, sides, front and back are formed of a metal alloy.
9. The device of claim 1, wherein the top, bottom, sides, front and back are formed of plastic.
10. The device of claim 1, further comprising a movable barrier moved by the first biasing member within the device.

What is claimed is:

1. A tapered optical fiber bundle, comprising:
a plurality of input fibers formed into a fiber bundle, the fiber bundle being adiabatically tapered, and heavily-fused into an induced cross-sectional shape with minimally deformed cores and no interstitial space between the input fibers.
2. The tapered optical fiber bundle of claim 1, wherein the input fibers are any of multimode, single mode, multiclad and cladding pumped fibers.
3. An optical fiber device, comprising:
a tapered fiber bundle having a plurality of input fibers, adiabatically tapered, and heavily-fused into an induced compact shape with minimally deformed cores and no interstitial space between the input fibers at a cleaved end; and
an output element coupled to the cleaved end.
4. The optical fiber device of claim 3, wherein the output element is another tapered fiber bundle.
5. The optical fiber device of claim 3, wherein the output element is a single optical fiber.
6. The optical fiber device of claim 5, wherein the single optical fiber is a multimode optical fiber.
7. The optical fiber device of claim 6, wherein at least one of the input fibers is terminated to reduce back reflections.
8. The optical fiber device of claim 5, wherein the single optical fiber is a double clad fiber.
9. The optical fiber device of claim 5, wherein the single optical fiber is pre-tapered.
10. The optical fiber device of claim 3, wherein the output element is fusion spliced to the cleaved end.
11. The optical fiber device of claim 9, wherein a spliced junction between the tapered fiber bundle and the output element is post-tapered.
12. The use of the optical fiber device of claim 3 as any one of an optical combiner, an optical splitter, a cladding-pumped fiber laser, and a cladding-pumped optical amplifier.
13. A method of manufacturing an optical fiber device, comprising:
i) positioning a plurality of optical fibers in a predetermined configuration for forming an optimized encircling radius;
(ii) bundling the positioned plurality of optical fibers while controlling the tension applied on individual fibers to result in a fiber bundle with minimized overall diameter;
(iii) heating and pulling the fiber bundle to heavily fuse the fiber bundle in an adiabatically tapered region into an induced shape with no interstitial space between fibers.
14. The method of claim 13, further including twisting the positioned plurality of optical fibers.
15. The method of claim 13, wherein positioning further includes bonding the plurality of optical fibers with an adhesive to secure their positions before fusing and tapering.
16. The method of claim 13, further including cleaving the bundle at the tapered region.
17. The method of claim 16, where the cleaved end of the bundle is reshaped into a desired cross-section by, at least once, fusion splicing the cleaved end to an optical fiber to match its cross-sectional geometry, and re-cleaving the optical fiber bundle.
18. The method of claim 16, further including coupling the cleaved end to an optical system.
19. The method of claim 16, further including fusion splicing the cleaved end to one of a single optical fiber and an output tapered fiber bundle.
20. The method of claim 19, further including pre-tapering of the single optical fiber.
21. The method of claim 19, further including post-tapering of a junction between the tapered fiber bundle and the one of the single optical fiber and the tapered fiber bundle.
22. The method of claim 13, further including at least partial removal of cladding from the plurality of optical fibers.
23. The method of claim 19, further including at least partial removal of cladding from the one of the output optical fiber and the output tapered fiber bundle.
24. The method of claim 19, further including re-coating at least part of a junction between the tapered fiber bundle and the one of the output optical fiber and the output tapered fiber bundle with a coating material.
25. The method of claim 24, wherein the coating material is one of polymer and metallic coatings materials.
26. The method of claim 19, further including heating of the one of the single optical fiber and cladding pumped fiber to diffuse its core to improve the transfer of light from a corresponding singlemode fiber in the input bundle.
27. A star coupler, comprising:
a tapered fiber bundle formed in the midsection of a plurality of fibers, adiabatically tapered, and heavily-fused into an induced compact shape with minimally deformed cores and no interstitial space between the fibers, such that the plurality of fibers form input and output leads on each side of the fused bundle.
28. The star coupler of claim 28, wherein at least one of the input leads is terminated to reduce back reflections.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A baking tin comprising:
at least one holding tray (2) for foodstuffs comprising:
a bottom wall (4),
a plurality of consecutive side walls (5, 6, 7, 8) extending away from the bottom wall (4) to define a holding cavity,
a plurality of corners (9, 10, 11, 12) each defined by two consecutive side walls;
a supporting structure (3) comprising:
at least one through opening (13) delimited by a plurality of consecutive edges (14, 15, 16, 17) to define a seat for receiving said tray (2) in said supporting structure (3),
wherein:
at least one of said corners (9, 10, 11, 12) of said tray (2) comprises an undercut (18),
said supporting structure (3) comprises at least one connecting portion (19) between two consecutive edges (14, 15) of the opening (13),
said undercut (18) is engaged by said connecting portion (19) to join said tray (2) to said supporting structure (3).
2. A baking tin as claimed in claim 1, wherein said undercut (18) comprises a first shoulder (20) defining a base surface for abutment and engagement of the connecting portion (19) between two consecutive edges of the opening (13) and a second shoulder (21) defining a top surface for retaining said connecting portion (19) in the undercut (18).
3. A baking tin as claimed in claim 1, wherein said connecting portion (19) is an integral part of said supporting structure (3) and extends between end portions (14a, 15b) of two consecutive edges (14, 15) of the opening (13) thereby connecting the two consecutive edges, said supporting structure (3) being flat.
4. A baking tin as claimed in claim 1 wherein said supporting structure (3) and tray (2) are made of paper or thin paperboard material for food use.
5. A baking tin as claimed in claim 1 wherein each corner (9, 10, 11, 12) formed between two consecutive side walls comprises an undercut (18); each undercut (18) being susceptible of engagement in a respective connecting portion (19) between two edges of said opening (13).
6. A baking tin as claimed in claim 1 wherein each side wall (5, 6, 7, 8) comprises a first side (5a, 6a, 7a, 8a) connected to the bottom wall (4) and a second side (5b, 6b, 7b, 8b) opposite to the first side and facing an entry section of the holding cavity of the tray (2); said side walls (5, 6, 7, 8) being of trapezoidal shape and having said second sides (5b, 6b, 7b, 8b) of larger size than the respective first sides (5a, 6a, 7a, 8a) to define a frustoconical shape of the tray (2).
7. A baking tin as claimed in claim 1 wherein said edges (14, 15, 16, 17) of the opening (13) in the supporting structure (3) are in contact with said side walls (5, 6, 7, 8) of the tray (2) following engagement of the connecting portion (19) in the undercut (18).
8. A baking tin as claimed in claim 1 wherein two opposite side walls (5, 7) of said side walls (5, 6, 7, 8) of the tray (2) comprise two flaps (22, 23), two other opposite side walls (6, 8) comprising two tailpieces of one piece construction with said flaps (23) to define a multi-layered structure closed towards the outside in which said flaps (23) are folded over and in contact with the tailpieces in turn folded over, which are positioned in parallel and in contact with said side wall (6; 8).
9. A baking tin as claimed in claim 1 wherein said tray (2) is made up of a single sheet of paper material and is obtained starting from a flat blank (24).
10. A flat blank made of paper or thin paperboard material for food use, to make a holding tray for foodstuffs, comprising:
a central panel (25) to define a bottom wall (4) of the tray (2),
a plurality of side panels (26, 27, 28, 29) peripherally connected to the central panel (25) through respective weakening lines (30, 31, 32, 33) to define a plurality of side walls (5, 6, 7, 8) of the tray (2),
at least one (26) of said side panels (26, 27, 28, 29) comprising:
at least one flap (349 to define a corner (9) of the tray (2) in combination with an adjacent side panel (27),
characterized in that said at least one side panel (26) comprising said flap (34) has:
at least two parallel cuts (36) extending between said side panel (26) and flap (34) to define an undercut (18) in said corner (9).
11. A blank as claimed in claim 10, comprising a first pair of said panels (26, 28) and a second pair of said panels (27, 29) that are symmetric with respect to the central panel (25); each side panel (26, 28) of said first pair respectively comprising two flaps (34) and at least two parallel cuts (36) extending between the side panel (26, 28) and the first one of said two flaps (34) and at least two parallel cuts (36) extending between said side panel (26, 28) and the second one of said two flaps (34) to define four undercuts (18) in as many corners (9, 10, 11, 12).
12. A blank as claimed in claim 11, wherein each pair of said cuts (36) defines a foldable portion (37) designed to jut out towards the inside of the tray (2) to define a reinforcing element for said undercuts (18), or alternatively wherein said cuts (36) are defined by material removal from said side panel (26, 28) and from the second one of said flaps (34) so as to define a hole in said walls.
13. A baking tin comprising:
one holding tray for foodstuff made of paper material comprising:
a bottom wall;
a plurality of consecutive side walls extending away from the bottom wall to define a holding cavity:
a plurality of corners each defined by two consecutive side walls;
a flat supporting structure made of paper material and comprising:
a through opening delimited by a plurality of consecutive edges to define a countershaped seat for receiving said tray;
wherein
said corners of said tray comprises an undercut each;
said supporting structure comprises a connecting portion between two consecutive edges of the opening;
said undercut comprises a first shoulder defining a base surface for abutment and engagement of the connecting portion between two consecutive edges of the opening and a second shoulder defining a top surface for retaining said connecting portion in the undercut.