Author: claimsbot

1. A method for manufacturing a non-volatile memory structure, comprising:
providing a substrate comprising an active area and an isolation structure surrounding the active area, wherein the active area comprises a pair of predetermined sourcedrain regions and a middle region therebetween;
forming a first gate and a second gate on the substrate and opposite each other, such that at least one portion of the middle region of the active area is between the first gate and the second gate;
forming an dielectric layer conformally on the substrate;
forming a charge-trapping layer conformally on the dielectric layer;
partially etching the dielectric layer and the charge-trapping layer using a first mask to remain a portion of the dielectric layer and a portion of the charge-trapping layer on the substrate between the first gate and the second gate and on two opposite sidewalls of the first gate and the second gate to serve for a storage node function; and
implanting a first dopant into the pair of predetermined sourcedrain regions of the active area to form a pair of sourcedrain regions through a second mask covering the middle region of the active area, the first and the second gates and the portion of the charge-trapping layer.
2. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first gate and the second gate are each formed to be entirely on the isolation structure and not to contact the active area.
3. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first gate and the second gate are each formed to be partially on the isolation structure and partially overlap a side portion of the middle region of the active area.
4. The method for manufacturing a non-volatile memory structure according to claim 1, further, before forming the dielectric layer, comprising:
implanting a second dopant into the active area to form a pair of LDD regions through a third mask covering the middle region of the active area.
5. The method for manufacturing a non-volatile memory structure according to claim 4, wherein the third mask comprises a photo resist layer.
6. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first mask comprises a photo resist layer.
7. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the second mask comprises a photo resist layer.
8. The method for manufacturing a non-volatile memory structure according to claim 1, further comprising implanting a third dopant into the substrate in the active area to form a well.
9. The method for manufacturing a non-volatile memory structure according to claim 1, further comprising forming a contact etch stop layer over the substrate.
10. The method for manufacturing a non-volatile memory structure according to claim 9, further comprising forming two contacts through the contact etch stop layer and on the sourcedrain regions correspondingly.
11. The method for manufacturing a non-volatile memory structure according to claim 1, wherein, the dielectric layer and the charge-trapping layer are etched through the first mask to further remain on other sidewalls of the first gate and the second gate to serve as spacers.
12. A non-volatile memory structure, comprising:
a substrate including an active area and an isolation structure surrounding the active area, wherein the active area comprises a pair of sourcedrain regions and a middle region between the two sourcedrain regions;
a first gate and a second gate disposed entirely on the isolation structure and opposite each other with the middle region of the active area therebetween;
a dielectric layer disposed on the substrate between the first gate and the second gate and on two opposite sidewalls of the first gate and the second gate; and
a charge-trapping layer disposed on the dielectric layer between the first gate and the second gate and between the source region and the drain region and with the dielectric layer together to serve for a storage node function.
13. The non-volatile memory structure according to claim 12, further comprising a pair of LDD regions each between the dielectric layer and each of the sourcedrain regions.
14. The non-volatile memory structure according to claim 12, further comprising:
a contact etch stop layer covering the charge-trapping layer and the sourcedrain regions.
15. The non-volatile memory structure according to claim 14, further comprising:
two contacts disposed through the contact etch stop layer and on the sourcedrain regions correspondingly.
16. The non-volatile memory structure according to claim 12, wherein the active area comprises a well of a dopant.
17. The non-volatile memory structure according to claim 12, wherein the charge-trapping layer is formed as a conformal layer.
18. The non-volatile memory structure according to claim 12, wherein the charge-trapping layer comprises silicon nitride.
19. The non-volatile memory structure according to claim 12, wherein, the dielectric layer and the charge-trapping layer are further disposed on the tops and other sidewalls of the first gate and the second gate to serve as spacers.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. At a computer system including one or more processors and system memory, the computer system also including a physical graphics processing unit (\u201cGPU\u201d), a method for providing a programmable GPU pipeline to a guest application executing in a child partition of a para-virtualized execution environment, the method comprising:
an act of instantiating a virtual machine session, including instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application;
an act of presenting a virtualized graphics processing unit (\u201cvGPU\u201d) to the guest application, the vGPU executing within the child partition, including presenting a plurality of device driver interfaces (\u201cDDIs\u201d) of a rendering framework to the guest application as part of a user-mode driver (\u201cUMD\u201d) of the vGPU, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize one or more features of the rendering framework, including utilizing at least one of: a domain shader, a hull shader, or a geometric shader; and
an act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU for using one or more of a domain shader, a hull shader, or a geometric shader at the physical GPU; and
an act of the render component scheduling the at least one physical GPU-specific command for execution at the physical GPU.
2. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a domain shader.
3. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a hull shader.
4. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a geometric shader.
5. The method as recited in claim 1, wherein the UMD converts any graphics commands received from the guest application into corresponding physical GPU-specific commands and stores the corresponding physical GPU-specific commands in a command buffer.
6. The method as recited in claim 5, wherein the act of presenting a vGPU to the guest application comprises an act of presenting a vGPU that includes a kernel-mode driver (\u201cKMD\u201d), the KMD being configured to construct a direct memory access buffer from the command buffer.
7. The method as recited in claim 6, wherein the UMD sends a command buffer containing physical GPU-specific compute shader commands to the KMD.
8. The method as recited in claim 6, wherein instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application comprises an act of negotiating one or more communications protocols among the UMD, the KMD, and the render component, including determining a type of composition device to instantiate based on a version of the rendering framework supported by the UMD.
9. The method as recited in claim 1, wherein the plurality of DDIs enable the guest application to send graphics commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize all features of the rendering framework.
10. The method as recited in claim 9, wherein the rendering framework includes DirectX\xae version 11.
11. The method as recited in claim 9, wherein the UMD comprises a new UMD that is enabled to execute concurrent with a legacy UMD, and wherein the render component is enabled to communicate with both the new UMD and the legacy UMD, such that both a new three-dimensional rendering framework and a legacy three-dimensional rendering can be used concurrently.
12. A computer program product for use at a computer system, the computer program product for implementing a method for providing GPU-accelerated computing functionality to a guest application executing in a child partition of a para-virtualized execution environment, the computer program product comprising one or more computer storage media having stored thereon computer-executable instructions that, when executed at a processor, cause the computer system to perform the method, including the following:
instantiate a virtual machine session, including instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application;
present a virtualized graphics processing unit (\u201cvGPU\u201d) to the guest application, the vGPU executing within the child partition, including presenting a plurality of device driver interfaces (\u201cDDIs\u201d) of a rendering framework to the guest application as part of a user-mode driver (\u201cUMD\u201d) of the vGPU, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize one or more features of the rendering framework, including utilizing at least one of: a domain shader, a hull shader, or a geometric shader; and
receive, at a render component executing within the root partition, at least one physical GPU-specific command for using one or more of a domain shader, a hull shader, or a geometric shader at the physical GPU; and
schedule the at least one physical GPU-specific command for execution at the physical GPU.
13. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a domain shader.
14. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a hull shader.
15. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a geometric shader.
16. The computer program product as recited in claim 12, wherein the UMD converts any graphics commands received from the guest application into corresponding physical GPU-specific commands and stores the corresponding physical GPU-specific commands in a command buffer.
17. The computer program product as recited in claim 16, wherein the act of presenting a vGPU to the guest application comprises an act of presenting a vGPU that includes a kernel-mode driver (\u201cKMD\u201d), the KMD being configured to construct a direct memory access buffer from the command buffer.
18. The computer program product as recited in claim 17, wherein the UMD sends a command buffer containing physical GPU-specific compute shader commands to the KMD.
19. The computer program product as recited in claim 12, wherein the plurality of DDIs enable the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize functions of both Direct2D and Direct3D.
20. A computer system, the computer system comprising:
one or more processors;
a graphics processing unit (\u201cGPU\u201d);
system memory; and
one or more computer-readable storage devices having stored thereon computer-executable instructions representing a virtualized graphics processing unit (\u201cvGPU\u201d) and a render component,
wherein the vGPU is configured to execute within the child partition and includes a user-mode driver (\u201cUMD\u201d) configured to:
present a plurality of device driver interfaces (\u201cDDIs\u201d) of a DirectX rendering framework to a guest application executing in a child partition, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the GPU to utilize one or more of: a domain shader, a hull shader, or a geometric shader of the DirectX rendering framework; and
convert vGPU-specific commands to GPU-specific commands; and

wherein the a render component is configured to execute in a root partition and to receive at least one GPU-specific command from the vGPU and to schedule the at least one physical GPU-specific command for execution at the GPU while using one or more of: a domain shader, a hull shader, or a geometric shader of the DirectX rendering framework.

1. An apparatus comprising:
an adjustable voltage source;
a voltage-to-current converter is coupled to the adjustable voltage source and that provides a reference current; and
an adjustable impedance network that is coupled to the voltage-to-current converter, wherein the adjustable impedance network includes:
a first set of resistors that are each formed of a first material in a substrate;
a second set of resistors that are each formed of a second material in the substrate, wherein resistors from each of the first and second sets of resistors are arranged in a pattern in parallel to one another so as to reduce external thermal gradient effects; and
a serpentine heater resistor that is formed over a portion of each of the resistors from the first and second sets.
2. The apparatus of claim 1, wherein the adjustable impedance network further comprises:
a field oxide layer;
a resistor body that includes the first and second sets of transistors formed over the field oxide layer;
a first metallization layer formed over the resistor body, wherein the first metallization layer includes a Faraday shield;
a second metallization layer that is formed over the first metallization layer, wherein the second metallization layer includes the serpentine heater; and
a third metallization layer formed over the second metallization layer, wherein the third metallization layer includes a heat spreader.
3. The apparatus of claim 1, wherein the first set of resistors are each formed of high-sheet rho (HSR) polysilicon, and wherein the second set of resistors are each formed of medium-sheet rho (MSR) polysilicon.
4. The apparatus of claim 3, wherein the voltage-to-current converter further comprises:
a first differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the first differential amplifier is coupled to the adjustable impedance network;
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the output terminal of the first differential amplifier, and wherein the first passive electrode of the first transistor provides the reference current, and wherein the second passive electrode of the first transistor is coupled to the second output terminal of the first differential amplifier;
a second differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the second differential amplifier is coupled to the adjustable impedance network; and
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the output terminal of the second differential amplifier, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor, and wherein the second passive electrode of the second transistor is coupled to the second output terminal of the second differential amplifier.
5. The apparatus of claim 4, wherein the voltage-to-current converter further comprises a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the third transistor is coupled to the output terminal of the second differential amplifier, and wherein the second first electrode of the third transistor is coupled to the second input terminal of the second differential amplifier.
6. The apparatus of claim 1, wherein the impedance network further comprises:
a plurality of trim sets coupled in series with one another, wherein each trim set includes:
a first resistor from the first set of resistors;
a second resistor from second set of resistors, wherein the first and second resistors are coupled in series with one another;
a first trim transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first and second passive electrodes of the first trim transistor are coupled to the first resistor, and wherein the control electrode of the first trim transistor receives at least one of a plurality of trim signals;
a second trim transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first and second passive electrodes of the second trim transistor are coupled to the second resistor; and
an inverter that is coupled to the control electrode of the second trim transistor and that receive the at least one of a plurality of trim signals; and
a faraday shield that separates the serpentine heater resistor from the resistors of the plurality of trim sets.
7. An apparatus comprising:
an adjustable voltage source including:
a plurality of reference resistors that are coupled in series with one another; and
a plurality of reference transistors, wherein each reference transistor includes first and second passive electrodes that are coupled to at least one of the reference resistors, and wherein each reference transistor includes a control electrode that receives one of a plurality of reference signals;
a voltage-to-current converter is coupled to the adjustable voltage source and that provides a reference current; and
an adjustable impedance network that is coupled to the voltage-to-current converter, wherein the adjustable impedance network includes:
a first set of resistors that are each formed of a first material in a substrate;
a second set of resistors that are each formed of a second material in the substrate, wherein resistors from each of the first and second sets of resistors are arranged in a pattern in parallel to one another so as to reduce external thermal gradient effects; and
a serpentine heater resistor that is formed over a portion of each of the resistors from the first and second sets.
8. The apparatus of claim 7, wherein the adjustable impedance network further comprises:
a field oxide layer;
a resistor body that includes the first and second sets of transistors formed over the field oxide layer;
a first metallization layer formed over the resistor body, wherein the first metallization layer includes a Faraday shield;
a second metallization layer that is formed over the first metallization layer, wherein the second metallization layer includes the serpentine heater; and
a third metallization layer formed over the second metallization layer, wherein the third metallization layer includes a heat spreader.
9. The apparatus of claim 7, wherein the first set of resistors are each formed of HSR polysilicon, and wherein the second set of resistors are each formed of MSR polysilicon.
10. The apparatus of claim 9, wherein the voltage-to-current converter further comprises:
a first differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the first differential amplifier is coupled to the adjustable impedance network;
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the output terminal of the first differential amplifier, and wherein the first passive electrode of the first transistor provides the reference current, and wherein the second passive electrode of the first transistor is coupled to the second output terminal of the first differential amplifier;
a second differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the second differential amplifier is coupled to the adjustable impedance network; and
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the output terminal of the second differential amplifier, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor, and wherein the second passive electrode of the second transistor is coupled to the second output terminal of the second differential amplifier.
11. The apparatus of claim 10, wherein the voltage-to-current converter further comprises a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the third transistor is coupled to the output terminal of the second differential amplifier, and wherein the second first electrode of the third transistor is coupled to the second input terminal of the second differential amplifier.
12. The apparatus of claim 7, wherein the impedance network further comprises:
a plurality of trim sets coupled in series with one another, wherein each trim set includes:
a first trim resistor from the first set of resistors;
a second trim resistor from second set of resistors, wherein the first and second resistors are coupled in series with one another;
a first trim transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first and second passive electrodes of the first trim transistor are coupled to the first trim resistor, and wherein the control electrode of the first trim transistor receives at least one of a plurality of trim signals;
a second trim transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first and second passive electrodes of the second trim transistor are coupled to the second trim resistor; and
an inverter that is coupled to the control electrode of the second trim transistor and that receive the at least one of a plurality of trim signals; and
a faraday shield that separates the serpentine heater resistor from the trim resistors of the plurality of trim sets.
13. An apparatus comprising:
an adjustable voltage source including:
a plurality of reference resistors that are coupled in series with one another; and
a plurality of NMOS reference transistors, wherein each NMOS reference transistor is coupled to at least one of the reference resistors at its source and drain and that receives one of a plurality of reference signals at its gate;

a voltage-to-current converter is coupled to the adjustable voltage source and that provides a reference current; and
an adjustable impedance network that is coupled to the voltage-to-current converter, wherein the adjustable impedance network includes:
a field oxide layer;
a first set of resistors that are each formed of HSR polysilicon within a resistor body that is formed over the field oxide layer;
a second set of resistors that are each formed of MSR polysilicon within the resistor body, wherein resistors from each of the first and second sets of resistors are arranged in a pattern in parallel to one another so as to reduce external thermal gradient effects; and
a first metallization layer formed over the resistor body, wherein the first metallization layer includes a Faraday shield;
a serpentine heater resistor that is formed over a portion of each of the resistors from the first and second sets within a second metallization layer that is formed over the first metallization layer; and
a third metallization layer formed over the second metallization layer, wherein the third metallization layer includes a heat spreader.
14. The apparatus of claim 13, wherein the voltage-to-current converter further comprises:
a first differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the first differential amplifier is coupled to the adjustable impedance network;
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the output terminal of the first differential amplifier, and wherein the first passive electrode of the first transistor provides the reference current, and wherein the second passive electrode of the first transistor is coupled to the second output terminal of the first differential amplifier;
a second differential amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first differential amplifier is coupled to the adjustable voltage source, and wherein the second input terminal of the second differential amplifier is coupled to the adjustable impedance network; and
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the output terminal of the second differential amplifier, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor, and wherein the second passive electrode of the second transistor is coupled to the second output terminal of the second differential amplifier.
15. The apparatus of claim 14, wherein the voltage-to-current converter further comprises a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the third transistor is coupled to the output terminal of the second differential amplifier, and wherein the second first electrode of the third transistor is coupled to the second input terminal of the second differential amplifier.
16. The apparatus of claim 13, wherein the impedance network further comprises a plurality of trim sets coupled in series with one another, wherein each trim set includes:
a first trim resistor from the first set of resistors;
a second trim resistor from second set of resistors, wherein the first and second resistors are coupled in series with one another;
a first NMOS trim transistor that is coupled to the first trim resistor at its source and drain and that receives at least one of a plurality of trim signals at its gate;
a second NMOS trim transistor that is coupled to the second trim resistor at its source and drain; and
an inverter that is coupled to the gate of the second NMOS trim transistor and that receive the at least one of a plurality of trim signals.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A phase change memory device comprising:
a memory array including a plurality of phase change memory cells;
a write boosting circuit which boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and which boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode; and
a write driver which is driven by the first control voltage in the first operation mode and which writes data to a selected memory cell of the memory array.
2. The phase change memory device of claim 1, wherein the control signal is a write enable signal and the first voltage is a supply voltage.
3. The phase change memory device of claim 1, wherein the first operation mode is a write operation mode, the second operation mode is a read operation mode, and the third operation mode is a standby mode.
4. The phase change memory device of claim 1, wherein the first control voltage is a high voltage sufficient to change the state of a phase change material of the selected memory cell, and the second control voltage is lower than the first control voltage and higher than the first voltage.
5. The phase change memory device of claim 1, further comprising:
a column boosting controller which boosts the first voltage and outputs a third control voltage in response to the control signal in the first operation mode and outputs the first voltage in response to the control signal in the second operation mode and the third operation mode; and
a column decoder which is driven by the third control voltage in the first operation mode and the first voltage in the second operation mode, and which selects a bit line connected to the selected memory cell.
6. The phase change memory device of claim 5, wherein the column boosting controller comprises:
a column boosting circuit which generates the third control voltage in response to the control signal in the first operation mode, and which boosts the first voltage and outputs a fourth control voltage in the second operation mode; and
a column selection unit which selectively outputs the third control voltage or the first voltage in response to the control signal.
7. The phase change memory device of claim 6, wherein the third control voltage is a high voltage sufficient to activate a switch for selecting the bit line connected to the selected memory cell, and
wherein the fourth control voltage is lower than the third control voltage and higher than the first voltage.
8. The phase change memory device of claim 1, further comprising:
a row boosting controller which boosts the first voltage and outputs a fifth control voltage in response to the control signal in the first operation mode, and which outputs the first voltage in response to the control signal in the second operation mode and the third operation mode; and
a row decoder which is driven by the fifth control voltage in the first operation mode and the first voltage in the second operation mode, and which selects a word line connected to the selected memory cell.
9. The phase change memory device of claim 8, wherein the row boosting controller comprises:
a row boosting circuit which generates the fifth control voltage in response to the control signal in the first operation mode, and which boosts the first voltage and outputs a sixth control voltage in the second operation mode; and
a row selector which selectively outputs the fifth control voltage or the first voltage in response to the control signal.
10. The phase change memory device of claim 9, wherein the fifth control voltage is a high voltage sufficient to activate the word line connected to the selected memory cell, and
wherein the sixth control voltage is lower than the fifth control voltage and higher than the first voltage.
11. The phase change memory device of claim 1, wherein each of the memory cells includes a phase change element connected in series with a transistor, and wherein the phase change element includes a phase change material including germanium (Ge), antimony (Sb) and tellurium (Te).
12. A phase change memory device, comprising a memory array including a plurality of phase change memory cells, a write driver which writes data to a selected memory cell among the memory cells, a column decoder which selects a bit line connected to the selected memory cell, and a row decoder which selects a word line connected to the selected memory cell,
wherein, in a first operation mode, the write driver, the column decoder and the row decoder are driven by at least one boosted voltage which is greater than a first voltage, and
where, in a second operation mode and a third operation mode, the column decoder and the row decoder are driven by the first voltage.
13. The phase change memory device of claim 12, further comprising:
boosting circuits respectively corresponding to the write driver, the column decoder and the row decoder and respectively generating the control voltages in response to a control signal; and
selectors respectively corresponding to the column decoder and the row decoder, each selecting one of a corresponding control voltage and the first voltage in response to the control signal, and applying the selected voltage to the column decoder and the row decoder.
14. The phase change memory device of claim 13, wherein the boosting circuits boost the first voltage and generate sub control voltages in the second operation mode and the third operation mode, and
wherein the sub control voltages are lower than the control voltages and greater than the first voltage.
15. The phase change memory of claim 13, wherein the control signal is a write enable signal which is activated in the first operation mode and deactivated in the second operation mode and the third operation mode, and
wherein the first operation mode is a write operation mode, the second operation mode is a read operation mode and the third operation mode is a standby mode.
16. A phase change memory device which comprises a memory array including a plurality of phase change memory cells, a write driver which writes data to the memory array, a column decoder which selects a bit line of a memory cell to which the data is written, and a row decoder which selects a word line of a memory cell to which the data is written, wherein the write driver, the column decoder, and the row decoder are respectively driven by separate voltage generators.
17. The phase change memory device of claim 16, wherein the voltage generators generate control voltages obtained by boosting a first voltage in a first operation mode, and generate sub control voltages lower than the control voltages and higher than the first voltage in a second operation mode and a third operation mode.
18. The phase change memory device of claim 17, further comprising selectors respectively connected to the column decoder and the row decoder, each selecting one of a corresponding control voltage and the first voltage in response to a control signal, and applying the selected voltage to the column decoder and the row decoder.
19. The phase change memory device of claim 18, wherein the control signal is a write enable signal which is activated in the first operation mode and deactivated in the second operation mode and the third operation mode, and
wherein the first operation mode is a write operation mode, the second operation mode is a read operation mode and the third operation mode is a standby mode.
20. A phase change memory device which comprises a memory array including a plurality of phase change memory cells each composed of a phase change element and a cell transistor, a plurality column selection transistors each connecting a bit line connected to the phase change memory cells to a corresponding data line, and a control node connecting the data line to a sense amplifier,
wherein, in a first operation mode, corresponding control voltages among control voltages obtained by boosting a first voltage are respectively applied to the control node, a gate of the column selection transistor, and a gate of a cell transistor of a selected phase change memory cell.
21. The phase change memory device of claim 20, wherein, in a second operation mode, the first voltage is applied to the gate of the column selection transistor and the gate of the cell transistor, and a clamp voltage is applied to the control node, and
wherein, in a third operation mode, a ground voltage is applied to the gate of the column selection transistor and the gate of the cell transistor and the first voltage is precharged to the control node.
22. The phase change memory device of claim 21, further comprising:
a write driver which is driven by a corresponding control voltage and which controls the control node to write data to the phase change memory cell;
a column decoder which is driven by a corresponding control voltage or the first voltage and which controls the column selection transistor; and
a row decoder which is driven by a corresponding control voltage or the first voltage and which controls the cell transistor.
23. The phase change memory device of claim 22, further comprising:
boosting circuits respectively corresponding to the write driver, the column decoder and the row decoder, and respectively generating the control voltages in response to a control signal; and
selectors respectively corresponding to the column decoder and the row decoder, which select one of a control voltage and the first voltage in response to the control signal, and which apply the selected voltage to the column decoder and the row decoder.
24. The phase change memory device of claim 23, wherein the boosting circuits boost the first voltage and generate sub control voltages in the second operation mode and the third operation mode, and
wherein the sub control voltages are lower than the control voltages and higher than the first voltage.
25. The phase change memory device of claim 24, wherein the control signal is a write enable signal which is activated in the first operation mode, and is deactivated in the second operation mode and the third operation mode, and
wherein the first operation mode is a write operation mode, the second operation mode is a read operation mode, and the third operation mode is a standby mode.